CN116114395A - 三维存储器及其制造方法 - Google Patents

三维存储器及其制造方法 Download PDF

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Publication number
CN116114395A
CN116114395A CN202180017818.2A CN202180017818A CN116114395A CN 116114395 A CN116114395 A CN 116114395A CN 202180017818 A CN202180017818 A CN 202180017818A CN 116114395 A CN116114395 A CN 116114395A
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China
Prior art keywords
layer
channel
dimensional memory
dielectric
charge storage
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Pending
Application number
CN202180017818.2A
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English (en)
Inventor
杜小龙
高庭庭
夏志良
孙昌志
刘佳裔
刘小欣
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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Application filed by Yangtze Memory Technologies Co Ltd filed Critical Yangtze Memory Technologies Co Ltd
Publication of CN116114395A publication Critical patent/CN116114395A/zh
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

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  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

本申请提供了一种三维存储器及其制造方法，该三维存储器包括堆叠结构，堆叠结构包括第一堆叠层和第二堆叠层，第一堆叠层包括交替堆叠的控制栅极层和第一介质层，沿相同的堆叠的方向，第二堆叠层包括交替堆叠的顶部选择栅极层和第二介质层；多个沟道结构，沟道结构贯穿堆叠结构，沟道结构包括电荷存储层，电荷存储层包括沿堆叠的方向间断设置的多个电荷存储部分，电荷存储部分设于相邻的所述第一介质层之间；以及至少一个隔离结构，贯穿顶部选择栅极层且位于相邻的沟道结构之间。本申请实施方式提供三维存储器及制造方法能够维持顶部选择栅切线的工艺窗口不变，减少存储密度损失。

Description

PCT国内申请，说明书已公开。

Claims (44)

  1. PCT国内申请，权利要求书已公开。
CN202180017818.2A 2021-09-06 2021-09-06 三维存储器及其制造方法 Pending CN116114395A (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2021/116668 WO2023029036A1 (zh) 2021-09-06 2021-09-06 三维存储器及其制造方法

Publications (1)

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CN116114395A true CN116114395A (zh) 2023-05-12

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CN202180017818.2A Pending CN116114395A (zh) 2021-09-06 2021-09-06 三维存储器及其制造方法

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US (1) US20230071503A1 (zh)
CN (1) CN116114395A (zh)
WO (1) WO2023029036A1 (zh)

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9419012B1 (en) * 2015-06-19 2016-08-16 Sandisk Technologies Llc Three-dimensional memory structure employing air gap isolation
US10516025B1 (en) * 2018-06-15 2019-12-24 Sandisk Technologies Llc Three-dimensional NAND memory containing dual protrusion charge trapping regions and methods of manufacturing the same
JP7279202B2 (ja) * 2019-06-17 2023-05-22 長江存儲科技有限責任公司 ゲート線スリットがない３次元メモリデバイスおよびそれを形成するための方法
CN113745235B (zh) * 2019-06-17 2024-04-26 长江存储科技有限责任公司 具有在栅极线缝隙中的支撑结构的三维存储器件和用于形成其的方法
CN110741475A (zh) * 2019-08-29 2020-01-31 长江存储科技有限责任公司 三维存储器及其制造方法
KR20210028759A (ko) * 2019-09-03 2021-03-15 삼성전자주식회사 반도체 장치
CN112259549A (zh) * 2020-10-19 2021-01-22 长江存储科技有限责任公司 一种半导体器件的制造方法及半导体器件

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US20230071503A1 (en) 2023-03-09
WO2023029036A1 (zh) 2023-03-09

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