WO2015124551A1 - Verfahren zur herstellung von halbleiterbauelementen und halbleiterbauelement - Google Patents
Verfahren zur herstellung von halbleiterbauelementen und halbleiterbauelement Download PDFInfo
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- WO2015124551A1 WO2015124551A1 PCT/EP2015/053278 EP2015053278W WO2015124551A1 WO 2015124551 A1 WO2015124551 A1 WO 2015124551A1 EP 2015053278 W EP2015053278 W EP 2015053278W WO 2015124551 A1 WO2015124551 A1 WO 2015124551A1
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- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1892—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof methods involving the use of temporary, removable substrates
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H01L31/0304—Inorganic materials including, apart from doping materials or other impurities, only AIIIBV compounds
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- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Definitions
- the present application relates to a method for
- gallium arsenide or indium phosphide light-emitting diodes often find on the
- An object is to provide a method with which in a simple and reliable way semiconductor devices
- Semiconductor device can be specified with an increased efficiency.
- the invention relates to a method for producing a plurality of, in particular, optoelectronic semiconductor components.
- the method comprises a step in which a semiconductor layer sequence
- the semiconductor layer sequence has an active region provided for generating and / or receiving radiation.
- the active region preferably has a quantum structure.
- quantum structure encompasses in particular any structure in which charge carriers by confinement quantize their
- quantum structure does not include information about the
- the active region may have a multiple quantum structure with a
- the semiconductor layer sequence comprises, for example, a first semiconductor layer and a second one
- the first semiconductor layer is n-type and the second semiconductor layer is p-type or vice versa.
- the method comprises a step in which a first connection layer on the first semiconductor layer facing away from the second side
- Semiconductor layer is formed. The first
- Connection layer is particularly after completion of the example epitaxial deposition of
- the first connection layer is thus arranged outside the semiconductor layer sequence.
- the method comprises a step in which a plurality of recesses is formed through the semiconductor layer sequence. In a direction perpendicular to a main plane of the
- Semiconductor layer sequence can be removed in the later region of the recesses, even before the first connection layer is applied.
- the method comprises a step in which a conduction layer in the
- the conductor layer is in particular for producing an electrically conductive
- connection provided between the first semiconductor layer and the first connection layer.
- the conductor layer adjoins directly to the first connection layer, in particular in the recesses.
- the method comprises a step in which a singulation into a plurality of semiconductor components takes place.
- the at least one recess is completely in plan view of the semiconductor body of the
- the recesses are therefore not on the edge of the semiconductor body.
- the semiconductor layer sequence can already be divided into individual semiconductor bodies, for example by means of isolation trenches which delimit the individual semiconductor bodies in the lateral direction.
- the separation trenches can be formed in a common step with the recesses.
- the recesses and the recesses can be formed in a common step with the recesses.
- Separation trenches are formed in successive production steps.
- the formation of the recesses and / or the separation trenches takes place, for example, by means of wet-chemical or dry-chemical etching. Furthermore, the
- a semiconductor layer sequence having a first semiconductor layer, a second semiconductor layer and one between the first semiconductor layer and the second semiconductor layer
- a first connection layer will be on the first one
- a plurality of recesses is formed through the semiconductor layer sequence.
- a conductive layer is formed in the recesses for establishing an electrically conductive connection between the first semiconductor layer and the first terminal layer
- Recesses emerges and the at least one recess in plan view of the semiconductor body completely from the
- Semiconductor body is surrounded.
- arranged conductor layer may be an electrical
- a metal grid on the first semiconductor layer for current spreading and electrical contacting of the first semiconductor layer can be dispensed with.
- the semiconductor bodies may each have more than one recess. In the case of a radiation-emitting component, it is thus easier to homogenize in a lateral direction
- a growth substrate for the semiconductor layer sequence is removed before the formation of the plurality of recesses.
- a laser stripping process can take place. For example, the removal of the
- Terminal layer and forming the plurality of
- Growth substrate is removed is also referred to as a thin-film semiconductor device.
- the method comprises a step in which a separating layer is applied for electrical insulation between the active region and the conductor layer, which covers the side surfaces of the recesses at least at the level of the second semiconductor layer and the active region.
- the semiconductor layer sequence and the conductor layer can also be carried out without a separation layer, for example by an air gap, by a Schottky contact, by the design of a contact with an ohmic characteristic and a high contact resistance, or by a targeted local change in the doping of
- Semiconductor layer sequence such as by ion implantation.
- material for the separating layer is applied over the whole area to the semiconductor layer sequence with the cutouts.
- the material for the release layer is applied only in places, especially in the area of the recesses.
- the material applied in particular over the entire area can be removed by means of a direction-selective etching process such that only obliquely or perpendicularly to the main extension plane of the semiconductor layers
- the material of the release layer is exposed to the entire surface of the etching process.
- no mask is used by means of which the regions in which material of the separating layer is removed and the regions in which material of the separating layer remains on the semiconductor layer sequence are defined.
- the direction-selective etching method has a higher etch rate, in particular in the vertical direction, than in the lateral direction.
- a direction-selective etching method a dry-chemical etching method is suitable.
- the etching rate is in the vertical direction
- further material of the separating layer is removed in a subsequent further direction-selective etching method, and the first semiconductor layer is partially in the recesses
- the semiconductor layer can be exposed in a partial region of the side surfaces of the recesses.
- the subarea adjoins the
- Radiation passage surface can be the material of
- the further connection layer is exposed by the further direction-selective etching method.
- the further direction-selective etching method removes dielectric material, in particular only dielectric material.
- a first insulating layer having openings wherein the recesses are formed so that they are in plan view overlap the semiconductor layer sequence with the openings.
- the recesses through the semiconductor layer sequence run completely within the openings in the first insulation layer. For the exposure of the first connection layer, it is therefore not necessary, after the
- the openings may be in the same
- Manufacturing step are formed as recesses of the insulating layer, is carried out by an electrical contacting of the second semiconductor layer.
- the method comprises a step in which a masking layer with a plurality of openings is applied to the semiconductor layer sequence and each one before the application of the line layer
- Recess in plan view is disposed completely within one of the plurality of openings.
- the semiconductor layer is locally free of the masking layer laterally of the recesses.
- Masking layer is for example a photoresist.
- the openings taper with increasing distance from the semiconductor layer sequence.
- Material for the conductor layer is deposited, in particular, with a main deposition direction, which runs obliquely to the vertical direction, so that material deposited in the openings of the conductor layer overlaps in plan view with material of the conductor layer deposited on the masking layer. In the openings, therefore, the material of the conductor layer partially covers the first semiconductor layer, in particular the side of the
- the formation of the conduction layer can also take place in two or more substeps.
- the conduction layer can also take place in two or more substeps. For example, the
- Conductive layer can also be formed so that the
- Recesses are completely filled, for example by means of a galvanic deposition and optionally a loopback of the electrodeposited material.
- the conduction layer can also be full-surface
- a TCO (transparent conductive oxide) material can be used for the conductor layer.
- the conductor layer can also be used on the large area
- a covering layer is applied to the conductor layer.
- Covering layer serves in particular for a subsequent material removal of the first semiconductor layer as a mask.
- Covering layer can also serve as a mask itself the conductive layer, in particular when the conductive layer has a sufficient resistance to the process for material removal.
- Abtrag compiler for example, a plasma etching, such as with a halogen-containing plasma is suitable
- a conductive layer containing nickel as a hard mask For example, a conductive layer containing nickel as a hard mask.
- a wet chemical process for example, a wet chemical process
- the cover layer is applied in particular before the removal of the masking layer.
- the covering layer is therefore applied both in the openings of the masking layer and on the masking layer itself. After removal of the masking layer, the cover layer remains only in areas not covered by the masking layer.
- an absorbent layer can be provided in places
- the contact layer is in particular for the improved contactability of the first
- the contact layer is doped at least twice as high as that adjacent to the contact layer
- the method comprises a step in which the semiconductor layer sequence is attached to a carrier, in particular between the formation of the first connection layer and the formation of the first connection layer
- the carrier serves in particular for the mechanical stabilization of the semiconductor layer sequence.
- the attachment can take place, for example, by means of a connecting layer, for example a solder layer or an adhesive layer.
- a semiconductor device according to at least one
- Semiconductor layer arranged, for generating and / or for
- the semiconductor body has at least one
- a side surface of the at least one recess has a partial region in which the conductive layer adjoins the first semiconductor layer.
- An electrically conductive contact between the first semiconductor layer and the conductor layer can therefore take place via the side surface of the recess.
- no electrically insulating material, in particular no separation layer is provided.
- the line layer is partially on a side facing away from the active area
- Semiconductor layer takes place in this case as an alternative or in addition to contacting via the side surface of
- the first semiconductor layer on a contact layer.
- the contact layer has a higher doping than a material of the first semiconductor layer adjoining the contact layer.
- the contact layer limits the first
- Semiconductor device is the contact layer in plan view of the semiconductor device only below the
- Radiation absorption by the contact layer can be so
- Semiconductor device is between the first
- Connection layer and the second semiconductor layer arranged a second connection layer for electrically contacting the second semiconductor layer.
- Terminal layer or a sub-layer thereof may be used as a
- the mirror layer for the radiation to be generated or received in the active region to be formed.
- the mirror layer has a reflectivity of at least 60%, preferably at least 80%, for a peak wavelength of the radiation to be generated or to be received.
- the second connection layer is expediently electrically insulated from the first connection layer, for example by means of an insulation layer arranged between the first connection layer and the second connection layer.
- the semiconductor body is in plan view of the
- Semiconductor device free of a contact for the external electrical contacting for example, a bonding pad for a wire bond.
- the arrangement of the contacts can be selected within wide limits. For example, that can
- Front side is understood to mean that side on which the
- Radiation passage surface of the semiconductor body is formed.
- the manufacturing method described above is particularly suitable for the production of the semiconductor device. Therefore, features implemented in connection with the method can also be used for the semiconductor component and vice versa.
- Figures 1A to IN an embodiment of a method for producing a semiconductor device based on schematically shown in sectional view
- FIGS. 2A and 2B each show a further one
- FIGS. 3 to 5 each show an exemplary embodiment of a semiconductor component.
- FIGS. 1A to 1I An exemplary embodiment of a method for producing, in particular, will be described with reference to FIGS. 1A to 1I
- Radiation emitter such as light-emitting diodes or
- Radiation receiver such as photodiodes or solar cells.
- a semiconductor layer sequence 2 with an active region 25 provided for generating and / or receiving electromagnetic radiation is provided.
- the active region 25 is designed to generate radiation and has a
- the quantum structure includes a
- a barrier layer 252 is arranged.
- the active one is shown in FIG. 1A.
- the area can also have more than two quantum layers
- the active region 25 is between a first semiconductor layer 21 and a second one
- Semiconductor layer 22 is arranged. In the shown
- the contact layer 210 serves for the simplified electrical contacting of the first
- the contact layer 210 expediently has a higher
- Doping as the adjacent to the contact layer material of the first semiconductor layer for example a
- contact layer is not mandatory.
- Semiconductor layer 22 are of the conductivity type
- the deposition of the semiconductor layer sequence 2 takes place on a growth substrate 200, for example by means of
- MOVPE metal-organic epitaxial deposition
- the semiconductor layer sequence, in particular the active region 25, preferably contains a III-V compound semiconductor material.
- III-V compound semiconductor materials are known for
- a structuring 26 having a plurality of depressions 260 is formed (FIG. 1B).
- the structuring is particularly useful for reducing waveguide effects and for
- Structuring 26 may be in the form of, for example
- Micro prisms are formed. However, other embodiments are conceivable, for example, an irregular structuring such as a roughening.
- a first insulation layer 71 is formed on the semiconductor layer sequence 2.
- the first insulation layer 71 has recesses 711. The electrical contacting of the second semiconductor layer takes place only via the
- the second connection layer 32 has
- the first sub-layer is formed in the recesses 711 and serves the electrical
- the first insulating layer is not absolutely necessary. It is also conceivable that the second connection layer
- the first sub-layer 321 is not explicitly shown for the purpose of simplified illustration.
- Insulation layer is used in the context of the present application, only the simplified reference to individual layers and does not imply any order in the production of
- second insulation layer does not necessarily require the presence of a first insulation layer.
- the second connection layer 32 also has recesses 325. In these recesses is the second
- Semiconductor layer 22 free of metallic material.
- a first connection layer 31 is applied to the second connection layer 32.
- the second connection layer 32 extends partially between the first connection layer 31 and the second semiconductor layer 22.
- Terminal layer is a second insulation layer 72
- Insulation layer covers the semiconductor layer sequence over its entire surface. Furthermore, the second insulation layer adjoins the first insulation layer 71 in the recesses 325 of the second connection layer.
- connection layer 31 Semiconductor layer sequence 2 over the entire surface.
- the semiconductor layer sequence is fastened to a carrier 5 by means of a connection layer 55, for example a solder layer or an electrically conductive adhesive layer.
- the second semiconductor layer 22 is arranged on the side of the semiconductor layer sequence facing the carrier 5 (FIG. 1D).
- the carrier serves for the mechanical stabilization of the
- Attachment to the carrier is already removed.
- the semiconductor layer sequence can be stabilized when attached to the carrier, for example by a temporary subcarrier.
- recesses 29 which extend completely through the semiconductor layer sequence 2 are formed by the side facing away from the carrier 5. At the same time separation trenches 28 for
- the recesses and the separation trenches are in the lateral direction of each other
- Semiconductor bodies are each surrounded along the entire circumference of material of the semiconductor body.
- the recesses are each surrounded along the entire circumference of material of the semiconductor body.
- flanks 29 and / or separating trenches 28 may have vertical flanks, that is to say flanks running parallel to the vertical direction. Alternatively, the flanks can be inclined to the vertical direction
- cross-section of the recesses 29 and / or separating trenches 28 tapers in the direction of the carrier 5.
- the recesses 29 overlap in the semiconductor layer sequence with the recesses 325 of the second connection layer 325.
- the recesses 29 extend completely within the recesses 325 of the second connection layer 325.
- material for a release layer 73 is deposited by means of a conforming process
- CVD chemical vapor deposition
- a conformally deposited layer follows in its course the shape of the underneath
- the material of the separating layer covers the entire semiconductor layer sequence, in particular the side surfaces of the recesses 29 and the separating trenches 28.
- the separating layer 73 is subjected to a direction-selective etching process over its entire area, so that surfaces parallel to the main plane of extension of the
- Semiconductor layers of the semiconductor layer sequence 2 run are freed from the material of the release layer.
- Separating layer 73 is thus only at the obliquely or perpendicular to the main extension plane
- Recesses electrical insulation of the side surfaces of the recesses 29 causes, without this a
- Lithography method is required. Rather, the formation of the separation layer 73 occursssj ustierend. By dispensing with two mutually adjusted lithography steps for the formation of the coated recesses, the lateral extent of the recesses 29 can be reduced. Thus, the proportion of the active region 25, which is lost by the formation of the recesses 29 reduces.
- Semiconductor layer sequence 2 a masking layer 8, for example, a photoresist layer applied.
- Masking layer is formed such that in the
- Masking layer openings 81 are formed, wherein the recesses 29 in plan view of the
- Openings 81 are arranged. As the distance from the semiconductor layer sequence 2 increases, the cross section of the openings 81 decreases, so that an undercut region is created.
- the further direction-selective method likewise has a higher etch rate in the vertical direction than in the lateral direction.
- the material covering the side surfaces 29 is thereby removed in the vertical direction.
- the side surfaces 290 of the recesses 29 each have a portion 291, in which the first
- Semiconductor layer 21 is exposed.
- the partial area adjoins, in particular, the contact layer 210.
- Terminal layer 31 is exposed.
- material of the second insulation layer 72 is removed in the region of the recesses 29 in this step.
- the exposure of the first connection layer 31 takes place in the recesses 325 of the second connection layer.
- Conduction layer 4 covers the side surfaces 290 of FIG.
- the deposition of the conductive layer takes place with a
- Conductive layer are covered in plan view of the semiconductor layer sequence of the masking layer 8. The deposited on the first semiconductor layer material of the conductor layer 4 and on the
- Masking layer deposited material overlap so partially in plan view.
- the cover layer 74 completely covers the conductor layer 4.
- the cover layer 74 can now be used as a mask for a
- Material removal of the semiconductor layer sequence 2 serve ( Figure IM).
- the contact layer 210 can be removed in regions, so that they only
- Radiation absorption is reduced by the contact layer 210.
- good electrical contactability and simultaneously reduced absorption losses are achieved in a simple and reliable manner.
- no additional photolithographic step is required for this purpose.
- Semiconductor layer sequence may further include a
- Auskoppel Modelltechnik 27 are formed, for example in the form of a roughening.
- a passivation layer 75 is optionally applied to the semiconductor layer sequence. It is also possible on the
- Passivation layer additionally one
- Form radiation conversion layer (not explicitly shown) or in the passivation layer
- the carrier 5 is thinned by the side facing away from the semiconductor layer sequence 2 side. As a result, the component height can be reduced. Prior to thinning, the backing may have high mechanical strength due to its greater thickness
- the semiconductor layer sequence 2 can be applied to a carrier which already has the desired final thickness in the finished semiconductor device.
- a first contact 61 is formed on the side facing away from the semiconductor layer sequence 2 of the carrier 5.
- the first contact 61 is connected to the first semiconductor layer 21 via the carrier 5, the first connection layer 31 and the line layer 4. Laterally of the semiconductor body 20 is on the
- a second contact 62 for electrically contacting the second semiconductor layer 22 via the second connection layer 32 is formed.
- Charge carriers are injected from opposite sides into the active region 25 and there with emission of
- the composite produced in this way is singulated along singulation lines 9, so that the semiconductor components produced each have a part of the carrier 5 and a semiconductor body 20 with at least one cutout 29.
- semiconductor components can be produced in a simple and reliable manner, wherein the semiconductor body 2, in particular the
- the recesses 29 in a sej ustierenden process can be easily and reliably prepared so that the conductor layer 4 in the recesses of the second semiconductor layer 22 and the active region 25 is electrically isolated.
- FIG. 1 shows an exemplary embodiment of a semiconductor component 1 produced in this way.
- the semiconductor component 1 has, by way of example only, a rear-side first contact 61 and a front side, in particular laterally, of the
- Semiconductor body 2 arranged contact 62 on.
- Passivation layer 75 preferably each contains an electrically insulating material, for example an oxide, such as silicon oxide, or a nitride, for example
- the first connection layer 31, the second connection layer 32, the first contact 61 and the second contact 62 preferably each contain a metal or consist of one
- the layers can each be single-layered or multi-layered.
- a further exemplary embodiment of a method is shown with reference to the intermediate step illustrated in FIG. 2A. This embodiment essentially corresponds to that described in connection with FIGS. 1A to 1C
- FIG. 2A essentially corresponds to FIG. 1B.
- the recess 325 of the second connection layer 32 is located in one of the recesses 260a of the structuring 26.
- Recess 325 of the second connection layer 32 is completely within the recess.
- the remaining recesses 260 may have a smaller lateral extent.
- FIG. 2B A further exemplary embodiment of a method is shown with reference to the intermediate step illustrated in FIG. 2B.
- This exemplary embodiment essentially corresponds to the exemplary embodiment illustrated in FIG. 2A.
- the first insulating layer 71 is formed so as to be in the
- Semiconductor layer sequence has openings 712. Through these openings, the electrical contacting of the first
- Recesses 29 are removed in areas. The exposure of the first terminal layer 31 is thus facilitated.
- Semiconductor layer 22 provided first sub-layer 321 of the second connection layer can be applied. Subsequently, this layer can be removed in the openings, in particular in the step in which the second connection layer 32
- Lithography mask is required.
- the openings 712 for electrical contacting of the first semiconductor layer 21 and the recesses 711 for electrical contacting of the second semiconductor layer 22 can thus be formed in a common method.
- Embodiment has the illustrated in Figure 3
- Embodiment of a semiconductor device 1 on two front-side contacts is thus not arranged on the rear side of the carrier 5, but also on the side of the semiconductor body 20.
- the carrier 5 may also be designed to be electrically insulating.
- the first contact 61 which is electrically conductively connected to the first semiconductor layer 21, is the front-side contact.
- Semiconductor layer 22 connected second contact 62 forms a back-side contact.
- the semiconductor layer arranged on the side of the active region 25 facing the carrier is the second
- a semiconductor component 1 is shown in which the first contact 61 and the second contact 62 are formed on the rear side of the carrier 5.
- the carrier has 5 plated-through holes 51.
- the carrier 5 comprises a carrier body 50 with recesses through which the plated-through holes extend in the vertical direction.
- the carrier body is partially, in particular in the field of
- Terminal layer 32 are over a gap 56th
- the gap can for example, with a gas, such as air or an inert gas, filled or evacuated. Alternatively, the gap may be filled with electrically insulating solid matter.
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Abstract
Description
Claims
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DE112015000850.0T DE112015000850B4 (de) | 2014-02-18 | 2015-02-17 | Verfahren zur Herstellung einer Mehrzahl von Halbleiterbauelementen und Halbleiterbauelement |
US15/119,376 US10074766B2 (en) | 2014-02-18 | 2015-02-17 | Method for producing semiconductor components and semiconductor component |
JP2016553005A JP2017512380A (ja) | 2014-02-18 | 2015-02-17 | 半導体構成素子を製造する方法、及び、半導体構成素子 |
CN201580009283.9A CN106062976B (zh) | 2014-02-18 | 2015-02-17 | 用于制造半导体器件的方法和半导体器件 |
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DE102014102029.4A DE102014102029A1 (de) | 2014-02-18 | 2014-02-18 | Verfahren zur Herstellung von Halbleiterbauelementen und Halbleiterbauelement |
DE102014102029.4 | 2014-02-18 |
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JP (1) | JP2017512380A (de) |
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DE112015000850A5 (de) | 2016-11-10 |
DE102014102029A1 (de) | 2015-08-20 |
JP2017512380A (ja) | 2017-05-18 |
US10074766B2 (en) | 2018-09-11 |
CN106062976A (zh) | 2016-10-26 |
CN106062976B (zh) | 2018-10-19 |
US20170062351A1 (en) | 2017-03-02 |
DE112015000850B4 (de) | 2022-03-24 |
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