WO2015096372A1 - 移位寄存器单元及其驱动方法、移位寄存器、显示装置 - Google Patents
移位寄存器单元及其驱动方法、移位寄存器、显示装置 Download PDFInfo
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- WO2015096372A1 WO2015096372A1 PCT/CN2014/078274 CN2014078274W WO2015096372A1 WO 2015096372 A1 WO2015096372 A1 WO 2015096372A1 CN 2014078274 W CN2014078274 W CN 2014078274W WO 2015096372 A1 WO2015096372 A1 WO 2015096372A1
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- 238000000034 method Methods 0.000 title claims abstract description 14
- 239000003990 capacitor Substances 0.000 claims abstract description 39
- 238000007599 discharging Methods 0.000 claims abstract description 8
- 230000003321 amplification Effects 0.000 claims abstract 5
- 238000003199 nucleic acid amplification method Methods 0.000 claims abstract 5
- 230000003139 buffering effect Effects 0.000 claims description 3
- 230000007423 decrease Effects 0.000 claims description 3
- 238000005728 strengthening Methods 0.000 abstract 2
- 102100040862 Dual specificity protein kinase CLK1 Human genes 0.000 description 18
- 101000749294 Homo sapiens Dual specificity protein kinase CLK1 Proteins 0.000 description 16
- 239000004973 liquid crystal related substance Substances 0.000 description 9
- 102100040844 Dual specificity protein kinase CLK2 Human genes 0.000 description 8
- 101000749291 Homo sapiens Dual specificity protein kinase CLK2 Proteins 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
- 230000008878 coupling Effects 0.000 description 6
- 238000010168 coupling process Methods 0.000 description 6
- 238000005859 coupling reaction Methods 0.000 description 6
- 239000011521 glass Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0404—Matrix technologies
- G09G2300/0408—Integration of the drivers onto the display substrate
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
- G09G2300/0809—Several active elements per pixel in active matrix panels
- G09G2300/0871—Several active elements per pixel in active matrix panels with level shifting
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/08—Details of timing specific for flat panels, other than clock recovery
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0219—Reducing feedthrough effects in active matrix panels, i.e. voltage changes on the scan electrode influencing the pixel voltage due to capacitive coupling
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/04—Maintaining the quality of display appearance
- G09G2320/043—Preventing or counteracting the effects of ageing
Definitions
- Shift register unit and driving method thereof shift register, display device
- the present disclosure relates to a shift register unit and a driving method thereof, a shift register, and a display device.
- a TFT-LCD (Thin Film Transistor-Liquid Crystal Display) driver mainly includes a gate driver and a data driver, wherein the gate driver converts the input clock signal into a liquid crystal display panel through a shift register Grid line.
- the shift register is commonly used in the gate driver of the liquid crystal display panel, and each gate line is connected to one stage circuit unit of the shift register.
- the gate input signal is output through the gate drive circuit, and each pixel is scanned one by one.
- the gate driving circuit can be disposed in the display panel by a chip on Array (COF) on a flexible substrate or a chip on glass (COG) on a glass substrate, or an integrated circuit unit can be formed by using a TFT. Formed in the display panel.
- COF chip on Array
- COG chip on glass
- the gate driver integrated on the glass substrate (Gate on Array, GO A) design can reduce the cost of the product, and can also reduce the cost of a process.
- FIG. 2 is a timing chart of the operation of the shift register unit shown in FIG. 1, and its working principle is as follows:
- the signal input terminal is a high level signal
- the signal received at the signal input terminal is the output signal of the shift register of the previous stage, so that the M1' tube is turned on; when the first clock signal input terminal CLK1 is low.
- the high-potential signal at the input charges the C1' capacitor, so that the potential of the PU node of the first node is pulled high, and the M5', M6' tube is opened.
- the ratio of M5' to M6' the potential of the PD at this time is made. For low potential, ⁇ 8', M9' are turned off, thus ensuring the stability of the signal output.
- the first node PU In the second phase, when the signal input is low, the ⁇ tube is turned off, the first node PU continues to maintain a high potential, and the M3' tube remains open. At this time, the first clock signal input terminal CLK1 is at a high potential. At this time, the first node amplifies the voltage of the first node due to the bootstrapping effect, and finally transmits the driving signal to the output terminal; at this time, the first node PU point is high. The potential, M6' is still on, so M8' and M9' continue to turn off, ensuring the stability of the signal output.
- the reset signal input terminal is connected to the output terminal of the next-stage shift register, and the next-stage output G ( n+1 ), that is, the reset terminal signal Reset is at a high level.
- High level signal guide at the input of the reset signal The transistors M2', M4' are made to transmit a turn-off signal to the first node PU node and the output terminal, turn off the transistor M3', and pull the output signal to the VGL potential.
- the second clock signal input terminal CLK2 is at a low potential, wherein the second clock signal has the same period as the first clock signal, and the phase is opposite.
- the first clock signal input terminal CLK1 is at a high potential, and M5' is turned off.
- the two-node PD point potential is at a low potential, and the transistors M8' and M9' are turned off.
- M6' since the previous stage has discharged the first node PU point and the output terminal through M2' and M4', M6' is in the off state. , so the second node PD point will not be discharged.
- the second clock signal input terminal CLK2 is at a high potential. Since the second clock signal input terminal CLK2 is at a high potential, M5' is turned on, and the second node PD point potential is pulled high, thereby turning on the transistors M8' and M9'.
- the first node PU point and the output terminal Output are noise-cancelled, so that the coupling (Coupling) noise voltage generated by the first clock signal input terminal CLK1 is eliminated, thereby ensuring low-voltage output and ensuring signal output stability.
- the above shift register can only cancel the output end during the working part, while the output end is in the floating state at other times, resulting in a large noise in the signal outputted from the output end of the shift register. This results in an erroneous output and poses a significant risk to the panel.
- a shift register unit and a driving method thereof, a shift register, and a display device are provided, which are capable of reducing noise in an output signal of an existing shift register.
- a shift register unit including a first capacitor, an input buffer module, a pull-up module, a reset control module, a pull-down module, and a pull-down enhancement module; the input buffer module, respectively a start signal input end, a pull-down module, a first capacitor first end and a pull-up module connection, configured to pre-charge the first capacitor in a signal input buffer phase;
- the pull-up module is respectively connected to the first clock signal input end, the first capacitor, the input buffer module, the pull-down module and the signal output end, and is configured to output a driving signal at the signal output end of the signal output stage;
- the reset control module is respectively connected to the reset signal input end, the low level signal input end and the pull-down module, and is configured to control the pull-down module to be in an off state during the reset phase;
- the pull-down module is respectively connected to the second clock signal input end, the low level signal input end, the signal output end, the input buffer module, the first capacitor, the pull-up module and the reset control module, and is used for the first noise-cancellation
- the potential of the phase control signal output is lowered and discharged for the first capacitor
- the pull-down enhancement module is respectively connected to the first clock signal input end and the pull-down module, and is configured to continuously reduce the potential of the output of the control block signal and continuously discharge the first capacitor in the second noise canceling phase.
- the input buffer module includes:
- a first transistor a gate of the first transistor and a first pole connected to the signal input, and a second pole of the first transistor is coupled to the first node.
- the pull-up module includes a third transistor
- the gate of the third transistor is connected to the first node, the first pole of the third transistor is connected to the first clock signal input end, and the second pole of the third transistor is connected to the signal output end.
- the reset control module includes a second transistor and a fourth transistor
- a gate of the second transistor is connected to the reset signal input end, a first pole of the second transistor is connected to the first node, and a second pole of the second transistor is connected to the low voltage signal input end;
- the gate of the transistor is connected to the reset signal input end, the first pole of the fourth transistor is connected to the signal output end, and the second pole of the fourth transistor is connected to the low voltage signal input end.
- the pull-down module includes a fifth transistor, a sixth transistor, an eighth transistor, and a ninth transistor;
- a first pole and a gate of the fifth transistor are connected to the second clock signal input end, and a second pole of the fifth transistor is connected to the second node;
- the first pole of the sixth transistor is connected to the second node, the gate is connected to the first node, and the second pole of the sixth transistor is connected to the low voltage signal input end;
- the first pole of the eighth transistor is connected to the first node, the gate of the eighth transistor is connected to the second node, and the second pole of the eighth transistor is connected to the input terminal of the low voltage signal;
- the first pole of the ninth transistor is connected to the signal output end, the gate of the ninth transistor is connected to the second node, and the second pole of the ninth transistor is connected to the low voltage signal input end.
- the pulldown enhancement module includes:
- At least one seventh transistor, a first pole and a gate of the seventh transistor are connected to the first clock signal input terminal, and a second pole of the seventh transistor is connected to the second node.
- the first extreme source the second extreme drain.
- a shift register comprising a plurality of shift register units of any of the above; except for the first stage shift register unit and the last stage shift register Outside the element, the start signal input end of each stage of the shift register unit is connected to the signal output end of its own upper shift register unit, and the reset signal input end of each stage shift register unit is connected to its own next The signal output of the stage shift register unit.
- a display device comprising the above-described shift register, the signal output of each of the shift registers being connected to a corresponding gate line.
- a driving method of a shift register unit comprising:
- the input buffer module is in an on state, the pull-up module, the reset control module, the pull-down module, and the pull-down enhancement module are in an off state, and the input buffer module precharges the first capacitor;
- the pull-up module is in an on state
- the input buffer module, the reset control module, the pull-down module, and the pull-down enhancement module are in an off state, and the pull-up module control signal output end outputs a driving signal
- the reset control module is in the on state, the input buffer module and the pull-up module are in the off state, the reset control module controls the pull-down module and the pull-down enhancement module is in the off state;
- the first noise canceling phase the reset control module, the pull-down module, and The pull-down enhancement module is in an on state, the input buffer module and the pull-up module are in an off state, and the potential of the pull-down module control signal output terminal is lowered and discharged for the first capacitor;
- the second noise canceling phase the reset control module, the pull-down module, and the pull-down enhancement module are in an on state, the input buffer module and the pull-up module are in an off state, and the potential of the pull-down enhancement module cooperates with the pull-down module control signal output terminal continuously decreases and is a capacitor continues to discharge;
- the shift register unit Prior to the start of the next frame, the shift register unit repeatedly alternates between a first noise canceling phase and a second noise canceling phase, continuously controlling the potential drop at the signal output and discharging the first capacitor.
- the first clock signal has the same period as the second clock signal, and the phases are opposite.
- Embodiments of the present disclosure provide a shift register unit and a driving method thereof, a shift register, and a display device, which can not only function as a gate driving of a liquid crystal display, but also when an output state thereof is in an inactive state, It is continuously noise-cancelled, which reduces the noise in its output signal, thereby reducing the possibility of its erroneous output and improving the reliability of the shift register.
- 1 is a schematic structural diagram of a shift register unit provided by the prior art
- 2 is a timing chart of operation of a shift register unit provided by the prior art
- FIG. 3 is a schematic structural diagram of a shift register unit according to an embodiment of the present disclosure
- FIG. 4 is a structural diagram of a shift register according to an embodiment of the present disclosure
- FIG. 5 is an operational timing diagram of a shift register unit provided by an embodiment of the present disclosure.
- Embodiments of the present disclosure provide a shift register unit including a first capacitor, an input buffer module 31, a pull-up module 32, a reset control module 33, a pull-down module 34, and a pull-down enhancement module 35;
- the input buffer module 31 is respectively connected to the start signal input terminal INPUT, the pull-down module 34, the first capacitor C1 first end and the pull-up module 32, and is used for pre-setting the first capacitor C1 in the signal input buffering stage. Charging
- the pull-up module 32 is respectively connected to the first clock signal input terminal CLK1, the first capacitor C1, the input buffer module 31, the pull-down module 34, and the signal output terminal OUTPUT for controlling the signal output terminal OUTPUT output during the signal output phase.
- Drive signal
- the reset control module 33 is respectively connected to the reset signal input terminal RESET, the low level signal input terminal VGL and the pull-down module 34 for controlling the pull-down module 34 to be in an off state during the reset phase; the pull-down module 34, respectively The second clock signal input terminal CLK2, the low level signal input terminal VGL, the signal output terminal OUTPUT, the input buffer module 31, the first capacitor C1, the pull-up module 32 and the reset control module 33 are connected for use in the first noise canceling stage. Decreasing a potential of the control signal output terminal OUTPUT and discharging the first capacitor C1;
- the pull-down enhancement module 35 is respectively connected to the first clock signal input terminal CLK1 and the pull-down module 34, and is configured to cooperate with the pull-down module 34 to control the potential of the signal output terminal OUTPUT to continue to be low in the second noise-cancellation phase, and to A capacitor C1 continues to discharge.
- the input buffer module 31 includes:
- the first transistor M1 has a gate and a first pole connected to the start signal input terminal INPUT, and a second pole of the first transistor M1 is connected to the first node PU.
- the pull-up module 32 includes a third transistor M3;
- the gate of the third transistor M3 is connected to the first node PU, and the third transistor M3
- the first pole is connected to the first clock signal input terminal CLK1
- the second pole of the third transistor M3 is connected to the signal output terminal OUTPUT.
- the reset control module 33 includes a second transistor M2 and a fourth transistor M4; a gate of the second transistor M2 is connected to the reset signal input terminal RESET, and a first pole of the second transistor M2 is connected to the first Node PU, the second pole of the second transistor M2 is connected to the low voltage signal input terminal VGL;
- the gate of the fourth transistor M4 is connected to the reset signal input terminal RESET, the first electrode of the fourth transistor M4 is connected to the signal output terminal OUTPUT, and the second electrode of the fourth transistor M4 is connected to the low electrode. Voltage signal input terminal VGL.
- the pull-down module 34 includes a fifth transistor M5, a sixth transistor M6, an eighth transistor M8, and a ninth transistor M9;
- the first transistor and the gate of the fifth transistor M5 are connected to the second clock signal input terminal CLK2, and the second electrode of the fifth transistor M5 is connected to the second node PD;
- the first pole of the sixth transistor M6 is connected to the second node PD, the gate is connected to the first node PU, and the second pole of the sixth transistor M6 is connected to the low voltage signal input end;
- a first pole of the eighth transistor M8 is connected to the first node PU, a gate of the eighth transistor M8 is connected to the second node PD, and a second pole of the eighth transistor M8 is connected to the low voltage signal input terminal VGL ;
- a first pole of the ninth transistor M9 is connected to the signal output terminal OUTPUT, a gate of the ninth transistor M9 is connected to the second node PD, and a second pole of the ninth transistor M9 is connected to the low voltage Signal input VGL.
- the pulldown enhancement module 35 includes:
- At least one seventh transistor M7, the first electrode and the gate of the seventh transistor M7 are connected to the first clock signal input terminal CLK1, and the second electrode of the seventh transistor M7 is connected to the second node PD.
- first extreme source and the second extreme drain Since the source and drain of the transistor used here are symmetrical, the source and drain are interchangeable. In an embodiment of the present disclosure, in order to distinguish the two poles of the transistor except the gate, one of the poles is referred to as a source and the other pole is referred to as a drain. If the source is selected as the signal input, the drain acts as the signal output and vice versa.
- the second pole of the transistor can also be the first pole of the transistor.
- the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the first Nine transistors M9 can be N-type transistors.
- FIG. 4 is a structural diagram of a shift register provided by an embodiment of the present disclosure, including The first stage shift register unit SR1, the second stage shift register unit SR2, the third stage shift register unit SR3, the fourth stage shift register unit SR4, ..., wherein, in addition to the first stage shift register unit And the last stage shift register unit, the start signal input end of each stage shift register unit is connected to the signal output end of its own upper shift register unit, and the reset signal input of each stage shift register unit The terminals are connected to the signal output of their own next stage shift register unit.
- the input signal of the first stage shift register unit is a field sync signal
- the reset signal input end of the last stage shift register unit can be connected to the reset unit
- the reset unit can be an additional redundant shift register, It can be an additional inverter.
- an embodiment of the present disclosure further provides a driving method of a shift register unit, which is based on the shift register unit described above, and includes:
- the input buffer module is in an on state, the pull-up module, the reset control module, the pull-down module, and the pull-down enhancement module are in an off state, and the input buffer module precharges the first capacitor;
- the pull-up module is in an on state
- the input buffer module, the reset control module, the pull-down module, and the pull-down enhancement module are in an off state, and the pull-up module control signal output end outputs a driving signal
- the reset control module is in the on state, the input buffer module and the pull-up module are in the off state, the reset control module controls the pull-down module and the pull-down enhancement module is in the off state;
- the first noise canceling phase the reset control module, the pull-down module, and The pull-down enhancement module is in an on state, the input buffer module and the pull-up module are in an off state, and the potential of the pull-down module control signal output terminal is lowered and discharged for the first capacitor;
- the second noise canceling phase the reset control module, the pull-down module, and the pull-down enhancement module are in an on state, the input buffer module and the pull-up module are in an off state, and the potential of the pull-down enhancement module cooperates with the pull-down module control signal output terminal continuously decreases and is The first capacitor continues to discharge;
- the shift register unit repeatedly alternates to experience the first noise canceling phase and before the start of the next frame In the second noise canceling phase, the potential of the signal output terminal is continuously controlled to be lowered and discharged for the first capacitor.
- the first clock signal and the second clock signal have the same period and opposite phases. For example, if the first clock signal is CLK, the second clock signal is CLKB, and if the first clock signal is CLKB, the second clock signal is Is CLK.
- the input signal input terminal is a high level signal
- the signal received by the start signal input terminal is an output signal of the shift register of the previous stage, so that the first transistor M1 is turned on; the first clock signal input terminal CLK1
- the high potential signal at the signal input charges the C1 capacitor, so that the potential of the PU node of the first node is pulled high, and the sixth transistor M6 is turned on, so that the potential of the PD node of the second node is low at this moment.
- the eighth transistor M8 and the ninth transistor M9 are turned off, thereby ensuring the stable output of the signal.
- the first transistor M1 is turned off, the first node PU continues to maintain a high potential, and the third transistor M3 remains turned on.
- the first clock signal input terminal CLK1 is at a high potential.
- the first node PU amplifies the voltage of the first node due to the bootstrapping effect, and finally transmits a driving signal to the output terminal; at this time, the first clock signal input end CLK1 is high, and the seventh transistor M7 is turned on. Since the PU point of the first node is high at this time, the sixth transistor M6 is still turned on, and the second node is designed by designing the ratio of the seventh transistor M7 to the sixth transistor M6.
- the PD is at a low potential, so that the eighth transistor M8 and the ninth transistor M9 continue to be turned off, ensuring the stable output of the signal.
- the next-stage output G ( n+1 ), that is, the reset terminal signal Reset is at a high level.
- the high level signal of the reset signal input terminal turns on the second transistor M2 of the transistor, and the fourth transistor M4 transmits a turn-off signal to the first node PU and the output terminal, turns off the third transistor M3, and pulls the output signal to VGL potential, at this time, the first clock signal input terminal CLK1 is low, the seventh transistor M7 is turned off, the second clock signal input terminal CLK2 is high, the fifth transistor M5 is turned on, and the sixth transistor M6 is low due to the first node PU.
- the second node PD is turned on, and the eighth transistor M8 and the ninth transistor M9 are turned on, and the first node PU and the signal output terminal are noise-canned, so that the coupling generated by the first clock signal input terminal CLK1 is generated.
- the noise voltage is eliminated to ensure low-voltage output and ensure signal output stability.
- the second clock signal input terminal CLK2 is at a low potential.
- the first node PU and the output terminal Output have been discharged through the second transistor M2 and the fourth transistor M4, at which time the sixth transistor M6 is in the off state, the first clock signal input terminal CLK1 is at a high potential, and the fifth transistor M5 is turned off.
- the seventh transistor M7 is turned on, the second node PD is still at a high potential, and the eighth transistor M8 and the ninth transistor M9 can continue to operate to perform noise cancellation on the first node PU and the output terminal Output.
- the second clock signal input terminal CLK2 is at a high potential
- the first clock signal input terminal CLK1 is at a low potential
- the fifth transistor M5 is turned on
- the sixth transistor M6 is in a closed state
- the second node PD potential is maintained.
- the eighth transistor M8 and the ninth transistor M9 are turned on to perform noise cancellation on the first node PU and the output terminal, so that the coupling (Coupling) noise voltage generated by the first clock signal input terminal CLK1 is eliminated, thereby ensuring low-voltage output and ensuring The stability of the signal output.
- the shift register unit repeats the fourth phase and the fifth phase, and continuously performs noise cancellation on the gate circuit.
- the shift register unit provided by the embodiment of the present disclosure can not only realize the function of the gate driving of the liquid crystal display, but also continuously suppresses noise when the output end thereof is in an inactive state, thereby reducing noise in the output signal thereof, thereby reducing the noise thereof.
- the possibility of erroneous output is basically off when some key thin film transistors (TFTs) are in an inactive state, avoiding shortening or error of the life of the shift register due to the drift of the threshold voltage of the thin film transistor (TFT) itself. Output.
- an embodiment of the present disclosure further provides a display device including the above-described shift register, and a signal output end of each of the shift registers is connected to a gate line.
- the display device may be: a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigation device, and the like, or any display product or component.
Abstract
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US14/424,247 US9613583B2 (en) | 2013-12-27 | 2014-05-23 | Shift register unit and driving method therefor, shift register, display device |
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CN201310738632.3A CN103700356A (zh) | 2013-12-27 | 2013-12-27 | 移位寄存器单元及其驱动方法、移位寄存器、显示装置 |
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Cited By (2)
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TWI556222B (zh) * | 2015-10-29 | 2016-11-01 | 友達光電股份有限公司 | 移位暫存器 |
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US20160049128A1 (en) | 2016-02-18 |
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