WO2014146344A1 - 阵列基板及其制作方法、显示面板 - Google Patents

阵列基板及其制作方法、显示面板 Download PDF

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Publication number
WO2014146344A1
WO2014146344A1 PCT/CN2013/075930 CN2013075930W WO2014146344A1 WO 2014146344 A1 WO2014146344 A1 WO 2014146344A1 CN 2013075930 W CN2013075930 W CN 2013075930W WO 2014146344 A1 WO2014146344 A1 WO 2014146344A1
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Prior art keywords
pixel
electrode
pixel electrode
gate
drain
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PCT/CN2013/075930
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English (en)
French (fr)
Inventor
石领
史世明
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京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US14/355,445 priority Critical patent/US9425219B2/en
Publication of WO2014146344A1 publication Critical patent/WO2014146344A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display

Definitions

  • Embodiments of the present invention relate to an array substrate, a method of fabricating the same, and a display panel. Background technique
  • the liquid crystal display device is a flat panel display device which displays an image by controlling an arrangement of liquid crystal molecules by an electric field formed between a pixel electrode and a common electrode in the panel, and controlling the refractive index of the liquid crystal molecules to light.
  • the liquid crystal display device is composed of an array substrate and a color filter substrate, wherein the array substrate is composed of laterally arranged gate lines and longitudinally arranged data lines.
  • both the pixel electrode and the common electrode are provided on the array substrate.
  • the number of gate lines and data lines are usually equal, and each pixel is connected to the gate line and the data line, respectively, but DLS (Data line sharing) technology can reduce the number of data lines by half.
  • the array substrate is provided with a first gate line 10, a second gate line 11, a third gate line 12, and a fourth gate line 13 arranged laterally, wherein the first gate line 10 is respectively Connected to the first pixel 1 and the third pixel 3; the second gate line 11 is connected to the second pixel 2 and the fourth pixel 4, respectively; the third gate line 12 is connected to the fifth pixel 5 and the seventh pixel 7, respectively; The gate lines 13 are connected to the sixth pixel 6 and the eighth pixel 8, respectively.
  • the first data line 14 and the second data line 15 are vertically arranged on the array substrate, wherein the left side of the first data line 14 is respectively connected to the first pixel 1 and the fifth pixel 5, and the right side and the second pixel respectively 2 is connected to the sixth pixel 6; the left side of the second data line 15 is connected to the third pixel 3 and the seventh pixel 7, respectively, and the right side is connected to the fourth pixel 4 and the eighth pixel 8, respectively.
  • the liquid crystal display device adopts the dot flip driving method to avoid the polarization phenomenon of the liquid crystal has become the mainstream.
  • any data line input point inverts the signal, that is, in the process of forming the electric field.
  • a forward electric field is formed once (i.e., when scanning a certain row of gate lines), and a reverse electric field is formed a second time (i.e., when scanning the next row of gate lines).
  • the polarity of the pixel actually generated when the array substrate adopts the dot inversion driving mode is as shown in FIG. 2.
  • the first gate line provides a driving signal
  • the first data line provides a positive signal
  • the second data line provides a negative signal.
  • the pixel forms a forward electric field, and the third pixel forms a reverse electric field; when the second gate line provides a driving signal, the first number The second data line provides a positive signal, and the second pixel forms a reverse electric field, and the fourth pixel forms a forward electric field; when the third gate line provides a driving signal, the first data line provides a positive signal, The second data line provides a negative signal, wherein the fifth pixel forms a forward electric field, and the seventh pixel forms a reverse electric field; when the fourth gate line provides a driving signal, the first data line provides a negative signal, and the second data line provides a positive signal, At this time, the sixth pixel forms a reverse electric field, and the eighth pixel forms a forward electric field.
  • the same polarity of adjacent pixels may cause coupling or crosstalk between pixels, which is inconsistent with the polarity of adjacent pixels to be achieved by the dot flip driving method.
  • This causes a phenomenon in which the polarity is asymmetrical in a part of the liquid crystal panel, thereby causing a phenomenon of coupling, crosstalk, and the like between the pixels, and the picture quality of the liquid crystal display device is lowered.
  • an array substrate including:
  • first pixel groups and second pixel groups disposed on the substrate, the first pixel group and the second pixel group being spaced apart from each other and constituting a pixel array;
  • Each of the first pixel groups includes two first pixel units, each of the first pixel units including a first pixel electrode connected to a common electrode and a drain of a driving thin film transistor of the first pixel unit a second pixel electrode connected to the poles, each of the second pixel groups includes two second pixel units, each of the second pixel units including a first connection to a drain of a driving thin film transistor of the second pixel unit a three-pixel electrode and a fourth pixel electrode connected to the common electrode.
  • the second pixel electrode is formed above the first pixel electrode; and in the second pixel unit, the fourth pixel electrode is formed in the third pixel unit Above the pixel electrode.
  • the first pixel electrode and the third pixel electrode are plate electrodes or slit electrodes; and the second pixel electrode and the fourth pixel electrode are slit electrodes.
  • the third pixel electrode is connected to a drain of a driving thin film transistor of the second pixel unit through a fifth pixel electrode, and the fifth pixel electrode and the first pixel electrode The four pixel electrodes are arranged in the same layer.
  • the array substrate further includes: 2n gate lines and n data lines are disposed on the substrate, wherein n is a positive integer.
  • each of the first or second pixel groups is driven by two gate lines and one data line.
  • the data line in each of the first pixel groups, is connected to a source of a driving thin film transistor of each of the first pixel units; in each of the second pixel groups, the The data line is connected to a source of the driving thin film transistor of each of the second pixel units.
  • the two gate lines are respectively connected to gates of driving thin film transistors of each of the first pixel units; in each of the second pixel groups The two gate lines are respectively connected to the gates of the driving thin film transistors of the second pixel units.
  • two first pixel units in each of the first pixel groups are arranged in a direction perpendicular to the data lines, and data lines for controlling the first pixel group are located in the two first pixel units. Between; and
  • Two second pixel units in each of the second pixel groups are arranged in a direction perpendicular to the data lines, and a data line for controlling the second pixel group is located between the two second pixel units.
  • the gate lines extend in a direction perpendicular to the data lines, and two gate lines for controlling each of the first or second pixel groups are respectively located in a direction of the data lines Both sides of the first or second pixel group.
  • Another embodiment of the present invention provides a display panel including an array substrate according to any of the embodiments of the present invention.
  • a further embodiment of the present invention provides a method for fabricating an array substrate, including:
  • a first gate and a second gate are disposed on the substrate, and a common electrode is disposed on the first pixel electrode and the substrate, wherein the first pixel electrode is in direct contact with the common electrode;
  • a first active layer, a first source and a first drain are disposed over the first gate via the gate insulating layer, and a gate insulating layer is disposed over the second gate
  • the fourth pixel electrode and the common electrode are in direct contact through the third via
  • the fifth pixel electrode and the second drain are in direct contact through the fourth via.
  • the first gate, the first active layer, the first source, the first drain, the first pixel electrode, and the second pixel electrode are used to form a pixel unit in the first pixel group.
  • the second gate, the second active layer, the second source, the second drain, the third pixel electrode, the fourth pixel electrode, and the fifth pixel electrode are used to form pixel units in the second pixel group, and each Each of the first or second pixel groups includes two pixel units, and the plurality of first pixel groups and the plurality of second pixel groups are spaced apart from each other and constitute a pixel array.
  • the second pixel electrode is formed over the first pixel electrode, and the fourth pixel electrode is formed above the third pixel electrode.
  • the array substrate provided by the embodiment of the invention, the manufacturing method thereof, and the display panel, the array substrate includes a substrate, and a plurality of first pixel groups and a plurality of second pixel groups disposed on the substrate, the first pixel group And the second pixel group is spaced apart from each other and constitutes a pixel array, wherein each of the first pixel groups includes two first pixel units, and each of the first pixel units includes a first pixel connected to a common electrode An electrode and a second pixel electrode connected to a drain of the driving thin film transistor of the first pixel unit, each of the second pixel groups includes two second pixel units, each of the second pixel units including a third pixel electrode connected to a drain of the driving thin film transistor of the second pixel unit and a fourth pixel electrode connected to the common electrode.
  • the first pixel group disposed on the substrate by the array interval and the second pixel group disposed between the adjacent first pixel groups can reduce the amount of the data line by using the shared data line technology.
  • Overcoming the phenomenon of asymmetric polarity under the point flip driving mode reduces the coupling and crosstalk between pixels and improves the picture quality of the liquid crystal display device.
  • FIG. 1 is a schematic structural view of an array substrate provided by the prior art
  • FIG. 2 is a schematic diagram showing the polarity of the array substrate when the dot flip driving method is provided in the prior art
  • FIG. 3 is a schematic structural view of the array substrate according to the embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of a first pixel unit according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of an electric field direction when a first pixel unit is in operation according to an embodiment of the present invention
  • FIG. 6 is a schematic structural diagram of a second pixel unit according to an embodiment of the present invention
  • FIG. 7 is a schematic diagram of an electric field direction when a second pixel unit is in operation according to an embodiment of the present invention
  • FIG. 8 is a schematic diagram showing polarity of an array substrate when a dot inversion driving method is provided according to an embodiment of the present invention.
  • An embodiment of the present invention provides an array substrate 1 , as shown in FIG. 3 , including:
  • first pixel groups 11 shown by dashed boxes in FIG. 3
  • second pixel groups 12 shown by broken lines in FIG. 3
  • Each of the first pixel groups 11 includes two first pixel units 110, and each of the first pixel units 110 includes a first pixel electrode connected to the common electrode and a driving thin film transistor (TFT) of the first pixel unit 110.
  • a drain-connected second pixel electrode each of the second pixel groups 12 includes two second pixel units 120, each of the second pixel units 120 including a drain connection of a driving thin film transistor (TFT) of the second pixel unit 120 Third pixel electrode and a portion connected to the common electrode Four pixel electrode.
  • the first pixel unit 110 includes:
  • a common electrode 20 disposed on the first pixel electrode 1101, wherein the first pixel electrode 1101 is in direct contact with the common electrode 20;
  • a gate insulating layer 1102 disposed on the first gate 1100, the first pixel electrode 1101, and the common electrode 20;
  • the gate insulating layer 1103 Provided on the first active layer 1103, the first source 1104, the first drain 1105, and the gate insulating layer
  • the second pixel electrode 1108 is disposed on the first drain electrode 1105 and the insulating layer 1106.
  • the second pixel electrode 1108 is in direct contact with the first drain electrode 1105 through the first via hole 1107.
  • first pixel electrode 1101 and the common electrode of the first pixel unit 110 are
  • the second pixel unit 120 includes, for example:
  • a second via hole 1207 is formed at the position, and a third via hole 1208 is formed at a position above the common electrode 20 of the insulating layer 1206 and the gate insulating layer 1202, and a portion of the insulating layer 1206 is formed at a position above the second drain electrode 1205.
  • a fourth via 1209 There is a fourth via 1209; a fourth pixel electrode 1210 (shown on the right side of the dashed line) and a fifth pixel electrode 1211 (shown on the left side of the dashed line) disposed on the second drain 1205, the third pixel electrode 1201, the common electrode 20, and the insulating layer 1206, wherein The fourth pixel electrode 1210 and the fifth pixel electrode 1211 are not in contact, the fifth pixel electrode 1211 and the third pixel electrode 1201 are in direct contact through the second via 1207, and the fourth pixel electrode 1210 and the common electrode 20 pass through the third via 1208. In direct contact, the fifth pixel electrode 1211 and the second drain electrode 1205 are in direct contact through the fourth via hole 1209.
  • the fourth pixel electrode 1210 and the common electrode 20 are in direct contact through the third via hole 1208.
  • the fifth pixel electrode 1211 and the second drain electrode 1205 are in direct contact with each other through the fourth via hole 1209. Therefore, as shown in FIG. 7, when the positive polarity display signal is received during the operation of the second pixel unit 120, the fourth pixel electrode An upward electric field is formed between 1210 and the third pixel electrode 1201, and between the common electrode 20 and the second drain 1205.
  • the second pixel electrode 1108 is formed above the first pixel electrode 1101; in the second pixel unit, the fourth pixel electrode 1210 is formed on the third pixel electrode 1201.
  • the pixel electrodes (the second pixel electrode 1108 and the fourth pixel electrode 1210) located above may be, for example, slit electrodes (for example, by gaps spaced apart from each other)
  • the strip electrodes are composed of, and the pixel electrodes (the first pixel electrode 1101 and the third pixel electrode 1201) located below may be, for example, plate electrodes or slit electrodes.
  • the array substrate 1 further includes:
  • the 2n gate lines 13 and the n data lines 14 are disposed on the substrate 10, wherein n is a positive integer.
  • each of the first or second pixel groups is driven by two gate lines and one data line.
  • the data line inputs a point inversion signal, that is, a forward electric field is formed for the first time (ie, when scanning a certain row of gate lines) in the process of forming an electric field.
  • the second time (that is, when scanning the next line of gate lines) forms a reverse electric field.
  • the first pixel unit 110 and the second pixel unit 120 provided by the embodiments of the present invention can change the polarity of the pixel unit in the prior art, and the polarities generated when the array substrate adopts the dot inversion driving mode are as shown in the figure. 8 shows that, while using the shared data line technology to reduce the amount of data lines, the phenomenon of polarity asymmetry in the original point flip driving mode is overcome, and the coupling between pixels is reduced. The crosstalk phenomenon improves the picture quality of the liquid crystal display device.
  • the data line 14 is connected to the source 1104 of the driving thin film transistor of each of the first pixel units or the source 1204 of the driving thin film transistor of each of the second pixel units.
  • each of the first or second pixel groups two gate lines are respectively associated with a gate of a driving thin film transistor of each of the first pixel units or a driving thin film transistor of each of the second pixel units
  • the gates are connected. That is, one of the gate lines is connected to the driving thin film transistor of one pixel unit in each pixel group, and the other one is connected to the driving thin film transistor of the other pixel unit in the pixel group.
  • first pixel units in each first pixel group are arranged in a direction perpendicular to the data line, and a data line for controlling the first pixel group is located between the two first pixel units;
  • two second pixel units in each second pixel group are arranged in a direction perpendicular to the data lines, and a data line for controlling the second pixel group is located between the two second pixel units, as shown in FIG. Shown.
  • the gate lines extend in a direction perpendicular to the data lines, and two gate lines for controlling each of the first or second pixel groups are respectively located on both sides of the first or second pixel group in the direction of the data lines, As shown in Figure 3.
  • the structure of the first pixel unit 110 and the structure of the second pixel unit 120 provided by the embodiment of the present invention are different, that is, when the first pixel unit 110 is in operation, the first pixel electrode 1101 and the common electrode 20, and A downward electric field is formed between the second pixel electrode 1108 and the first drain 1105; when the second pixel unit 120 is in operation, the fourth pixel electrode 1210 and the third pixel electrode 1201, and the common electrode 20 and the second drain 1205 An upward electric field is formed.
  • the purpose of the polarity is as shown in FIG. 8 when the array substrate adopts the dot inversion driving mode, thereby reducing the polarity of the data in the point flip driving mode while reducing the amount of data lines by using the shared data line technology. , the coupling between the pixels and the crosstalk phenomenon are reduced, and the picture quality of the liquid crystal display device is improved.
  • the first pixel unit 110 provided by the embodiment of the present invention may form an upward electric field between the first pixel electrode 1101 and the common electrode 20, and the second pixel electrode 1108 and the first drain 1105 during operation.
  • the fourth pixel electrode 1210 and the third pixel electrode 1201, and the common electric field 20 and the second drain 1205 form a downward electric field, which is not limited by the embodiment of the present invention.
  • Embodiments of the present invention provide an array substrate, including a substrate, and a plurality of substrates disposed on the substrate a first pixel group and a plurality of second pixel groups, the first pixel group and the second pixel group are spaced apart from each other and constitute a pixel array, wherein each of the first pixel groups includes two first pixel units, each of the first pixels
  • the unit includes a first pixel electrode connected to the common electrode and a second pixel electrode connected to the drain of the driving thin film transistor of the first pixel unit, each second pixel group including two second pixel units, each of the second pixels
  • the unit includes a third pixel electrode connected to a drain of the driving thin film transistor of the second pixel unit and a fourth pixel electrode connected to the common electrode.
  • the first pixel group disposed on the substrate by the array interval and the second pixel group disposed between the adjacent first pixel groups can reduce the amount of the data line by using the shared data line technology.
  • Overcoming the phenomenon of asymmetric polarity under the point flip driving mode reduces the coupling and crosstalk between pixels and improves the picture quality of the liquid crystal display device.
  • Embodiments of the present invention provide a method for fabricating an array substrate, including:
  • n is a positive integer.
  • the data line is coupled to the first source and/or the second source.
  • a plurality of first pixel groups and second pixel groups are disposed on the substrate, and the first pixel group and the second pixel group are spaced apart from each other and constitute a pixel array.
  • Each of the first pixel groups includes two first pixel units, each of the first pixel units includes a first pixel electrode connected to the common electrode and a second pixel electrode connected to the drain of the driving thin film transistor of the first pixel unit,
  • Each of the second pixel groups includes two second pixel units, each of the second pixel units including a third pixel electrode connected to a drain of the driving thin film transistor of the second pixel unit and a fourth pixel electrode connected to the common electrode.
  • a method of disposing a plurality of first pixel groups and second pixel groups on a substrate includes:
  • the first pixel electrode and the third pixel electrode are disposed on the substrate.
  • a first gate and a second gate are disposed on the substrate, and a common electrode is disposed on the first pixel electrode and the substrate, wherein the first pixel electrode is in direct contact with the common electrode.
  • the first gate is connected to the corresponding gate line, and the second gate is connected to the corresponding gate line.
  • the etching process can be simultaneously performed by using one etching mask process. Therefore, when the first pixel unit is fabricated in the embodiment of the present invention, First, a first pixel electrode is disposed on the substrate, and then an etching mask process is performed A first gate is simultaneously formed, and a common electrode is disposed on the first pixel electrode, wherein the first pixel electrode is in direct contact with the common electrode.
  • a gate insulating layer is disposed on at least the first gate, the second gate, the first pixel electrode, the third pixel electrode, and the common electrode.
  • a first active layer, a first source, and a first drain are disposed above the first gate via a gate insulating layer, and a second active layer is disposed over the second gate via a gate insulating layer. Two sources and a second drain.
  • a passivation insulating layer on the first active layer, the second active layer, the first source, the second source, the first drain, the second drain, and the gate insulating layer, wherein the first drain a first via hole extending to the first drain is formed on the upper end, a second via hole extending to the third pixel electrode is formed on the third pixel electrode, and a third via hole extending to the common electrode is formed on the common electrode, A fourth via extending to the second drain is formed over the second drain.
  • the second pixel electrode is disposed on the first drain and the passivation insulating layer, wherein the second pixel electrode is in direct contact with the first drain through the first via, and the second drain and the third pixel are A fourth pixel electrode and a fifth pixel electrode are disposed on the common electrode and the passivation insulating layer, wherein the fifth pixel electrode and the third pixel electrode are in direct contact through the second via hole, and the fourth pixel electrode and the common electrode pass through the third via hole In direct contact, the fifth pixel electrode and the second drain are in direct contact through the fourth via.
  • the first pixel electrode of the first pixel unit is in direct contact with the common electrode, and the second pixel electrode is in direct contact with the first drain through the first via hole, as shown in FIG. 5, at the first When the pixel unit is in operation, a first electric field is formed between the first pixel electrode and the common electrode, and the second pixel electrode and the first drain.
  • the fourth pixel electrode and the third pixel electrode are in direct contact with each other through the second via hole, and the fourth pixel electrode and the common electrode are in direct contact through the third via hole, and the fourth pixel electrode and the second drain electrode pass through The four vias are in direct contact. Therefore, as shown in FIG. 7, when the second pixel unit operates, an upward electric field is formed between the fourth pixel electrode and the third pixel electrode, and between the common electrode and the second drain.
  • the data line inputs a point inversion signal, that is, a forward electric field is formed for the first time in the process of forming an electric field, and a reverse electric field is formed for the second time.
  • the first pixel unit and the second pixel unit provided by the embodiments of the present invention can change the polarity of the pixel unit in the prior art, and the polarity generated when the array substrate adopts the dot inversion driving mode is as shown in FIG. 8 . Show, thereby reducing data lines by using shared data line technology At the same time, the phenomenon of polarity asymmetry in the point flip driving mode is overcome, the coupling and crosstalk between pixels are reduced, and the picture quality of the liquid crystal display device is improved.
  • the structure of the first pixel unit and the structure of the second pixel unit provided by the embodiment of the present invention are different in that, when the first pixel unit is in operation, the first pixel electrode and the common electrode, and the second pixel electrode A downward electric field is formed between the first drains; when the second pixel unit operates, an upward electric field is formed between the fourth pixel electrode and the third pixel electrode, and the common electrode and the second drain.
  • the purpose is to make the polarity of the array substrate adopt the dot inversion driving mode, as shown in FIG. 8, thereby reducing the polarity of the data in the point flip driving mode while reducing the amount of data lines by using the shared data line technology. , the coupling between the pixels and the crosstalk phenomenon are reduced, and the picture quality of the liquid crystal display device is improved.
  • the first pixel unit provided by the embodiment of the present invention may form an upward electric field between the first pixel electrode and the common electrode, and the second pixel electrode and the first drain during operation; the second pixel unit In operation, the fourth pixel electrode and the third pixel electrode, and the common electric field and the second drain form a downward electric field, which is not limited by the embodiment of the present invention.
  • Embodiments of the present invention provide a method for fabricating an array substrate, including disposing a first pixel electrode and a third pixel electrode on a substrate, and disposing a first gate electrode and a second gate electrode on the substrate and on the first pixel electrode and the substrate a common electrode is disposed, wherein the first pixel electrode is in direct contact with the common electrode, and a gate insulating layer is disposed on the first gate, the second gate, the first pixel electrode, the third pixel electrode, and the common electrode, at the first gate a first active layer, a first source and a first drain are disposed above the gate electrode via a gate insulating layer, and a second active layer, a second source and a second layer are disposed over the second gate via a gate insulating layer a drain, a passivation insulating layer is disposed on the first active layer, the second active layer, the first source, the second source, the first drain, the second drain, and the gate insulating layer, wherein a first via extending to
  • the number of the arrays can be set on the substrate a pixel group, and a second pixel group disposed between each adjacent first pixel group, while reducing the amount of data lines by using a shared data line technology, overcoming the phenomenon of polarity asymmetry in the point flip driving mode, and reducing The coupling between the pixels and the crosstalk phenomenon improve the picture quality of the liquid crystal display device. Therefore, the above description of the structure of the array substrate is also applicable to the fabrication method.
  • the first gate, the first active layer, the first source, the first drain, the first pixel electrode, and the second pixel electrode are used to form a pixel unit in the first pixel group
  • the second gate a second active layer, a second source, a second drain, a third pixel electrode, a fourth pixel electrode, and a fifth pixel electrode are used to form pixel units in the second pixel group
  • the two pixel groups respectively include two pixel units, and the plurality of first pixel groups and the plurality of second pixel groups are spaced apart from each other and constitute a pixel array.
  • the second pixel electrode is formed above the first pixel electrode
  • the fourth pixel electrode is formed above the third pixel electrode.
  • the embodiment of the invention further provides a display panel comprising the array substrate having any of the above features.
  • the display panel provided by the embodiment of the present invention may be a liquid crystal display device, and the liquid crystal display device may be a product having a display function such as a liquid crystal display, a liquid crystal television, a digital photo frame, a mobile phone, a tablet computer, or the like, or the invention is not limited.

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Abstract

阵列基板（1）及其制作方法、显示面板。阵列基板（1）包括基板（10）、多个第一像素组（11）和多个第二像素组（12）。多个第一像素组（11）和多个第二像素组（12）设置于基板（10）上。第一像素组（11）和第二像素组（12）互相间隔设置并构成像素阵列。每个第一像素组（11）均包括两个第一像素单元（110）。各第一像素单元（110）包括与公共电极（20）连接的第一像素电极（1101）以及与第一像素单元（110）的驱动薄膜晶体管的漏极（1105）连接的第二像素电极（1108）。每个第二像素组（12）均包括两个第二像素单元（120）。各第二像素单元（120）包括与第二像素单元（120）的驱动薄膜晶体管的漏极（1205）连接的第三像素电极（1201）以及与公共电极（20）连接的第四像素电极（1210）。

Description

阵列基板及其制作方法、 显示面板 技术领域
本发明的实施例涉及阵列基板及其制作方法、 显示面板。 背景技术
液晶显示装置是一种通过位于面板内的像素电极和公共电极之间形成的 电场， 控制液晶分子的排列， 并通过控制液晶分子对光的折射率， 从而显示 画面的一种平板显示装置。液晶显示装置由阵列基板和彩膜基板构成，其中， 阵列基板由横向排列的栅线和纵向排列的数据线构成。 特别地， 高级超维场 转换模式的液晶显示装置中， 像素电极和公共电极都设于阵列基板上。
在阵列基板的设计中， 栅线和数据线的数量通常相等， 每个像素分别与 栅线和数据线相连， 但是， DLS ( Data line sharing, 共享数据线）技术能够 将数据线的数量减少一半。 示例性的， 如图 1所示， 阵列基板上设有横向排 列的第一栅线 10、 第二栅线 11、 第三栅线 12和第四栅线 13 , 其中， 第一栅 线 10分别与第一像素 1和第三像素 3连接； 第二栅线 11分别与第二像素 2 和第四像素 4连接；第三栅线 12分别与第五像素 5和第七像素 7连接；第四 栅线 13分别与第六像素 6和第八像素 8连接。阵列基板上设有纵向排列的第 一数据线 14和第二数据线 15, 其中， 第一数据线 14的左侧分别与第一像素 1和第五像素 5连接， 右侧分别与第二像素 2和第六像素 6连接； 第二数据 线 15的左侧分别与第三像素 3和第七像素 7连接， 右侧分别与第四像素 4 和第八像素 8连接。
液晶显示装置采用点翻转驱动方式以避免液晶的极化现象已成为主流， 当所述液晶显示装置采用点翻转驱动方式工作时， 任一数据线输入点翻转信 号， 即在形成电场的过程中第一次（即， 在扫描某一行栅线时）形成正向电 场， 第二次（即， 在扫描下一行栅线时）形成反向电场。 阵列基板采用点翻 转驱动方式时实际产生的像素极性示意图如图 2所示，第一栅线提供驱动信 号时， 第一数据线提供正极信号， 第二数据线提供负极信号， 此时第一像素 形成正向电场， 第三像素形成反向电场； 第二栅线提供驱动信号时， 第一数 据线提供负极信号，第二数据线提供正极信号，此时第二像素形成反向电场， 第四像素形成正向电场； 第三栅线提供驱动信号时， 第一数据线提供正极信 号， 第二数据线提供负极信号， 此时第五像素形成正向电场， 第七像素形成 反向电场； 第四栅线提供驱动信号时， 第一数据线提供负极信号， 第二数据 线提供正极信号， 此时第六像素形成反向电场， 第八像素形成正向电场。 然 而， 当所述液晶显示装置采用点翻转驱动方式工作时， 相邻像素极性相同有 可能会引起像素间的耦合或串扰， 这不符合点翻转驱动方式所要达到的相邻 像素的极性相反的要求。 这样导致在液晶面板的部分区域出现了极性不对称 的现象， 从而引发了像素之间的耦合、 串扰等现象， 降低了液晶显示装置的 画面质量。 发明内容
根据本发明的一个实施例提供一种阵列基板， 包括：
基板；
设置于所述基板上的多个第一像素组和多个第二像素组， 所述第一像素 组和所述第二像素组互相间隔设置并构成像素阵列；
其中， 每个所述第一像素组均包括两个第一像素单元， 各所述第一像素 单元包括与公共电极连接的第一像素电极以及与所述第一像素单元的驱动薄 膜晶体管的漏极连接的第二像素电极， 每个所述第二像素组均包括两个第二 像素单元， 各所述第二像素单元包括与所述第二像素单元的驱动薄膜晶体管 的漏极连接的第三像素电极以及与所述公共电极连接的第四像素电极。
在一个示例中， 所述第一像素单元中， 所述第二像素电极形成于所述第 一像素电极的上方； 所述第二像素单元中， 所述第四像素电极形成于所述第 三像素电极的上方。
在一个示例中， 所述第一像素电极和所述第三像素电极为板状电极或狭 缝电极； 所述第二像素电极和所述第四像素电极为狭缝电极。
在一个示例中， 所述第二像素单元中， 所述第三像素电极通过第五像素 电极与所述第二像素单元的驱动薄膜晶体管的漏极连接， 所述第五像素电极 与所述第四像素电极同层设置。
在一个示例中， 所述阵列基板还包括： 交叉设置于所述基板上的 2n条栅线以及 n条数据线，其中， n为正整数。 在一个示例中， 每个所述第一或第二像素组由两条栅线和一条数据线驱 动。
在一个示例中， 在每个所述第一像素组中， 所述数据线与各所述第一像 素单元的驱动薄膜晶体管的源极连接； 在每个所述第二像素组中， 所述数据 线与各所述第二像素单元的驱动薄膜晶体管的源极连接。
在一个示例中， 在每个所述第一像素组中， 所述两条栅线分别与各所述 第一像素单元的驱动薄膜晶体管的栅极连接； 在每个所述第二像素组中， 所 述两条栅线分别与各所述第二像素单元的驱动薄膜晶体管的栅极连接。
在一个示例中， 每个所述第一像素组中的两个第一像素单元沿与数据线 垂直的方向排列， 用于控制该第一像素组的数据线位于所述两个第一像素单 元之间； 且
每个所述第二像素组中的两个第二像素单元沿与数据线垂直的方向排 列， 用于控制该第二像素组的数据线位于所述两个第二像素单元之间。
在一个示例中， 所述栅线沿与所述数据线垂直的方向延伸， 且用于控制 每个所述第一或第二像素组的两条栅线在所述数据线的方向上分别位于所述 第一或第二像素组的两侧。
本发明的另一个实施例提供一种显示面板， 包括根据本发明任一实施例 的阵列基板。
本发明的再一个实施例提供一种阵列基板的制作方法， 包括：
在基板上设置第一像素电极以及第三像素电极；
在基板上设置第一栅极、 第二栅极并在所述第一像素电极以及所述基板 上设置公共电极， 其中， 所述第一像素电极与所述公共电极直接接触；
至少在所述第一栅极、 第二栅极、 第一像素电极、 第三像素电极以及公 共电极上设置栅绝缘层；
在所述第一栅极上方隔着所述栅绝缘层设置第一有源层、 第一源极和第 一漏极， 以及在所述第二栅极上方隔着所述栅绝缘层设置第二有源层、 第二 源极和第二漏极；
在所述第一有源层、 第二有源层、 第一源极、 第二源极、 第一漏极、 第 二漏极以及栅绝缘层上设置钝化绝缘层， 其中， 所述第一漏极上方形成有延 伸至所述第一漏极的第一过孔， 所述第三像素电极上方形成有延伸至所述第 三过孔， 所述第二漏极上方形成有延伸至所述第二漏极的第四过孔；
在所述第一漏极以及钝化绝缘层上设置第二像素电极， 其中， 所述第二 像素电极与所述第一漏极通过所述第一过孔直接接触，以及在所述第二漏极、 第三像素电极、 公共电极以及钝化绝缘层上设置第四像素电极和第五像素电 极， 其中， 所述第五像素电极与第三像素电极通过所述第二过孔直接接触， 所述第四像素电极与公共电极通过所述第三过孔直接接触， 所述第五像素电 极与第二漏极通过所述第四过孔直接接触。
在一个示例中， 所述第一栅极、 第一有源层、 第一源极、 第一漏极、 第 一像素电极和第二像素电极用于形成第一像素组中的像素单元， 所述第二栅 极、 第二有源层、 第二源极、 第二漏极、 第三像素电极、 第四像素电极和第 五像素电极用于形成第二像素组中的像素单元， 且每个第一或第二像素组中 分别包括两个像素单元， 多个第一像素组和多个第二像素组互相间隔设置并 构成像素阵列。
在一个示例中， 所述第二像素电极形成在所述第一像素电极的上方， 所 述第四像素电极形成在所述第三像素电极的上方。
本发明实施例所提供的阵列基板及其制作方法、 显示面板， 阵列基板包 括基板， 以及设置于所述基板上的多个第一像素组和多个第二像素组， 所述 第一像素组和所述第二像素组互相间隔设置并构成像素阵列， 其中， 每个所 述第一像素组均包括两个第一像素单元， 各所述第一像素单元包括与公共电 极连接的第一像素电极以及与所述第一像素单元的驱动薄膜晶体管的漏极连 接的第二像素电极， 每个所述第二像素组均包括两个第二像素单元， 各所述 第二像素单元包括与所述第二像素单元的驱动薄膜晶体管的漏极连接的第三 像素电极以及与所述公共电极连接的第四像素电极。 通过该方案， 能够通过 阵列间隔设置于基板上的第一像素组， 以及设置于各相邻的第一像素组之间 的第二像素组， 在采用共享数据线技术减少数据线用量的同时， 克服点翻转 驱动方式下极性不对称的现象， 降低了像素之间的耦合、 串扰现象， 提高了 液晶显示装置的画面质量。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 筒单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为现有技术提供的阵列基板的结构示意图；
图 2为现有技术提供的采用点翻转驱动方式时阵列基板的极性示意图； 图 3为本发明实施例提供的阵列基板的结构示意图；
图 4为本发明实施例提供的第一像素单元的结构示意图；
图 5为本发明实施例提供的第一像素单元工作时的电场方向示意图； 图 6为本发明实施例提供的第二像素单元的结构示意图；
图 7为本发明实施例提供的第二像素单元工作时的电场方向示意图； 图 8为本发明实施例提供的采用点翻转驱动方式时阵列基板的极性示意 图。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
本发明实施例提供一种阵列基板 1 , 如图 3所示， 包括：
基板 10;
设置于基板 10上的多个第一像素组 11 (图 3中虚线框所示）和多个第 二像素组 12 (图 3中虚线框所示）， 第一像素组 11和第二像素组 12互相间 隔设置并构成像素阵列；
其中， 每个第一像素组 11均包括两个第一像素单元 110, 各第一像素单 元 110包括与公共电极连接的第一像素电极以及与第一像素单元 110的驱动 薄膜晶体管（TFT )的漏极连接的第二像素电极， 每个第二像素组 12均包括 两个第二像素单元 120, 各第二像素单元 120包括与第二像素单元 120的驱 动薄膜晶体管 （TFT ) 的漏极连接的第三像素电极以及与公共电极连接的第 四像素电极。
在一个示例中， 如图 4所示， 第一像素单元 110包括：
设置于基板 10上的第一栅极 1100和第一像素电极 1101;
设置于第一像素电极 1101上的公共电极 20, 其中， 第一像素电极 1101 与公共电极 20直接接触；
设置于第一栅极 1100、第一像素电极 1101和公共电极 20上的栅绝缘层 1102;
设置于第一栅极 1100上方的第一有源层 1103、第一源极 1104和第一漏 极 1105;
设置于第一有源层 1103、 第一源极 1104、 第一漏极 1105以及栅绝缘层
1102上的绝缘层 1106,其中，绝缘层 1106的在第一漏极 1105上方的位置处 形成有第一过孔 1107;
设置于第一漏极 1105以及绝缘层 1106上的第二像素电极 1108, 其中， 第二像素电极 1108与第一漏极 1105通过第一过孔 1107直接接触。
需要说明的是，由于第一像素单元 110的第一像素电极 1101与公共电极
20直接接触， 且第二像素电极 1108与第一漏极 1105通过第一过孔 1107直 触， 因此， 如图 5所示， 在第一像素单元 110工作中收到正极性的显示 信号时， 第一像素电极 1101与公共电极 20, 以及第二像素电极 1108与第一 漏极 1105之间形成向下的电场。
进一步地， 如图 6所示， 第二像素单元 120例如包括：
设置于基板 10上的第二栅极 1200、 第三像素电极 1201和公共电极 20; 设置于第二栅极 1200、第三像素电极 1201以及公共电极 20上的栅绝缘 层 1202;
设置于第二栅极 1200上方的第二有源层 1203、第二源极 1204和第二漏 极 1205;
设置于第二有源层 1203、 第二源极 1204、 第二漏极 1205以及栅绝缘层 1202上的绝缘层 1206,其中，绝缘层 1206和栅绝缘层 1202的在第三像素电 极 1201上方的位置处形成有第二过孔 1207, 绝缘层 1206和栅绝缘层 1202 的在公共电极 20上方的位置处形成有第三过孔 1208,绝缘层 1206的在第二 漏极 1205上方的位置处形成有第四过孔 1209; 设置于第二漏极 1205、第三像素电极 1201、公共电极 20以及绝缘层 1206 上的第四像素电极 1210 (虚线右侧所示）和第五像素电极 1211 (虚线左侧所 示） ， 其中， 第四像素电极 1210与第五像素电极 1211不接触， 第五像素电 极 1211与第三像素电极 1201通过第二过孔 1207直接接触， 第四像素电极 1210与公共电极 20通过第三过孔 1208直接接触， 第五像素电极 1211与第 二漏极 1205通过第四过孔 1209直接接触。
需要说明的是，由于第二像素单元 120的第五像素电极 1211与第三像素 电极 1201通过第二过孔 1207直接接触， 且第四像素电极 1210与公共电极 20通过第三过孔 1208直接接触， 第五像素电极 1211与第二漏极 1205通过 第四过孔 1209直接接触， 因此， 如图 7所示， 在第二像素单元 120工作中收 到正极性的显示信号时， 第四像素电极 1210与第三像素电极 1201 , 以及公 共电极 20与第二漏极 1205之间形成向上的电场。
从图 4-7可以看出， 在第一像素单元中， 第二像素电极 1108形成于第一 像素电极 1101的上方； 在第二像素单元中， 第四像素电极 1210形成于第三 像素电极 1201的上方。另外，为了使在上下像素电极之间形成的电场施加到 液晶层， 位于上方的像素电极（第二像素电极 1108和第四像素电极 1210 ) 例如可以为狭缝电极（例如由相互间隔的缝隙和条状电极组成） ， 而位于下 方的像素电极（第一像素电极 1101和第三像素电极 1201 )例如可以为板状 电极或狭缝电极。
进一步地， 阵列基板 1还包括：
交叉设置于基板 10上的 2n条栅线 13以及 n条数据线 14,其中， n为正 整数。
进一步地， 每个第一或第二像素组由两条栅线和一条数据线驱动。
需要说明的是，具有上述结构的阵列基板在采用点翻转驱动方式工作时， 数据线输入点翻转信号， 即在形成电场的过程中第一次（即扫描某一行栅线 时）形成正向电场， 第二次（即扫描下一行栅线时）形成反向电场。 采用本 发明实施例所提供的第一像素单元 110和第二像素单元 120, 能够改变原本 现有技术中像素单元的极性， 使阵列基板采用点翻转驱动方式时的产生的极 性示意图如图 8 所示， 从而在采用共享数据线技术减少数据线用量的同时， 克服原有的点翻转驱动方式下极性不对称的现象， 降低了像素之间的耦合、 串扰现象， 提高了液晶显示装置的画面质量。
进一步地，在第一像素组或第二像素组中，数据线 14与各第一像素单元 的驱动薄膜晶体管的源极 1104或各第二像素单元的驱动薄膜晶体管的源极 1204连接。
进一步地， 在每个所述第一或第二像素组中， 两条栅线分别与各所述第 一像素单元的驱动薄膜晶体管的栅极或各所述第二像素单元的驱动薄膜晶体 管的栅极相连。 也就是说， 其中一条栅线与每个像素组中的一个像素单元的 驱动薄膜晶体管连接， 另外一条栅线与该像素组中的另一个像素单元的驱动 薄膜晶体管连接。
例如， 每个第一像素组中的两个第一像素单元沿与数据线垂直的方向排 歹 ij , 用于控制该第一像素组的数据线位于所述两个第一像素单元之间； 且每 个第二像素组中的两个第二像素单元沿与数据线垂直的方向排列， 用于控制 该第二像素组的数据线位于所述两个第二像素单元之间， 如图 3所示。
例如， 栅线沿与数据线垂直的方向延伸， 且用于控制每个第一或第二像 素组的两条栅线在数据线的方向上分别位于第一或第二像素组的两侧， 如图 3所示。
需要补充的是， 本发明实施例所提供的第一像素单元 110的结构和第二 像素单元 120的结构的区别在于， 第一像素单元 110工作时， 第一像素电极 1101与公共电极 20,以及第二像素电极 1108与第一漏极 1105之间形成向下 的电场；第二像素单元 120工作时，第四像素电极 1210与第三像素电极 1201 , 以及公共电极 20与第二漏极 1205之间形成向上的电场。 其目的在于使阵列 基板采用点翻转驱动方式时的产生的极性示意图如图 8 所示，从而在采用共 享数据线技术减少数据线用量的同时， 克服点翻转驱动方式下极性不对称的 现象， 降低了像素之间的耦合、 串扰现象，提高了液晶显示装置的画面质量。
同理的， 本发明的实施例所提供的第一像素单元 110可以在工作时， 第 一像素电极 1101与公共电极 20, 以及第二像素电极 1108与第一漏极 1105 之间形成向上的电场；第二像素单元 120工作时，第四像素电极 1210与第三 像素电极 1201 , 以及公共电极 20与第二漏极 1205之间形成向下的电场， 本 发明的实施例不做限制。
本发明实施例提供一种阵列基板， 包括基板， 以及设置于基板上的多个 第一像素组和多个第二像素组， 第一像素组和第二像素组互相间隔设置并构 成像素阵列， 其中， 每个第一像素组均包括两个第一像素单元， 各第一像素 单元包括与公共电极连接的第一像素电极以及与第一像素单元的驱动薄膜晶 体管的漏极连接的第二像素电极,每个第二像素组均包括两个第二像素单元， 各第二像素单元包括与第二像素单元的驱动薄膜晶体管的漏极连接的第三像 素电极以及与公共电极连接的第四像素电极。 通过该方案， 能够通过阵列间 隔设置于基板上的第一像素组， 以及设置于各相邻的第一像素组之间的第二 像素组， 在采用共享数据线技术减少数据线用量的同时， 克服点翻转驱动方 式下极性不对称的现象， 降低了像素之间的耦合、 串扰现象， 提高了液晶显 示装置的画面质量。
本发明实施例提供一种阵列基板的制作方法， 包括：
S101、 在基板上交叉设置 2n条栅线以及 n条数据线。
其中， n为正整数。
数据线与第一源极和 /或第二源极连接。
采用共享数据线技术， 在基板上交叉设置 2n条栅线以及 n条数据线。
S102、 在基板上设置多个第一像素组和第二像素组， 第一像素组和第二 像素组互相间隔设置并构成像素阵列。
每个第一像素组均包括两个第一像素单元， 各第一像素单元包括与公共 电极连接的第一像素电极以及与第一像素单元的驱动薄膜晶体管的漏极连接 的第二像素电极， 每个第二像素组均包括两个第二像素单元， 各第二像素单 元包括与第二像素单元的驱动薄膜晶体管的漏极连接的第三像素电极以及与 公共电极连接的第四像素电极。
例如， 在基板上设置多个第一像素组和第二像素组的方法包括：
S201、 在基板上设置第一像素电极以及第三像素电极。
S202、 在基板上设置第一栅极、 第二栅极并在第一像素电极以及基板上 设置公共电极， 其中， 第一像素电极与公共电极直接接触。
其中， 第一栅极与对应的栅线相连， 第二栅极与对应的栅线相连。
需要说明的是， 在制作第一像素单元时， 由于栅极和公共电极的材料相 同， 通常通过一次刻蚀掩膜工艺就可同时制作获得， 因此， 本发明实施例在 制作第一像素单元时， 先在基板上设置第一像素电极， 再通过刻蚀掩膜工艺 同时形成第一栅极， 以及位于第一像素电极上的公共电极， 其中， 第一像素 电极与公共电极直接接触。
S203、 至少在第一栅极、 第二栅极、 第一像素电极、 第三像素电极以及 公共电极上设置栅绝缘层。
S204、 在第一栅极上方隔着栅绝缘层设置第一有源层、 第一源极和第一 漏极， 以及在第二栅极上方隔着栅绝缘层设置第二有源层、 第二源极和第二 漏极。
5205、 在第一有源层、 第二有源层、 第一源极、 第二源极、 第一漏极、 第二漏极以及栅绝缘层上设置钝化绝缘层， 其中， 第一漏极上方形成有延伸 至第一漏极的第一过孔， 第三像素电极上方形成有延伸至第三像素电极的第 二过孔， 公共电极上方形成有延伸至公共电极的第三过孔， 第二漏极上方形 成有延伸至第二漏极的第四过孔。
5206、 在第一漏极以及钝化绝缘层上设置第二像素电极， 其中， 第二像 素电极与第一漏极通过第一过孔直接接触， 以及在第二漏极、第三像素电极、 公共电极以及钝化绝缘层上设置第四像素电极和第五像素电极， 其中， 第五 像素电极与第三像素电极通过第二过孔直接接触， 第四像素电极与公共电极 通过第三过孔直接接触， 第五像素电极与第二漏极通过第四过孔直接接触。
需要说明的是，由于第一像素单元的第一像素电极与公共电极直接接触， 且第二像素电极与第一漏极通过第一过孔直接接触， 因此， 如图 5所示， 在 第一像素单元工作时， 第一像素电极与公共电极， 以及第二像素电极与第一 漏极之间形成向下的电场。 由于第二像素单元的第四像素电极与第三像素电 极通过第二过孔直接接触， 且第四像素电极与公共电极通过第三过孔直接接 触， 第四像素电极与第二漏极通过第四过孔直接接触， 因此， 如图 7所示， 在第二像素单元工作时， 第四像素电极与第三像素电极， 以及公共电极与第 二漏极之间形成向上的电场。
需要说明的是，具有上述结构的阵列基板在采用点翻转驱动方式工作时， 数据线输入点翻转信号， 即在形成电场的过程中第一次形成正向电场， 第二 形成反向电场。 采用本发明实施例所提供的第一像素单元和第二像素单元， 能够改变原本现有技术中像素单元的极性， 使阵列基板采用点翻转驱动方式 时的产生的极性示意图如图 8 所示，从而在采用共享数据线技术减少数据线 用量的同时， 克服点翻转驱动方式下极性不对称的现象， 降低了像素之间的 耦合、 串扰现象， 提高了液晶显示装置的画面质量。
需要补充的是， 本发明实施例所提供的第一像素单元的结构和第二像素 单元的结构的区别在于， 第一像素单元工作时， 第一像素电极与公共电极， 以及第二像素电极与第一漏极之间形成向下的电场； 第二像素单元工作时， 第四像素电极与第三像素电极， 以及公共电极与第二漏极之间形成向上的电 场。 其目的在于使阵列基板采用点翻转驱动方式时的产生的极性， 如图 8 所 示， 从而在采用共享数据线技术减少数据线用量的同时， 克服点翻转驱动方 式下极性不对称的现象， 降低了像素之间的耦合、 串扰现象， 提高了液晶显 示装置的画面质量。
同理的， 本发明的实施例所提供的第一像素单元可以在工作时， 第一像 素电极与公共电极， 以及第二像素电极与第一漏极之间形成向上的电场； 第 二像素单元工作时， 第四像素电极与第三像素电极， 以及公共电极与第二漏 极之间形成向下的电场， 本发明的实施例不做限制。
本发明实施例提供一种阵列基板的制作方法， 包括在基板上设置第一像 素电极以及第三像素电极， 在基板上设置第一栅极、 第二栅极并在第一像素 电极以及基板上设置公共电极， 其中， 第一像素电极与公共电极直接接触， 至少在第一栅极、 第二栅极、 第一像素电极、 第三像素电极以及公共电极上 设置栅绝缘层， 在第一栅极上方隔着栅绝缘层设置第一有源层、 第一源极和 第一漏极， 以及在第二栅极上方隔着栅绝缘层设置第二有源层、 第二源极和 第二漏极， 在第一有源层、 第二有源层、 第一源极、 第二源极、 第一漏极、 第二漏极以及栅绝缘层上设置钝化绝缘层， 其中， 第一漏极上方形成有延伸 至第一漏极的第一过孔， 第三像素电极上方形成有延伸至第三像素电极的第 二过孔， 公共电极上方形成有延伸至公共电极的第三过孔， 第二漏极上方形 成有延伸至第二漏极的第四过孔， 在第一漏极以及钝化绝缘层上设置第二像 素电极， 其中， 第二像素电极与第一漏极通过第一过孔直接接触， 以及在第 二漏极、 第三像素电极、 公共电极以及钝化绝缘层上设置第四像素电极和第 五像素电极， 其中， 第五像素电极与第三像素电极通过第二过孔直接接触， 第四像素电极与公共电极通过第三过孔直接接触， 第五像素电极与第二漏极 通过第四过孔直接接触。 通过该方案， 能够通过阵列间隔设置于基板上的第 一像素组， 以及设置于各相邻的第一像素组之间的第二像素组， 在采用共享 数据线技术减少数据线用量的同时， 克服点翻转驱动方式下极性不对称的现 象， 降低了像素之间的耦合、 串扰现象， 提高了液晶显示装置的画面质量。 因此， 以上关于阵列基板的结构描述也适用于该制作方法。 例如， 上述第一 栅极、 第一有源层、 第一源极、 第一漏极、 第一像素电极和第二像素电极用 于形成第一像素组中的像素单元， 上述第二栅极、 第二有源层、 第二源极、 第二漏极、 第三像素电极、 第四像素电极和第五像素电极用于形成第二像素 组中的像素单元， 且每个第一或第二像素组中分别包括两个像素单元， 多个 第一像素组和多个第二像素组互相间隔设置并构成像素阵列。 例如， 在制作 像素电极的过程中， 第二像素电极形成在第一像素电极的上方， 第四像素电 极形成在第三像素电极的上方。
本发明实施例还提供一种显示面板，包括具有上述任意特征的阵列基板。 本发明实施例所提供的显示面板可以为液晶显示装置， 液晶显示装置可 以为液晶显示器、 液晶电视、 数码相框、 手机、 平板电脑等具有显示功能的 产品或者部本发明不做限制。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1、 一种阵列基板， 包括：
基板；
设置于所述基板上的多个第一像素组和多个第二像素组， 所述第一像素 组和所述第二像素组互相间隔设置并构成像素阵列；
其中， 每个所述第一像素组均包括两个第一像素单元， 各所述第一像素 单元包括与公共电极连接的第一像素电极以及与所述第一像素单元的驱动薄 膜晶体管的漏极连接的第二像素电极， 每个所述第二像素组均包括两个第二 像素单元， 各所述第二像素单元包括与所述第二像素单元的驱动薄膜晶体管 的漏极连接的第三像素电极以及与所述公共电极连接的第四像素电极。
2、 根据权利要求 1所述的阵列基板， 其中， 所述第一像素单元中， 所述 第二像素电极形成于所述第一像素电极的上方； 所述第二像素单元中， 所述 第四像素电极形成于所述第三像素电极的上方。
3、根据权利要求 1或 2所述的阵列基板， 其中， 所述第一像素电极和所 述第三像素电极为板状电极或狭缝电极； 所述第二像素电极和所述第四像素 电极为狭缝电极。
4、 根据权利要求 1-3中任意一项所述的阵列基板， 其中， 所述第二像素 单元中， 所述第三像素电极通过第五像素电极与所述第二像素单元的驱动薄 膜晶体管的漏极连接， 所述第五像素电极与所述第四像素电极同层设置。
5、 根据权利要求 1-4中任意一项所述的阵列基板， 其中， 所述阵列基板 还包括：
交叉设置于所述基板上的 2n条栅线以及 n条数据线，其中， n为正整数。
6、根据权利要求 5所述的阵列基板， 其中，每个所述第一或第二像素组 由两条栅线和一条数据线驱动。
7、 根据权利要求 6所述的阵列基板， 其中， 在每个所述第一像素组中， 所述数据线与各所述第一像素单元的驱动薄膜晶体管的源极连接； 在每个所 述第二像素组中， 所述数据线与各所述第二像素单元的驱动薄膜晶体管的源 极连接。
8、 根据权利要求 7所述的阵列基板， 其中， 在每个所述第一像素组中， 所述两条栅线分别与各所述第一像素单元的驱动薄膜晶体管的栅极连接； 在 每个所述第二像素组中， 所述两条栅线分别与各所述第二像素单元的驱动薄 膜晶体管的栅极连接。
9、根据权利要求 6所述的阵列基板， 其中，每个所述第一像素组中的两 个第一像素单元沿与数据线垂直的方向排列， 用于控制该第一像素组的数据 线位于所述两个第一像素单元之间； 且
每个所述第二像素组中的两个第二像素单元沿与数据线垂直的方向排 列， 用于控制该第二像素组的数据线位于所述两个第二像素单元之间。
10、 根据权利要求 9所述的阵列基板， 其中， 所述栅线沿与所述数据线 垂直的方向延伸， 且用于控制每个所述第一或第二像素组的两条栅线在所述 数据线的方向上分别位于所述第一或第二像素组的两侧。
11、 一种显示面板， 包括如权利要求 1-10中任意一项所述的阵列基板。
12、 一种阵列基板的制作方法， 包括：
在基板上设置第一像素电极以及第三像素电极；
在基板上设置第一栅极、 第二栅极并在所述第一像素电极以及所述基板 上设置公共电极， 其中， 所述第一像素电极与所述公共电极直接接触；
至少在所述第一栅极、 第二栅极、 第一像素电极、 第三像素电极以及公 共电极上设置栅绝缘层；
在所述第一栅极上方隔着所述栅绝缘层设置第一有源层、 第一源极和第 一漏极， 以及在所述第二栅极上方隔着所述栅绝缘层设置第二有源层、 第二 源极和第二漏极；
在所述第一有源层、 第二有源层、 第一源极、 第二源极、 第一漏极、 第 二漏极以及栅绝缘层上设置钝化绝缘层， 其中， 所述第一漏极上方形成有延 伸至所述第一漏极的第一过孔， 所述第三像素电极上方形成有延伸至所述第 三过孔， 所述第二漏极上方形成有延伸至所述第二漏极的第四过孔；
在所述第一漏极以及钝化绝缘层上设置第二像素电极， 其中， 所述第二 像素电极与所述第一漏极通过所述第一过孔直接接触 ,以及在所述第二漏极、 第三像素电极、 公共电极以及钝化绝缘层上设置第四像素电极和第五像素电 极， 其中， 所述第五像素电极与第三像素电极通过所述第二过孔直接接触， 所述第四像素电极与公共电极通过所述第三过孔直接接触， 所述第五像素电 极与第二漏极通过所述第四过孔直接接触。
13、 根据权利要求 12所述的方法， 其中， 所述第一栅极、 第一有源层、 第一源极、 第一漏极、 第一像素电极和第二像素电极用于形成第一像素组中 的像素单元， 所述第二栅极、 第二有源层、 第二源极、 第二漏极、 第三像素 电极、 第四像素电极和第五像素电极用于形成第二像素组中的像素单元， 且 每个第一或第二像素组中分别包括两个像素单元， 多个第一像素组和多个第 二像素组互相间隔设置并构成像素阵列。
14、根据权利要求 12所述的方法， 其中， 所述第二像素电极形成在所述 第一像素电极的上方， 所述第四像素电极形成在所述第三像素电极的上方。
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