WO2013086919A1 - 阵列基板及其制造方法和显示装置 - Google Patents

阵列基板及其制造方法和显示装置 Download PDF

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Publication number
WO2013086919A1
WO2013086919A1 PCT/CN2012/084772 CN2012084772W WO2013086919A1 WO 2013086919 A1 WO2013086919 A1 WO 2013086919A1 CN 2012084772 W CN2012084772 W CN 2012084772W WO 2013086919 A1 WO2013086919 A1 WO 2013086919A1
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Prior art keywords
pixel
pixel electrode
data signal
gate scan
adjacent
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PCT/CN2012/084772
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English (en)
French (fr)
Inventor
李成
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北京京东方光电科技有限公司
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Priority to US13/806,172 priority Critical patent/US9116407B2/en
Publication of WO2013086919A1 publication Critical patent/WO2013086919A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134336—Matrix
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/40—Arrangements for improving the aperture ratio
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • Embodiments of the present invention relate to an array substrate, a method of fabricating the same, and a display device. Background technique
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • the TFT-LCD is mainly composed of an array substrate of a pair of boxes and a color filter substrate, wherein the array substrate is formed with a plurality of gate scan lines and a plurality of data signal lines disposed to cross each other, and a plurality of gates which are disposed to cross each other.
  • the array substrate is formed with a plurality of gate scan lines and a plurality of data signal lines disposed to cross each other, and a plurality of gates which are disposed to cross each other
  • Each of the plurality of pixel regions arranged in a matrix defined by the polar scan lines and the plurality of data signal lines is covered with the pixel electrodes. As shown in FIG.
  • the TFT-LCD array substrate includes: a plurality of gate scan lines 100 and a plurality of data signal lines 200 arranged in a crossover; and an arrangement defined by the plurality of gate scan lines 100 and the plurality of data signal lines 200 a plurality of pixel regions of the matrix; and pixel electrodes 300 overlying each of the plurality of pixel regions, wherein the adjacent two gate scan lines 100 and adjacent two data signal lines crossing the same 200 defines a pixel area.
  • a black matrix (BM) needs to be disposed at a corresponding position on the color filter substrate, thereby adversely affecting the aperture ratio of the TFT-LCD.
  • the main factors that generally affect the aperture ratio of a TFT-LCD include:
  • the electrode material is mainly the resistivity property of the gate scan line and the data signal line. If the resistivity of the electrode material is high, in order to reduce the delay of signal transmission, these lines have to be made wider. This will undoubtedly reduce the aperture ratio of the pixel;
  • the resolution and size are determined and the pixel size is fixed.
  • the electrode materials of the prior art although there is a metal material having a relatively low resistivity, the line width cannot be made very small due to the process. Therefore, reducing the redundancy of design and process is the main way to increase the aperture ratio.
  • the pixel electrode is covered above the data signal line, which can reduce the area of light leakage, and a part of the light blocking can be formed by using the data signal line, thereby reducing the width of the BM, thereby bringing Increase the aperture ratio.
  • the width of the data signal line is relatively narrow, generally about 4 microns.
  • the data signal lines may be above these TFT-LCD products, or data signals.
  • a portion of the area above the line may be covered with pixel electrodes, that is, there are still gaps between adjacent pixel electrodes.
  • many areas on the array substrate do not cover the pixel electrodes. Therefore, these areas cannot form a modulated electric field, and the liquid crystal display still has light leakage.
  • the aperture ratio of the TFT-LCD can only be increased to a limited extent and there is also a risk of short circuit. Therefore, the aperture ratio and stability of the existing TFT-LCD need to be further improved. Summary of the invention
  • Embodiments of the present invention provide an array substrate, a manufacturing method, and a display device for improving light transmission efficiency and stability of the display device.
  • An embodiment of the present invention provides an array substrate, including: a plurality of gate scan lines and a plurality of data signal lines disposed in a crossover manner;
  • the plurality of pixel regions are divided into a plurality of first pixel regions and a plurality of second pixel regions, each of the plurality of pixel regions being surrounded by adjacent two gate scan lines and a phase intersecting therewith Two adjacent data signal lines define one pixel area, wherein
  • the first pixel regions are spaced apart from each other, and each of the first pixel regions is covered with a corresponding first pixel electrode, and the first pixel electrode is in the first layer;
  • the second pixel regions are spaced apart from each other, and each of the second pixel regions is covered with a corresponding second pixel electrode, and the second pixel electrode is in the second layer;
  • An insulating layer is disposed between the first layer and the second layer; wherein the spacing is disposed between one pixel region.
  • the first pixel electrode and the second pixel electrode covered on the adjacent pixel regions in the gate scanning line direction overlap above the corresponding data signal lines.
  • the at least one first pixel electrode overlaps the corresponding gate scan line, and/or the at least one second pixel electrode overlaps the corresponding gate scan line.
  • the first layer and the layer of the data signal line further include: a resin layer.
  • the embodiment of the invention further provides a method for manufacturing an array substrate, comprising:
  • a pattern including a plurality of gate scan lines and a plurality of data signal lines disposed in a crossover, wherein the plurality of gate scan lines and the plurality of data signal lines disposed in a cross arrangement are arranged in a matrix a pixel area, each of the plurality of pixel areas is defined by two adjacent gate scan lines and two adjacent data signal lines crossing the same, the plurality of pixels being divided into a plurality of first a pixel area and a plurality of second pixel areas;
  • each first pixel electrode corresponding to a first pixel region, the first pixel Electrode spacing setting
  • each of the second pixel electrodes Corresponding to a second pixel region, the second pixel electrode is spaced apart, and is disposed in a pixel region where the first pixel electrode is not disposed;
  • interval setting refers to a pixel area setting.
  • first pixel electrode and the second pixel electrode covered on the adjacent pixel regions in the gate scan line direction overlap above the corresponding data signal lines.
  • the at least one first pixel electrode overlaps the corresponding gate scan line, and/or the at least one second pixel electrode overlaps the corresponding gate scan line.
  • the plurality of first pixel electrodes are formed on the substrate on which the plurality of gate scan lines and the plurality of data signal lines are formed, and each first pixel electrode corresponds to a first pixel region Before the first pixel electrode is spaced apart, the method further includes:
  • a resin layer is deposited on the substrate forming a pattern including the gate scan lines and the data signal lines disposed alternately.
  • Embodiments of the present invention also provide a display device including the array substrate as described above.
  • the pixel electrodes covered on the non-adjacent pixel regions in the array substrate are located in the same layer, and the pixel electrodes covered on the adjacent pixel regions are located in different layers, thus reducing design and process redundancy.
  • the aperture ratio of the array substrate is increased, the short circuit between the pixel electrodes covered on the adjacent pixel regions does not occur, and the light transmission efficiency and stability of the display device are improved.
  • FIG. 1 is a schematic plan view of a TFT-LCD array substrate in the prior art
  • FIG. 2 is a schematic plan view of a TFT-LCD array substrate in an embodiment of the present invention.
  • FIG. 3 is a cross-sectional view of the TFT-LCD array substrate of the embodiment of the present invention taken along line A-A';
  • FIG. 4 is a schematic diagram of a modulated electric field after a box in an embodiment of the present invention. detailed description
  • the array substrate of the TFT-LCD includes: a plurality of gate scan lines and a plurality of data signal lines disposed at a crossover; and the arrays defined by the plurality of gate scan lines and the plurality of data signal lines are arranged in a matrix a plurality of pixel regions; each of the plurality of pixel regions includes a thin film transistor as a switching element; and a pixel electrode overlying each of the plurality of pixel regions, wherein adjacent pixel regions
  • the covered pixel electrodes are not on the same layer, and the gate of the thin film transistor of each pixel is electrically connected or integrally formed with the corresponding gate line scan line, and the source is electrically connected or integrally formed with the corresponding data signal line, and the drain is formed.
  • the pixel electrode is formed by two patterning processes, for example, first, after forming a plurality of gate scan lines and a plurality of data signal lines disposed on the substrate, respectively, on the substrate Forming a corresponding first pixel electrode on each of the first pixel regions that are not adjacent; then, after depositing an insulating layer on the substrate on which the first pixel electrode is formed, on each of the second pixel regions not adjacent to each other Forming a corresponding second pixel electrode, wherein the second pixel region is different from the first pixel region.
  • the pixel electrodes covered on the adjacent pixel regions are not on the same layer, the pixel apertures covered by the adjacent pixel regions do not occur while reducing the redundancy of the design and process to increase the aperture ratio of the TFT-LCD.
  • the pixel electrode is indium tin oxide, for example, by (ITO), indium speech oxide (IZO), tin oxide (SnO x) transparent conductive material.
  • ITO indium tin oxide
  • IZO indium speech oxide
  • SnO x tin oxide
  • the TFT-LCD array substrate includes: a plurality of gate scan lines 100 and a plurality of data signal lines 200 disposed in a crosswise manner; and a plurality of gate scan lines 100 and a plurality of strips disposed at intersection with each other
  • the data signal line 200 defines a plurality of pixel regions arranged in a matrix, wherein the plurality of pixels are divided into a first pixel region and a second pixel region, and the first pixel region in the gate scan line direction and the data signal line direction
  • the second pixel regions are alternately arranged with each other, and each of the pixel regions is defined by two adjacent gate scan lines 100 and two adjacent data signals 200 intersecting therewith.
  • the first pixel regions are spaced apart from each other, and each of the first pixel regions is covered with a corresponding first pixel electrode 300, the first pixel electrode 300 is in the first layer; the second pixel regions are spaced apart, and each The second pixel area is covered with a corresponding second pixel electrode 400, and the second pixel electrode 400 is in the second layer; and, between the first layer and the second layer, an insulating layer is included.
  • the interval setting refers to spacing one pixel area setting. That is, the first pixel regions are not adjacent to each other, and the second pixel region The first pixel electrodes 300 are spaced apart from each other, and the second pixel electrodes 400 are also spaced apart from each other.
  • FIG. 3 A cross-sectional view along the line A-A' of the TFT-LCD array substrate is shown in FIG. 3, and a data signal line 200 is disposed on the glass substrate 1, and the first pixel electrode 300 is located above the data signal line 200, above the first pixel electrode 300. There is an insulating layer 2, and a second pixel electrode 400 is disposed above the insulating layer 2.
  • the first pixel electrodes 300 are spaced apart from each other, the second pixel electrodes 400 are also spaced apart from each other, and the first pixel electrodes 300 and the second pixel electrodes 400 are respectively located at two layers, and even if the first pixel electrodes 300 are covered
  • the gate scan lines and/or data signal lines are formed in the first pixel region where they are located, and the adjacent first pixel electrodes 300 are also far apart without being connected. Thus, no short circuit occurs between the pixel electrodes covered on the adjacent pixel regions.
  • the redundancy of the design and the process can be further reduced, and the aperture ratio can be improved.
  • the first pixel electrode 300 and the second pixel electrode 400 covered on the pixel regions adjacent in the gate scanning line direction overlap above the corresponding data signal lines.
  • the first pixel electrode 300 can cover a portion or all of the area above the corresponding data signal line defining the first pixel region in which it is located
  • the second pixel electrode 400 can also cover the corresponding data signal line defining the second pixel region in which it is located.
  • the first pixel electrode 300 covers a portion or all of the area above the corresponding data signal line defining the first pixel region
  • the second pixel electrode 400 covered on the adjacent pixel region is also covered. A portion or all of the area above the corresponding data signal line of the second pixel region.
  • first pixel electrode 300 and the second pixel electrode 400 are respectively located in two layers, a short circuit does not occur between the pixel electrodes covered on the adjacent pixel regions. Further, in the direction of the gate scanning line, there is no gap or void between the pixel electrodes covered on the adjacent pixel regions, and the area which is affected by the light leakage is reduced, thereby increasing the aperture ratio.
  • the first pixel electrode and the second pixel electrode covered on adjacent pixel regions in the direction of the data signal line may overlap above the corresponding gate scan line, and only the pixel electrode in the direction of the data signal line is reduced. The gap between them.
  • one, two, more, or all of the first pixel electrodes 300 may overlap with corresponding gate scan lines defining the first pixel region in which they are located. There may be one, two, more, or all of the first pixel electrodes 300 covering a portion or all of the area above the corresponding gate scan line. or, One, two, more, or all of the second pixel electrodes 400 overlap the corresponding gate scan lines. There may be one, two, more, or all of the second pixel electrodes 400 covering a portion or all of the area above the corresponding gate scan line. or,
  • One, two, more, or all of the first pixel electrodes 300 overlap the corresponding gate scan lines, and one, two, more, or all of the second pixel electrodes 400 and corresponding gates
  • the pole scan lines overlap. That is, one, two, more, or all of the first pixel electrodes 300 cover a portion or all of the area above the corresponding gate scan line, and one, two, more, or all of the second pixel electrodes 400 are covered. Part or all of the area above the corresponding gate scan line.
  • the gap between the pixel electrodes in the direction of the data signal line is reduced or absent, the area where the light leakage is affected is reduced, and the aperture ratio is improved.
  • the first pixel electrode and the second pixel electrode covered on adjacent pixel regions in the direction of the data signal line overlap above the corresponding gate scan line while adjacent to the pixel region in the gate scan line direction
  • the upper first pixel electrode and the second pixel electrode overlap above the corresponding data signal line, so that not only the gap between the pixel electrodes in the direction of the gate scanning line but also the pixel electrode in the direction of the data signal line can be reduced. The gap between them.
  • the gap between the pixel electrodes in the gate scanning line direction is absent, and after the TFT substrate is formed on the array substrate and the color filter substrate, the gate is scanned.
  • the first pixel electrode 300 and the second pixel electrode 400 covered on the adjacent pixel regions in the line direction overlap above the corresponding data signal lines, so that the pixel electrode and the common electrode on the color film are provided at any position in the liquid crystal cell.
  • the modulated electric field formed between them forms a completely modulated electric field in the liquid crystal cell, as shown in FIG.
  • the gate scanning line and the data signal line can be used as a light blocking layer, thereby eliminating the BM on the color filter substrate.
  • a resin material is interposed between the data signal line and the pixel electrode, that is, a layer between the first layer where the first pixel electrode 300 is located and the layer where the data signal line is located further includes: a resin layer.
  • the resin layer 3 is included.
  • the pixel electrodes on the adjacent pixel regions on the TFT-LCD array substrate are not in the same layer, that is, the pixel electrodes are formed by two patterning processes.
  • the patterning process includes: masking, exposure, development, etching, and stripping.
  • the process of manufacturing a TFT-LCD array substrate includes:
  • Step 501 forming a pattern including a gate scan line and a data signal line disposed at a crossover on the substrate, wherein the adjacent two gate scan lines and the adjacent two data signal lines crossing the same define a pixel area.
  • a plurality of gate scan lines and a plurality of data signal lines arranged in a cross are formed on the substrate by two or more patterning processes.
  • the plurality of pixel regions arranged in a matrix are defined by the gate scan lines and the data signal lines, that is, the adjacent two gate scan lines and the adjacent two data signal lines crossing the same define a pixel region, wherein
  • the plurality of pixel regions are divided into a first pixel region and a second pixel region, and the first pixel region and the second pixel region are alternately arranged with each other in the gate scanning line direction and the data signal line direction.
  • the first pixel regions are spaced apart from each other, and the second pixel regions are also spaced apart from each other.
  • the first pixel regions are not adjacent to each other, and the second pixel regions are not adjacent to each other, and the first pixels are not adjacent to each other.
  • the area is different from the second pixel area.
  • Step 502 Form a first pixel electrode corresponding to the first pixel region on a substrate on which a plurality of gate scan lines and a plurality of data signal lines are formed.
  • a first pixel electrode is correspondingly formed on each of the first pixel regions not adjacent to each other by a patterning process on a substrate on which a plurality of gate scan lines and a plurality of data signal lines are formed. That is, a plurality of first pixel electrodes are formed, each of the first pixel electrodes corresponding to one pixel region, and the first pixel electrodes are spaced apart.
  • the pixel area corresponding to the first pixel electrode is the first pixel area
  • the interval setting refers to the setting of one pixel area.
  • the first pixel electrode extends to cover the gate scan line and/or the data signal line forming the first pixel region, the interval between adjacent first pixel regions may be smaller than one pixel region.
  • the at least one first pixel electrode may cover part or all of the area above the data signal line, or at least the first pixel electrode may cover part or all of the area above the gate scan line, or at least one first pixel electrode may cover the data signal A portion or all of the area above the line, and at least one first pixel electrode may cover a portion or all of the area above the gate scan line.
  • Step 503 depositing an insulating layer on the substrate on which the first pixel electrode is formed to form an insulating layer.
  • the insulating layer is used to isolate the first pixel electrode from the second pixel electrode.
  • the insulating layer comprises silicon nitride.
  • Step 504 forming a plurality of second pixel electrodes on the substrate on which the insulating layer is formed, each second pixel electrode corresponding to one second pixel region, the second pixel electrode being spaced apart, and disposed on the pixel not provided with the first pixel electrode Area.
  • the pixel area corresponding to the second pixel electrode is the second pixel area, and the second pixel area is spaced apart.
  • the corresponding second pixel electrode may be formed on each of the second pixel regions not adjacent to each other in the matrix, wherein the second pixel region is different from the first pixel region.
  • a second pixel electrode is formed corresponding to each of the second pixel regions on the substrate on which the plurality of gate scan lines, the plurality of data signal lines, the first pixel electrode, and the insulating layer are formed by a patterning process. Since the second pixel region is different from the first pixel region, the pixel electrodes covered on the adjacent pixel regions are not on the same layer.
  • At least one second pixel electrode may cover part or all of the area above the data signal line, or at least the second pixel electrode may cover part or all of the area above the gate scan line, or at least one second pixel electrode may cover the data signal A portion or all of the area above the line, and at least two first pixel electrodes may cover a portion or all of the area above the gate scan line.
  • the first pixel electrode and the second pixel electrode covered on the adjacent pixel regions in the gate scanning line direction may overlap above the corresponding data signal lines.
  • At least one first pixel electrode overlaps with a corresponding gate scan line; or, at least one second pixel electrode overlaps with a corresponding gate scan line; or
  • At least one first pixel electrode overlaps a corresponding gate scan line, and at least one second pixel electrode overlaps a corresponding gate scan line.
  • the method further includes: depositing a resin layer on the substrate on which the pattern including the gate scan line and the data signal line is formed .
  • the array substrate of the TFT-LCD is taken as an example, but the embodiment of the present invention is not limited thereto, and the electronic paper, the OLED panel, the digital photo frame, the mobile phone, the tablet computer, and the like have products or components having any display function.
  • the above array substrate can also be used for the array substrate.
  • the embodiment of the invention further provides a display device comprising any one of the above array substrates.
  • An example of the display device is a liquid crystal display device in which a TFT array substrate and an opposite substrate are opposed to each other to form a liquid crystal cell in which a liquid crystal material is filled.
  • the opposite substrate is, for example, a color filter substrate.
  • the pixel electrode of each pixel unit of the TFT array substrate is used to apply an electric field to control the degree of rotation of the liquid crystal material to perform a display operation.
  • the liquid crystal display further includes a backlight that provides backlighting for the array substrate.
  • Another example of the display device is an organic electroluminescence display device in which a TFT array is subjected to a display operation.
  • the display device may be: a product or a component having any display function such as a liquid crystal panel, an electronic paper, an OLED panel, a liquid crystal television, a liquid crystal display, a digital photo frame, a mobile phone, a tablet computer, or the like.
  • the pixel electrodes covered on the non-adjacent pixel regions in the array substrate are located in the same layer, and the pixel electrodes covered on the adjacent pixel regions are located in different layers, thus reducing design and The redundancy of the process improves the aperture ratio of the array substrate, and the short circuit of the pixel electrode covered on the adjacent pixel region does not occur, thereby improving the light transmission efficiency and stability of the display device.
  • the pixel electrodes covered on the adjacent pixel regions in the direction of the gate scanning line overlap above the corresponding data signal lines, so that a completely modulated electric field can be formed in the liquid crystal cell, so that there is no possibility of light leakage in the liquid crystal cell.
  • the line width design of the BM on the color filter substrate can be minimized, thereby increasing the pixel aperture ratio and improving the light transmission efficiency of the display device.
  • the gap between the pixel electrodes can be reduced in the direction of the data signal line, or not, the area where the light leakage is affected is reduced, the aperture ratio is further increased, and the light transmission efficiency of the display device is improved.

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Abstract

提供了一种阵列基板及其制造方法和显示装置。该阵列基板包括：交叉设置的栅极扫描线（100）和数据信号线（200）；多个像素区，由彼此交叉设置的多条栅极扫描线（100）和多条数据信号线（200）限定；以及多个像素电极，覆盖在多个像素区的每个像素区上，且包括多个第一像素电极（300）和多个第二像素电极（400），其中多个像素区被分为多个第一像素区和多个第二像素区，多个第一像素区之间间隔设置，且每个第一像素区上覆盖有对应的第一像素电极（300），第一像素电极（300）处于第一层；第二像素区之间间隔设置，且每个第二像素区上覆盖有对应的第二像素电极（400），第二像素电极（400）处于第二层；第一层与第二层之间包括绝缘层（2）。由此，在提高阵列基板的开口率的同时，不会发生相邻像素区上覆盖的像素电极之间的电路现象，提高了显示装置的透光性以及稳定性。

Description

阵列基板及其制造方法和显示装置 技术领域
本发明的实施例涉及一种阵列基板及制造方法和显示装置。 背景技术
薄膜晶体管液晶显示器 ( Thin Firm Transistor Liquid Crystal Display, TFT-LCD )以其体积小， 功耗低， 无辐射， 分辨率高等优点成为了目前的主 导产品。
TFT-LCD主要由对盒的阵列基板和彩膜基板构成， 其中， 阵列基板上形 成有彼此交叉设置的多条栅极扫描线和多条数据信号线， 并且， 由彼此交叉 设置的多条栅极扫描线和多条数据信号线限定的排列为矩阵的多个像素区中 的每个像素区覆盖有像素电极。 如图 1所示， 该 TFT-LCD阵列基板包括： 交叉设置的多条栅极扫描线 100和多条数据信号线 200; 由多条栅极扫描线 100和多条数据信号线 200限定的排列为矩阵的多个像素区； 以及在多个像 素区中的每个像素区上覆盖的像素电极 300, 其中， 相邻的两条栅极扫描线 100和与其交叉的相邻两条数据信号线 200限定一个像素区。
由于， 每个像素区上覆盖的像素电极并不覆盖在栅极扫描线上， 也不覆 盖在数据信号线上， 因此， 在栅极扫描线和数据信号线所处的区域会存在漏 光， 这样， 需在彩膜基板上对应位置设置黑矩阵（BM ) , 从而， 会不利地 影响 TFT-LCD的开口率。
目前，液晶显示器的分辨率不断提高，每英寸像素（Pixels Per Inch, PPI ) 越来越高， 像素的尺寸也越来越小。 而对于高端的像素设计来说， 开口率的 提升显得尤为重要， 但是也是越来越困难。
一般影响 TFT-LCD开口率的主要因素包括：
1、液晶显示器的分辨率和显示尺寸。 因为分辨率和显示尺寸决定了像素 尺寸的大小， 在固有的工艺基础上， 像素的尺寸越大， 开口率相对越高；
2、 电极材料， 主要是栅极扫描线和数据信号线的电阻率属性，如果电极 材料的电阻率高的话，为了降低信号传输的延迟，不得不把这些线做宽一些， 这样无疑会降低像素的开口率；
3、设计上或者工艺上的冗余度， 为了产品量产的稳定性， 在设计时要尽 量保证稳定的可靠设计， 此外， 考虑到工艺波动， 都会留有一定的冗余度， 因此， 这也会影响到像素的开口率。
对于一个特定 TFT-LCD产品来说， 分辨率和尺寸确定后， 像素的尺寸 也就被固定了下来。 并且， 现有的业内电极材料中， 虽然有电阻率比较低的 金属材料， 但是由于工艺， 线宽方面也不能做到非常小。 因此， 减少设计和 工艺的冗余度成为提高开口率的主要途径。
例如： 目前一些 TFT-LCD产品中， 将像素电极覆盖在数据信号线的上 方， 这样可以减少漏光的面积， 另外可以利用数据信号线形成一部分挡光， 从而可以减小 BM的宽度， 进而带来提升开口率。
但是， 数据信号线的宽度比较窄， 一般为 4微米左右， 为防止相邻的像 素电极之间发生短路现象， 这些 TFT-LCD产品中， 只能有部分数据信号线 的上方， 或者， 数据信号线上方的部分区域， 可以覆盖有像素电极， 即相邻 像素电极之间仍然有空隙。这样，阵列基板上很多区域是没有覆盖像素电极， 因此， 这些区域不能形成调制电场， 液晶显示器仍存在漏光， 还需在彩膜基 板上对应位置设置黑 BM。 这样， ， 只能有限地提高 TFT-LCD的开口率而且 还存在短路的风险。 因此， ， 现有的 TFT-LCD的开口率以及稳定性还需进 一步提高。 发明内容
本发明实施例提供一种阵列基板及制造方法和显示装置， 用以提高显示 装置的透光效率以及稳定性。
本发明实施例提供一种阵列基板， 包括： 交叉设置的多条栅极扫描线和 多条数据信号线；
多个像素区， 由彼此交叉设置的所述多条栅极扫描线和所述多条数据信 号线限定且排列为矩阵；
多个薄膜晶体管， 分别包括在所述多个像素区的每个像素区中； 以及 多个像素电极， 分别覆盖在所述多个像素区的每个像素区上， 且包括多 个第一像素电极和多个第二像素电极， 其中所述多个像素区被分为多个第一像素区和多个第二像素区， 所述多个像素区的每个像素区由相邻的两条栅极扫描线和与其交叉的相 邻两条数据信号线限定一个像素区， 其中，
所述第一像素区之间间隔设置， 且每个第一像素区上覆盖有对应的第一 像素电极， 所述第一像素电极处于第一层；
所述第二像素区之间间隔设置， 且每个第二像素区上覆盖有对应的第二 像素电极， 所述第二像素电极处于第二层；
所述第一层与所述第二层之间设置有绝缘层； 其中， 所述间隔设置指间 隔一个像素区设置。
备选地， 在栅极扫描线方向的相邻的像素区上覆盖的第一像素电极与第 二像素电极在对应的数据信号线上方交叠。
备选地， 至少一个第一像素电极与对应的栅极扫描线交叠， 和 /或， 至少 一个第二像素电极与对应的栅极扫描线交叠。
备选地， 所述第一层与所述数据信号线所在层之间还包括： 树脂层。 本发明实施例还提供一种阵列基板的制造方法， 包括：
在基板上形成包括交叉设置的多条栅极扫描线和多条数据信号线的图 形， 其中， 交叉设置的所述多条栅极扫描线和所述多条数据信号线限定排列 为矩阵的多个像素区， 所述多个像素区中的每个像素区由相邻的两条栅极扫 描线和与其交叉的相邻两条数据信号线限定， 所述多个像素区分为多个第一 像素区和多个第二像素区；
在形成有所述多条栅极扫描线和所述多条数据信号线的所述基板上形成 多个第一像素电极， 每个第一像素电极对应一个第一像素区， 所述第一像素 电极间隔设置；
在形成有所述多条栅极扫描线、 所述多条数据信号线和所述多个第一像 素电极的基板上形成绝缘层；
在形成有所述多条栅极扫描线、 所述多条数据信号线、 所述多个第一像 素电极和所述绝缘层的基板上形成多个第二像素电极， 每个第二像素电极对 应一个第二像素区， 所述第二像素电极间隔设置， 且设置于未设置第一像素 电极的像素区；
其中所述间隔设置指间隔一个像素区设置。 备选地， 在栅极扫描线方向的相邻的像素区上覆盖的第一像素电极与第 二像素电极在对应的数据信号线上方交叠。
备选地， 至少一个第一像素电极与对应的栅极扫描线交叠， 和 /或， 至少 一个第二像素电极与对应的栅极扫描线交叠。
备选地， 所述在形成有所述多条栅极扫描线和所述多条数据信号线的所 述基板上形成多个第一像素电极， 每个第一像素电极对应一个第一像素区， 所述第一像素电极间隔设置之前， 还包括：
在形成包括交叉设置的栅极扫描线和数据信号线的图形的基板上沉积树 脂层。
本发明实施例还提供一种显示装置， 包括如上所述的阵列基板。
本发明实施例中， 阵列基板中不相邻的像素区上覆盖的像素电极位于同 一层中， 而相邻的像素区上覆盖的像素电极位于不同层中， 这样， 在减少设 计和工艺的冗余度来提高阵列基板的开口率的同时， 不会发生相邻像素区上 覆盖的像素电极之间短路现象， 提高了显示装置的透光效率以及稳定性。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为现有技术中 TFT-LCD阵列基板的平面示意图；
图 2本发明实施例中 TFT-LCD阵列基板的平面示意图；
图 3为图 2中本发明实施例的 TFT-LCD阵列基板沿线 A-A'的截面示意 图；
图 4为本发明实施例中对盒后调制电场的示意图。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
本发明实施例中， TFT-LCD的阵列基板上包括： 交叉设置的多条栅极扫 描线和多条数据信号线； 由多条栅极扫描线和多条数据信号线限定的排列为 矩阵的多个像素区； 多个像素区中的每个像素区中包括作为开关元件的薄膜 晶体管； 以及在多个像素区中的每个像素区上覆盖的像素电极， 其中， 相邻 的像素区上覆盖的像素电极不在同一层上， 而且， 其中每个像素的薄膜晶体 管的栅极与相应的栅线扫描线电连接或一体形成， 源极与相应的数据信号线 电连接或一体形成， 漏极与相应的像素电极电连接或一体形成。 而且， 在本 发明实施例中， 像素电极是通过两次构图工艺形成的， 例如， 首先， 在基板 上形成交叉设置的多条栅极扫描线和多条数据信号线后， 在该基板上互不相 邻的每个第一像素区上形成对应的第一像素电极； 然后， 在形成了第一像素 电极的基板上沉积了绝缘层后， 在互不相邻的每个第二像素区上形成对应的 第二像素电极， 其中， 第二像素区与第一像素区不同。 这样， 由于相邻的像 素区上覆盖的像素电极不在同一层上， 从而在减少设计和工艺的冗余度来提 高 TFT-LCD开口率的同时， 不会发生相邻像素区上覆盖的像素电极之间短 路的现象。
该像素电极例如通过铟锡氧化物（ITO )、 铟辞氧化物（IZO )、 氧化锡 ( SnOx )等透明导电材料形成。
下面结合图 2和 3对本发明实施例的阵列基板的结构进行详细说明。 参见图 2, 本发明实施例中， TFT-LCD阵列基板包括： 交叉设置的多条 栅极扫描线 100和多条数据信号线 200; 由彼此交叉设置的多条栅极扫描线 100和多条数据信号线 200限定的排列为矩阵的多个像素区， 其中， 该多个 像素区分成第一像素区和第二像素区， 且在栅极扫描线方向和数据信号线方 向第一像素区和第二像素区彼此交替设置， 每个像素区由相邻的两条栅极扫 描线 100和与其交叉的相邻两条数据信号 200线限定。
这里， 第一像素区之间间隔设置， 且每个第一像素区上覆盖有对应的第 一像素电极 300, 第一像素电极 300处于第一层； 第二像素区之间间隔设置， 且每个第二像素区上覆盖有对应的第二像素电极 400, 第二像素电极 400处 于第二层； 并且， 第一层与第二层之间包括： 绝缘层。 本发明实施例中， 间 隔设置指间隔一个像素区设置。 即第一像素区之间互不相邻， 第二像素区之 间也互不相邻， 从而， 第一像素电极 300之间间隔设置， 第二像素电极 400 之间也间隔设置。
该 TFT-LCD阵列基板的沿线 A-A'的剖面图如图 3所示， 在玻璃基板 1 上有数据信号线 200, 第一像素电极 300位于数据信号线 200上方， 第一像 素电极 300上方有绝缘层 2, 绝缘层 2上方有第二像素电极 400。
由于第一像素电极 300之间间隔设置， 第二像素电极 400之间也间隔设 置， 并且， 第一像素电极 300与第二像素电极 400分别位于两个层， 而且， 即使第一像素电极 300覆盖形成在其所在的第一像素区的栅极扫描线和 /或 数据信号线， 相邻第一像素电极 300也相距很远而不会相连接。 这样， 相邻 像素区上覆盖的像素电极之间不会发生短路。 本发明实施例中， 还可以进一 步减少设计和工艺的冗余度， 提高开口率。
备选地， 在栅极扫描线方向相邻的像素区上覆盖的第一像素电极 300与 第二像素电极 400在对应的数据信号线上方交叠。 这样， 第一像素电极 300 可以覆盖限定其所在第一像素区的对应的数据信号线上方部分或全部区域， 而第二像素电极 400也可覆盖限定其所在第二像素区的对应的数据信号线上 方部分或全部区域。 这里， 如图 3所示， 第一像素电极 300覆盖了限定所在 第一像素区的对应的数据信号线上方部分或全部区域， 相邻的像素区上覆盖 的第二像素电极 400也覆盖了限定其所在第二像素区的对应的数据信号线上 方部分或全部区域。
由于第一像素电极 300与第二像素电极 400分别位于两个层， 这样， 相 邻像素区上覆盖的像素电极之间不会发生短路。 并且， 在栅极扫描线方向， 相邻的像素区上覆盖的像素电极之间没有空隙或者空隙被减少， 减少了带来 漏光影响的区域， 从而提高了开口率。
备选地， 也可以在数据信号线方向的相邻的像素区上覆盖的第一像素电 极与第二像素电极在对应的栅极扫描线上方交叠， 而只减少数据信号线方向 上像素电极之间的空隙。
作为示例， 该 TFT-LCD阵列基板上， 可以有一个、 两个、 多个， 或全 部的第一像素电极 300与限定其所在第一像素区的对应的栅极扫描线交叠。 即可有一个， 两个， 多个， 或全部的第一像素电极 300覆盖在对应栅极扫描 线上方部分或全部区域。 或者， 有一个， 两个， 多个， 或全部的第二像素电极 400与对应的栅极扫描线 交叠。 即可有一个， 两个， 多个， 或全部的第二像素电极 400覆盖在对应栅 极扫描线上方部分或全部区域。 或者，
有一个， 两个， 多个， 或全部的第一像素电极 300与对应的栅极扫描线 交叠， 以及， 有一个， 两个， 多个， 或全部的第二像素电极 400与对应的栅 极扫描线交叠。 即有一个， 两个， 多个， 或全部的第一像素电极 300覆盖在 对应栅极扫描线上方部分或全部区域， 以及有一个， 两个， 多个， 或全部的 第二像素电极 400覆盖在对应栅极扫描线上方部分或全部区域。
这样， 由于数据信号线方向上像素电极之间的空隙减少了， 或没有了， 从而， 减少了带来漏光影响的区域， 提高了开口率。
备选地， 在数据信号线方向的相邻的像素区上覆盖的第一像素电极与第 二像素电极在对应的栅极扫描线上方交叠， 同时在栅极扫描线方向相邻的像 素区上覆盖的第一像素电极与第二像素电极在对应的数据信号线上方交叠， 这样不仅可以减少栅极扫描线方向上像素电极之间的空隙， 而且还可以减少 数据信号线方向上像素电极之间的空隙。 这样， 在栅极扫描线方向， 相邻的 像素区上覆盖的像素电极之间没有空隙或者空隙被减少， 同时， 数据信号线 方向上相邻像素电极之间的空隙减少了， 或没有了， 从而， 减少了带来漏光 影响的区域， 提高了开口率。
在如图 2所示的 TFT-LCD阵列基板中， 栅极扫描线方向上像素电极之 间的空隙没有了， 该阵列基板与彩膜基板对盒后形成 TFT-LCD后， 由于在 栅极扫描线方向的相邻的像素区上覆盖的第一像素电极 300与第二像素电极 400在对应的数据信号线上方交叠， 这样使得液晶盒内任意位置都有像素电 极和彩膜上公共电极之间形成的调制电场， 即在液晶盒内形成完全的调制电 场， 如图 4所示。 从而， 使得液晶盒内无漏光的可能性， 这样就可以避免考 虑对盒对位冗余度， 把彩膜基板上的 BM的线宽设计最小化， 以此来提高像 素开口率， 提高 TFT-LCD的性能。
进一步， 在如图 4所示的实施例中， 如果对盒工艺的精度足够高的话， 可以将栅极扫描线和数据信号线来作挡光层， 进而省去彩膜基板上的 BM。
备选地， 由于像素电极和数据信号线之间存在寄生电容， 当该寄生电容 过大时， 会导致液晶显示器的串扰非常严重， 因此， 在本发明实施例中， 在 数据信号线和像素电极之间插入一层树脂材料， 即第一像素电极 300所处的 第一层与数据信号线所在层之间还包括： 树脂层。 这样， 由于树脂材料本身 的介电常数较低， 厚度也会大一些， 从而， 可以有效降低像素电极和数据线 之间的寄存电容， 进而改善画面特性， 提高 TFT-LCD的性能。
这里，如图 4所示，在第一像素电极 300所处的第一层与数据信号线 200 所在层之间包括： 树脂层 3。
本发明实施例中， TFT-LCD阵列基板上相邻的像素区上的像素电极不在 同一层， 即通过两次构图工艺形成像素电极。 而构图工艺中有分别包括： 掩 模、 曝光、 显影、 刻蚀和剥离等工艺。
以下， 将对本发明实施例的阵列基板的制造方形进行详细说明。
作为示例， 制造 TFT-LCD阵列基板的过程包括：
步骤 501 : 在基板上形成包括交叉设置的栅极扫描线和数据信号线的图 形， 其中， 相邻的两条栅极扫描线和与其交叉的相邻两条数据信号线限定一 个像素区。
通过两次或多次构图工艺在基板上形成交叉设置的多条栅极扫描线和多 条数据信号线。 这样， 由这些栅极扫描线和数据信号线限定排列为矩阵的多 个像素区， 即相邻的两条栅极扫描线和与其交叉的相邻两条数据信号线限定 一个像素区， 其中， 多个像素区被分为第一像素区和第二像素区， 在栅极扫 描线方向和数据信号线方向第一像素区和第二像素区彼此交替设置。 其中， 第一像素区之间间隔设置， 第二像素区之间也间隔设置， 这样， 第一像素区 之间互不相邻， 第二像素区之间也互不相邻， 而第一像素区与第二像素区不 同。
步骤 502: 在形成有多条栅极扫描线和多条数据信号线的基板上对应于 所述第一像素区形成第一像素电极。
在形成有多条栅极扫描线和多条数据信号线的基板上通过一次构图工艺 在互不相邻的每个第一像素区上对应形成第一像素电极。 即形成多个第一像 素电极，每个第一像素电极对应一个像素区， 第一像素电极间隔设置。这里， 第一像素电极对应的像素区为第一像素区，间隔设置指间隔一个像素区设置。 但是， 如果第一像素电极延伸为覆盖形成所在第一像素区的栅极扫描线和 / 或数据信号线， 相邻第一像素区之间的间隔可能会小于一个像素区。 其中，至少一个第一像素电极可以覆盖数据信号线上方部分或全部区域， 或， 至少第一像素电极可以覆盖栅极扫描线上方部分或全部区域， 或者， 至 少一个第一像素电极可以覆盖数据信号线上方部分或全部区域， 和， 至少一 个第一像素电极可以覆盖栅极扫描线上方部分或全部区域。
步骤 503: 在形成了第一像素电极的基板上沉积绝缘层， 形成绝缘层。 绝缘层用来隔离第一像素电极与第二像素电极， 一般， 绝缘层包括氮化 硅。
步骤 504: 在形成了绝缘层的基板上形成多个第二像素电极， 每个第二 像素电极对应一个第二像素区， 第二像素电极间隔设置， 且设置于未设置第 一像素电极的像素区。 这里， 第二像素电极对应的像素区为第二像素区， 第 二像素区间隔设置。 即可在矩阵中互不相邻的每个第二像素区上形成对应第 二像素电极， 其中， 第二像素区与第一像素区不同。
通过构图工艺在形成有多条栅极扫描线、 多条数据信号线、 第一像素电 极及绝缘层的基板上对应于每个第二像素区形成第二像素电极。 由于第二像 素区与第一像素区不同， 这样， 相邻的像素区上覆盖的像素电极不在同一层 上。
这里，至少一个第二像素电极可以覆盖数据信号线上方部分或全部区域， 或， 至少第二像素电极可以覆盖栅极扫描线上方部分或全部区域， 或者， 至 少一个第二像素电极可以覆盖数据信号线上方部分或全部区域， 和， 至少二 个第一像素电极可以覆盖栅极扫描线上方部分或全部区域。
因此， 本发明实施例中， 在栅极扫描线方向的相邻的像素区上覆盖的第 一像素电极与第二像素电极可在对应的数据信号线上方交叠。
备选地， 至少一个第一像素电极与对应的栅极扫描线交叠； 或， 至少一个第二像素电极与对应的栅极扫描线交叠； 或，
至少一个第一像素电极与对应的栅极扫描线交叠， 和至少一个第二像素 电极与对应的栅极扫描线交叠。
通过上述工艺即可制造出相邻的像素区上覆盖的像素电极不在同一层的 TFT-LCD阵列基板。 当然， 为有效降低像素电极和数据线之间的寄存电容， 本发明实施例中， 在步骤 502之前， 还包括： 在形成了包括栅极扫描线和数 据信号线的图形的基板上沉积树脂层。 上述所有实施例中以 TFT-LCD的阵列基板为例进行描述， 但是本发明 实施例不限于此， 电子纸、 OLED面板、 数码相框、 手机、 平板电脑等具有 任何显示功能的产品或部件中的阵列基板也可釆用上述阵列基板。
本发明实施例还提供了一种显示装置， 其包括上述任意一种阵列基板。 该显示装置的一个示例为液晶显示装置， 其中， TFT阵列基板与对置基 板彼此对置以形成液晶盒， 在液晶盒中填充有液晶材料。 该对置基板例如为 彩膜基板。 TFT阵列基板的每个像素单元的像素电极用于施加电场对液晶材 料的旋转的程度进行控制从而进行显示操作。 在一些示例中， 该液晶显示器 还包括为阵列基板提供背光的背光源。
该显示装置的另一个示例为有机电致发光显示装置， 其中， TFT阵列基 进行显示操作。
所述显示装置可以为： 液晶面板、 电子纸、 OLED面板、 液晶电视、 液 晶显示器、 数码相框、 手机、 平板电脑等具有任何显示功能的产品或部件。
本发明实施例的显示装置中， 阵列基板中不相邻的像素区上覆盖的像素 电极位于同一层中，而相邻的像素区上覆盖的像素电极位于不同层中，这样， 在减少设计和工艺的冗余度来提高阵列基板开口率的同时， 不会发生相邻像 素区上覆盖的像素电极短路现象， 提高了显示装置的透光效率以及稳定性。
另外， 在栅极扫描线方向的相邻的像素区上覆盖的像素电极在对应的数 据信号线上方交叠， 这样， 可在液晶盒内形成完全的调制电场， 使得液晶盒 内无漏光的可能性， 可把彩膜基板上的 BM的线宽设计最小化， 以此来提高 像素开口率， 提高显示装置的透光效率。
备选地， 在数据信号线方向上也可将像素电极之间的空隙减少了， 或没 有了， 减少了带来漏光影响的区域， 进一步提高了开口率， 提高显示装置的 透光效率。
备选地， 不仅可以减少栅极扫描线方向上像素电极之间的空隙， 而且还 可以减少数据信号线方向上像素电极之间的空隙。这样，在栅极扫描线方向， 相邻的像素区上覆盖的像素电极之间没有空隙或者空隙被减少， 同时， 数据 信号线方向上相邻像素电极之间的空隙减少了， 或没有了， 从而， 减少了带 来漏光影响的区域， 提高了开口率。 发明的精神和范围。 这样， 倘若本发明的这些修改和变型属于本发明权利要 求及其等同技术的范围之内， 则本发明也意图包含这些改动和变型在内。

Claims

权利要求书
1、 一种阵列基板， 包括：
彼此交叉设置的多条栅极扫描线和多条数据信号线；
多个像素区， 由彼此交叉设置的所述多条栅极扫描线和所述多条数据信 号线限定且排列为矩阵；
多个薄膜晶体管， 分别包括在所述多个像素区的每个像素区中； 以及 多个像素电极， 分别覆盖在所述多个像素区的每个像素区上， 且包括多 个第一像素电极和多个第二像素电极， 其中
所述多个像素区被分为多个第一像素区和多个第二像素区，
所述多个像素区的每个像素区由相邻的两条栅极扫描线和与其交叉的相 邻两条数据信号线限定，
所述多个第一像素区之间间隔设置， 且每个第一像素区上覆盖有对应的 第一像素电极， 所述第一像素电极处于第一层；
所述多个第二像素区之间间隔设置， 且每个第二像素区上覆盖有对应的 第二像素电极， 所述第二像素电极处于第二层；
所述第一层与所述第二层之间设置有绝缘层； 其中， 所述间隔设置指间 隔一个像素区设置。
2、如权利要求 1所述的阵列基板，其中在栅极扫描线方向的相邻的像素 区上覆盖的第一像素电极与第二像素电极在对应的数据信号线上方交叠。
3、如权利要求 1所述的阵列基板，其中在数据信号线方向的相邻的像素 区上覆盖的第一像素电极与第二像素电极在对应的栅极扫描线上方交叠。
4、如权利要求 1所述的阵列基板，其中在栅极扫描线方向的相邻的像素 区上覆盖的第一像素电极与第二像素电极在对应的数据信号线上方交叠， 并 且在数据信号线方向的相邻的像素区上覆盖的第一像素电极与第二像素电极 在对应的栅极扫描线上方交叠。
5、如权利要求 1所述的阵列基板，其中至少一个第一像素电极与对应的 栅极扫描线交叠， 和 /或， 至少一个第二像素电极与对应的栅极扫描线交叠。
6、如权利要求 2所述的阵列基板，其中至少一个第一像素电极与对应的 栅极扫描线交叠， 和 /或， 至少一个第二像素电极与对应的栅极扫描线交叠。
7、如权利要求 1所述的阵列基板，其中所述第一层与所述数据信号线所 在层之间还包括： 树脂层。
8、 一种阵列基板的制造方法， 包括：
在基板上形成包括交叉设置的多条栅极扫描线和多条数据信号线的图 形， 其中， 交叉设置的所述多条栅极扫描线和所述多条数据信号线限定排列 为矩阵的多个像素区， 且所述多个像素区中的每个像素区由相邻的两条栅极 扫描线和与其交叉的相邻两条数据信号线限定， 所述多个像素区分为多个第 一像素区和多个第二像素区；
在形成有所述多条栅极扫描线和所述多条数据信号线的所述基板上形成 多个第一像素电极， 每个第一像素电极对应一个第一像素区， 所述第一像素 电极间隔设置；
在形成有所述多条栅极扫描线、 所述多条数据信号线和所述多个第一像 素电极的基板上形成绝缘层；
在形成有所述多条栅极扫描线、 所述多条数据信号线、 所述多个第一像 素电极和所述绝缘层的基板上形成多个第二像素电极， 每个第二像素电极对 应一个第二像素区， 所述第二像素电极间隔设置， 且设置于未设置第一像素 电极的像素区；
其中， 所述间隔设置指间隔一个像素区设置。
9、如权利要求 8所述的方法，其中在栅极扫描线方向的相邻的像素区上 覆盖的第一像素电极与第二像素电极在对应的数据信号线上方交叠。
10、 如权利要求 8所述的方法， 其中在数据信号线方向的相邻的像素区 上覆盖的第一像素电极与第二像素电极在对应的栅极扫描线上方交叠。
11、 如权利要求 8所述的方法， 其中在栅极扫描线方向的相邻的像素区 上覆盖的第一像素电极与第二像素电极在对应的数据信号线上方交叠， 并且 在数据信号线方向的相邻的像素区上覆盖的第一像素电极与第二像素电极在 对应的栅极扫描线上方交叠。
12、 如权利要求 8所述的方法， 其中至少一个第一像素电极与对应的栅 极扫描线交叠， 和 /或， 至少一个第二像素电极与对应的栅极扫描线交叠。
13、 如权利要求 9所述的方法， 其中至少一个第一像素电极与对应的栅 极扫描线交叠， 和 /或， 至少一个第二像素电极与对应的栅极扫描线交叠。
14、 如权利要求 8所述的方法， 其中所述在形成有所述多条栅极扫描线 和所述多条数据信号线的所述基板上形成多个第一像素电极， 每个第一像素 电极对应一个第一像素区， 所述第一像素电极间隔设置之前， 还包括： 在形成有交叉设置的栅极扫描线和数据信号线的基板上沉积树脂层。
15、 一种显示装置， 包括：
权利要求 1所述的阵列基板；
对置基板， 与所述阵列基板相对置以形成液晶盒； 以及
液晶材料， 填充在所述液晶盒中。
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