CN103676369A - 一种阵列基板及其制造方法、显示器件 - Google Patents

一种阵列基板及其制造方法、显示器件 Download PDF

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CN103676369A
CN103676369A CN201210340180.9A CN201210340180A CN103676369A CN 103676369 A CN103676369 A CN 103676369A CN 201210340180 A CN201210340180 A CN 201210340180A CN 103676369 A CN103676369 A CN 103676369A
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黎蔚
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BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
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Priority to EP13174192.8A priority patent/EP2708941A1/en
Priority to US13/947,602 priority patent/US9196736B2/en
Priority to JP2013172025A priority patent/JP2014056237A/ja
Priority to KR1020130110378A priority patent/KR20140035292A/ko
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Abstract

本发明公开了一种阵列基板，所述阵列基板包括基板，在基板的每个像素区域内形成有至少一条公共电极线，公共电极线为纵向设置且平行于数据线。本发明还公开了一种阵列基板的制造方法及显示器件，将公共电极线设置为纵向布局且平行于数据线。采用本发明，能减少交叠面积，节约了面积从而能实现宽屏显示。

Description

一种阵列基板及其制造方法、显示器件
技术领域
本发明涉及显示技术领域，尤其涉及一种阵列基板及其制造方法、显示器件。
背景技术
薄膜晶体管液晶显示器(TFT-LCD)具有体积小、功耗低、无辐射、制造成本相对较低等特点，在当前的平板显示器市场占据了主导地位。
针对现有阵列基板的像素结构而言，像素由数据信号线和栅极信号线交错形成，像素中包含像素电极(pixel)和作为开关的薄膜晶体管(TFT)，其中，TFT的栅极连接栅极信号线，源极连接数据信号线，漏极与像素电极连接。公共电极(Vcom)与像素电极之间形成存储电容Cst。
如图1所示，图1所示为现有阵列基板的结构示意图，Vcom6一般设置在栅极层，并采用与TFT的栅极53相同的金属材料制得。如图2所示，图2为现有阵列基板的双栅结构像素阵列示意图，阵列基板包括基板，在基板上形成有矩阵方式排列的像素区域，每个像素区域内形成有位于奇数列的第一像素电极和第一薄膜晶体管，位于偶数列的第二像素电极和第二薄膜晶体管，第一薄膜晶体管的漏极与第一像素电极连接，第二薄膜晶体管的漏极与第二像素电极连接，每个像素区域内形成有第一栅线和第二栅线，第一栅线与第一薄膜晶体管的栅极连接，第二栅线与第二薄膜晶体管的栅极连接，每个像素区域内形成有一条数据线，数据线分别与偶数列的第二薄膜晶体管的源极、同一行下一像素区域内奇数列的第一薄膜晶体管的源极连接或数据线分别与奇数列的第一薄膜晶体管的源极、同一行上一像素区域内偶数列的第二薄膜晶体管的源极连接。
综上所述，目前的阵列基板虽然采用双栅结构，但是公共电极与像素电极的交叠面积过大，且公共电极线为横向设置，不利于宽屏显示。
发明内容
有鉴于此，本发明的主要目的在于提供一种阵列基板及其制造方法和显示器件，能减少公共电极与像素电极的交叠面积，节约了面积从而能实现宽屏显示。
为达到上述目的，本发明的技术方案是这样实现的：
一种阵列基板，在基板的每个像素区域内形成有位于奇数列的第一像素电极和位于偶数列的第二像素电极，其中，所述像素区域内形成有至少一条公共电极线，所述公共电极线为纵向设置且平行于数据线。
其中，所述公共电极线和所述数据线与源漏极形成于同一层。
其中，所述公共电极线位于每两条数据线之间，所述位于奇数列的第一像素电极与所述位于偶数列的第二像素电极共用一根公共电极线。
其中，所述公共电极线的布线方式为外部布线方式。
其中，所述公共电极线的布线方式为内部布线方式。
一种阵列基板的制造方法，在基板的每个像素区域内形成有位于奇数列的第一像素电极和位于偶数列的第二像素电极，该方法包括：
将至少一条公共电极线形成在每个像素区域内，将公共电极线设置为纵向布局且平行于数据线。
其中，该方法还包括：将所述公共电极线和所述数据线与源漏极设置于同一层。
其中，该方法还包括：设置所述公共电极线位于每两条数据线之间，所述位于奇数列的第一像素电极与所述位于偶数列的第二像素电极共用一根公共电极线。
其中，所述公共电极线的布线方式为外部布线方式或内部布线方式。
一种显示器件，该显示器件包括权利要求1至5任一项所述的阵列基板。
本发明的阵列基板，采用双栅结构，且在基板的每个像素区域内形成有公共电极线，该公共电极线为纵向设置且平行于数据线，该公共电极线位于每两条数据线之间。
采用本发明，由于公共电极线为纵向设置且平行于数据线，因此，能减少公共电极与像素电极的交叠面积，节约了面积从而能实现宽屏显示。
附图说明
图1为现有阵列基板的结构示意图；
图2为现有阵列基板的双栅结构像素阵列示意图；
图3为本发明阵列基板的结构示意图；
图4为本发明阵列基板像素阵列的一结构示意图；
图5为本发明阵列基板像素阵列的另一种结构示意图。
附图标记说明
1，像素电极；51，源极；52、漏极；53、栅极；54、有源层；55、栅绝缘层；6、公共电极；7、液晶；8、彩膜基板；9、透明电极；10、阵列基板。
具体实施方式
目前，双栅结构越来越被普通应用于阵列基板中。本发明的阵列基板也基于双栅结构，包括基板，在基板上形成有矩阵方式排列的像素区域，每个像素区域内形成有位于奇数列的第一像素电极和第一薄膜晶体管，位于偶数列的第二像素电极和第二薄膜晶体管，第一薄膜晶体管的漏极与第一像素电极连接，第二薄膜晶体管的漏极与第二像素电极连接，每个像素区域内形成有第一栅线和第二栅线，第一栅线与第二薄膜晶体管的栅极连接，第二栅线与第一薄膜晶体管的栅极连接，每个像素区域内形成有一条数据线，数据线与偶数列的第二薄膜晶体管的源极连接、数据线与同一行下一像素区域内奇数列的第一薄膜晶体管的源极连接；或者，数据线与奇数列的第一薄膜晶体管的源极连接、数据线与同一行上一像素区域内偶数列的第二薄膜晶体管的源极连接，每个像素区域内形成有至少一条公共电极线，公共电极线为纵向设置且平行于数据线。
上述方案对应的有益效果为：采用双栅结构的阵列基板中，每行像素连接在两条不同的栅极信号线上，每条数据信号线可以连接两列像素，这样，每四列像素只需要两条数据信号线即可。例如，对于阵列基板的像素阵列为六列两行像素的情况，需要设置四条栅极信号线G1～G4，而只需要设置三条数据信号线D1、D2、D3即可。采用本发明，由于将公共电极线设置为纵向布局，区别于现有技术的公共电极线横向布局，从而使交叠面积变小，由于节约了面积，从而能实现宽屏显示。
这里，公共电极线和数据线与源漏极形成于同一层，减小了公共电极信号线与像素电极之间的间距。
本发明的阵列基板结构如图3所示，所述阵列基板可以包括像素电极1、TFT、公共电极6、液晶7、彩膜基板8、透明电极9、阵列基板10；其中，TFT包括栅极53、有源层54、栅绝缘层55、源极51和漏极52(源漏极一般简称为S/D)，其中，像素电极1和透明电极9之间充有液晶7，透明电极9形成在彩膜基板8的下表面上，TFT、像素电极1、以及公共电极6均形成在阵列基板10上。具体地，公共电极6及公共电极信号线(图3未示出)与源漏极形成于同一层，即公共电极6及公共电极信号线形成于S/D层。其中，公共电极6及公共电极信号线还采用与S/D层相同的金属材料制得。一般情况下，S/D层可以采用包含有Mo、AlNd、Al、Ti、Cu等导电金属材料，同样，公共电极6及公共电极信号线也采用包含有Mo、AlNd、Al、Ti、Cu等的导电金属材料。
上述方案对应的有益效果为：公共电极(Vcom)与像素电极之间形成存储电容Cst，Cst的计算公式为：Cst＝S/D；其中，S表示像素电极与Vcom之间的交叠面积；D表示像素电极与Vcom6之间的间距。对比图1和图3可知，由于本发明是将公共电极线和数据线与源漏极形成于同一层，区别于现有技术是将公共电极线与栅极形成于同一层，则采用本发明使像素电极与Vcom之间的间距变小了，从而避免了现有技术在像素电极与Vcom之间的间距较大的情况下，为了确保Cst不变必须增大像素电极与Vcom之间的交叠面积所带来的一系列不利影响，如面积变大，导致像素电极的开口率减小，公共电极线的电阻增加；像素电极开口率的减小会加大液晶面板功率消耗，公共电极线的电阻增加会加大Vcom电压的偏移，Vcom偏移导致液晶面板有偏色，产生greenish不良。
这里，公共电极线位于每两条数据线之间，位于奇数列的第一像素电极与所述位于偶数列的第二像素电极共用一根公共电极线。
需要说明的是，本发明中的公共电极线只要纵向设置即可，并不限制每个像区域内都必须有公共电极线，可以几组像素区域共用一条纵向公共电极线，此时其他没有设置纵向公共电极线的像素区域内的公共电极通过横向布线相互电连接，设置的纵向公共电极线采用外部布线方式。
这里，公共电极线的布线方式为外部布线方式或内部布线方式。图4所采用的像素阵列的公共电极线为外部布线方式，图5所采用的像素阵列的公共电极线为内部布线方式。所述外部布线方式是指将公共电极线在显示区域外的区域(一般称为fanout区域)通过公共电极线将各公共电极电性连接，内部布线方式具体如图5所示，在每行像素之间通过设置公共电极信号线将各公共电极电性连接。
需要说明的是，双栅结构不仅仅限于上述描述的结构，还可以为COA(colorfilter on array，彩膜集成在阵列基板的技术)结构，当然可以理解的是，本发明保护的是双栅结构中纵向公共电极线的布线方式，并不限制其载体。另，本发明也可适用于双数据线的结构中，在双数据线结构中设置纵向公共电极线，可进一步实现宽屏显示。
一种阵列基板的制造方法，在基板的每个像素区域内形成有位于奇数列的第一像素电极和位于偶数列的第二像素电极，该方法包括：将至少一条公共电极线形成在每个像素区域内，将公共电极线设置为纵向布局且平行于数据线。
这里，该方法还包括：将公共电极线和数据线与源漏极设置于同一层。
这里，该方法还包括：设置公共电极线位于每两条数据线之间，设置位于奇数列的第一像素电极与位于偶数列的第二像素电极共用一根公共电极线。
这里，公共电极线的布线方式为外部布线方式或内部布线方式。
上述描述的实现方式可以为现有技术中的构图工艺，举例说明，将公共电极线和数据线与源漏极设置于同一层，步骤可以为先将材料沉积在需要形成源漏极的基板上，之后再利用曝光、显影、剥离等工艺同时形成源漏极和公共电极线，在此不一一描述。
一种显示器件，该显示器件包括上述提到的阵列基板。
本发明的显示器件，包括有设置纵向电极线的阵列基板，可以实现宽屏显示，且公共电极线和源漏极同层设置，可以进一步减少像素电极和公共电极的重叠面积。
以上所述，仅为本发明的较佳实施例而已，并非用于限定本发明的保护范围。

Claims (10)

1.一种阵列基板，在基板的每个像素区域内形成有位于奇数列的第一像素电极和位于偶数列的第二像素电极，其特征在于，所述像素区域内形成有至少一条公共电极线，所述公共电极线为纵向设置且平行于数据线。
2.根据权利要求1所述的阵列基板，其特征在于，所述公共电极线和所述数据线与源漏极形成于同一层。
3.根据权利要求1或2所述的阵列基板，其特征在于，所述公共电极线位于每两条数据线之间，所述位于奇数列的第一像素电极与所述位于偶数列的第二像素电极共用一根公共电极线。
4.根据权利要求1或2所述的阵列基板，其特征在于，所述公共电极线的布线方式为外部布线方式。
5.根据权利要求1或2所述的阵列基板，其特征在于，所述公共电极线的布线方式为内部布线方式。
6.一种阵列基板的制造方法，在基板的每个像素区域内形成有位于奇数列的第一像素电极和位于偶数列的第二像素电极，其特征在于，该方法包括：
将至少一条公共电极线形成在每个像素区域内，将公共电极线设置为纵向布局且平行于数据线。
7.根据权利要求6所述的方法，其特征在于，该方法还包括：将所述公共电极线和所述数据线与源漏极设置于同一层。
8.根据权利要求6或7所述的方法，其特征在于，该方法还包括：设置所述公共电极线位于每两条数据线之间，所述位于奇数列的第一像素电极与所述位于偶数列的第二像素电极共用一根公共电极线。
9.根据权利要求6或7所述的方法，其特征在于，所述公共电极线的布线方式为外部布线方式或内部布线方式。
10.一种显示器件，其特征在于，该显示器件包括权利要求1至5任一项所述的阵列基板。
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