WO2014040043A1 - Non-volatile array wakeup and backup sequencing control - Google Patents

Non-volatile array wakeup and backup sequencing control Download PDF

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Publication number
WO2014040043A1
WO2014040043A1 PCT/US2013/058990 US2013058990W WO2014040043A1 WO 2014040043 A1 WO2014040043 A1 WO 2014040043A1 US 2013058990 W US2013058990 W US 2013058990W WO 2014040043 A1 WO2014040043 A1 WO 2014040043A1
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WO
WIPO (PCT)
Prior art keywords
logic element
nvl
volatile logic
element arrays
volatile
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2013/058990
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English (en)
French (fr)
Inventor
Steven Craig BARTLING
Sudhanshu KHANNA
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Texas Instruments Japan Ltd
Texas Instruments Inc
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Texas Instruments Japan Ltd
Texas Instruments Inc
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Publication date
Application filed by Texas Instruments Japan Ltd, Texas Instruments Inc filed Critical Texas Instruments Japan Ltd
Priority to CN201380046963.9A priority Critical patent/CN104603715B/zh
Publication of WO2014040043A1 publication Critical patent/WO2014040043A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3287—Power saving characterised by the action undertaken by switching off individual functional units in the computer system
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/30—Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/325—Power saving in peripheral device
    • G06F1/3275—Power saving in memory, e.g. RAM, cache
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
    • G06F11/1032—Simple parity
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operations
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1415—Saving, restoring, recovering or retrying at system level
    • G06F11/1438—Restarting or rejuvenating
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operations
    • G06F11/1446—Point-in-time backing up or restoration of persistent data
    • G06F11/1458—Management of the backup or restore process
    • G06F11/1469—Backup restoration techniques
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0683—Plurality of storage devices
    • G06F3/0688—Non-volatile semiconductor memory arrays
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/4401—Bootstrapping
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/4401—Bootstrapping
    • G06F9/4406—Loading of operating system
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/3562—Bistable circuits of the primary-secondary type
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/50—Reducing energy consumption in communication networks in wire-line communication networks, e.g. low power modes or reduced link rate

Definitions

  • Energy harvesting also known as power harvesting or energy scavenging, is the process by which energy is derived from external sources, captured, and stored for small, wireless autonomous devices, such as those used in wearable electronics and wireless sensor networks.
  • Harvested energy may be derived from various sources, such as: solar power, thermal energy, wind energy, salinity gradients, and kinetic energy, etc.
  • typical energy harvesters provide a very small amount of power for low-energy electronics.
  • the energy source for energy harvesters is present as ambient background and is available for use. For example, temperature gradients exist from the operation of a combustion engine, and in urban areas, there is a large amount of electromagnetic energy in the environment because of radio and television broadcasting, etc.
  • FIG. 17 is a block diagram of an example power detection arrangement as configured in accordance with various embodiments of the invention.
  • FIG. 19 is a flow chart illustrating an example operation of a processing device exercising wakeup and backup sequencing control as configured in accordance with various embodiments of the invention.
  • a data input may be latched by a first latch.
  • a second latch coupled to the first latch may receive the data input for retention while the first latch is inoperative in a standby power mode.
  • the first latch receives power from a first power line that is switched off during the standby power mode.
  • the second latch receives power from a second power line that remains on during the standby mode.
  • a controller receives a clock input and a retention signal and provides a clock output to the first latch and the second latch.
  • a change in the retention signal is indicative of a transition to the standby power mode.
  • the first power domain is divided into a first portion configured to supply power to switched logic elements associated with the first function and a second portion configured to supply power to switched logic elements associated with the second function.
  • the first portion and the second portion of the first power domain are individually configured to be powered up or down independently of other portions of the first power domain.
  • the third power domain can be divided into a first portion configured to supply power to non-volatile logic element arrays associated with the first function and a second portion configured to supply power to non-volatile logic element arrays associated with the second function.
  • these additional elements are disposed in the slave stage 222 of the associated FF.
  • the additional transistors are not on the critical path of the FF and have only 1.8% and 6.9% impact on normal FF performance and power (simulation data) in this particular implementation.
  • the NU (NVL-Update) control input is pulsed high for a cycle to write to the FF.
  • the thirty-one bit data output of an NVL array fans out to ND ports of eight thirty-one bit FF groups.
  • Q outputs of 248 FFs are connected to the 31b parallel data input of NVL array 110 through a 31b wide 8-1 mux 212.
  • the mux may be broken down into smaller muxes based on the layout of the FF cloud and placed close to the FFs they serve.
  • the NVL controller synchronizes writing to the NVL array, and the select signals MUX_SEL ⁇ 2:0> of 8-1 mux 212.
  • Vdd is 1.5 volts and the ground reference plane has a value of 0 volts.
  • a logic high has a value of approximately 1.5 volts, while a logic low has a value of approximately 0 volts.
  • Other embodiments that use logic levels that are different from ground for logic 0 (low) and Vdd for logic 1 (high) would clamp nodes Q, QB to a voltage corresponding to the quiescent plate line voltage so that there is effectively no voltage across the FeCaps when the bitcell is not being accessed.
  • At least one of the plurality of nonvolatile logic element arrays is configured to store a boot state representing a state of the computing device apparatus after a given amount of a boot process is completed.
  • the at least one non-volatile logic controller in this approach is configured to control restoration of data representing the boot state from the at least one of the plurality of non-volatile logic element arrays to corresponding ones of the plurality of volatile storage elements in response to detecting a previous system reset or power loss event for the computing device apparatus.
  • the at least one non-volatile logic controller can be configured to execute a round-trip data restoration operation that automatically writes back data to an individual non- volatile logic element after reading data from the individual non- volatile logic element without completing separate read and write operations.
  • the pass line PASS is switched low at the sixth time S6, and the sense amplifier enable signal SAEN is switched law at the seventh time S7.
  • a clear signal CLR is switched from low to high to clamp the aspects of the individual non-volatile logic element to the electrical ground to help maintain data integrity as discussed herein. This process includes a lower total number of transitions than what is needed for distinct and separate read and write operations (read, then write). This lowers the overall energy consumption.
  • BL and the read capacitors are precharged to VDD/2 before the pass gates 802, 822, and 823 are enabled in order to minimize signal loss via charge sharing when the recovered signals on Q are transferred via BL to the read storage capacitors 820 and 821.
  • PL1 is toggled back low and node Q is discharged using clamp transistor 806 during time period s2.
  • PL2 is toggled high keeping PL1 low during time period s3.
  • a new voltage 904 develops on node Q, but this time with the opposite capacitor ratio.
  • This voltage is then stored on another external read capacitor 821 via transfer gate 823.
  • Sense amplifier 810 can then determine the state of the bitcell by using the voltages stored on the external read capacitors 820, 821.
  • FIG. 11 is a more detailed schematic of a set of input/output circuits 1150 used in the NVL array of FIG. 10.
  • each IO set 1045 of the thirty-two drivers in IO block 1044 is similar to IO circuits 1150.
  • I/O block 1044 provides several features to aid testability of NVL bits.
  • FIG. 12A is a timing diagram illustrating an offset voltage test during a read cycle. To apply a disturb voltage to a bitcell, state si is modified during a read. This FIG. illustrates a voltage disturb test for reading a data value of "0" (node Q); a voltage disturb test for a data value of " 1" is similar, but injects the disturb voltage onto the opposite side of the sense amp (node QB).
  • VDDL/VDDN_CV can be any valid voltage less than or equal to VDDN FV and the circuit will function correctly.
  • FIG. 14 is a block diagram illustrating power domains within NVL array 110.
  • VDDL Variable logic voltage
  • Data output buffers within IO buffer block 1044 are in the NVL logic power domain VDDN CV and therefore may remain off while domain VDDR (or VDDL depending on the specific implementation) is ON during normal operation of the chip. ISO-Low isolation is implemented to tie all such signals to ground during such a situation. While VDDN CV is off, logic connected to data outputs in VDDR (or VDDL depending on the specific implementation) domain in random logic area may generate short circuit current between power and ground in internal circuits if any signals from the VDDN CV domain are floating (not driven when VDDN CV domain is powered down) if they are not isolated.
  • VDDN domain is needed on control inputs of the NVL arrays that go to the NVL bitcells, such as: row enables, PL1, PL2, restore, recall, and clear, for example. This enables a reduction in system power dissipation by allowing blocks of SOC logic and NVL logic gates that can operate at a lower voltage to do so.
  • word line drivers 1042 that drive the signals for each row of bitcells, including plate lines PL1, PL2, transfer gate enable PASS, sense amp enable SAEN, clear enable CLR, and voltage margin test enable VCON, for example.
  • the bitcell array 1040 and the wordline circuit block 1042 are supplied by VDDN.
  • FIG. 16 is a timing diagram illustrating operation of level shifting using a sense amp within a ferroelectric bitcell.
  • Input data that is provided to NVL array 110 from multiplexor 212, referring again to FIG. 2, also needs to be level shifted from the 1.2v VDDL domain to 1.5 volts needed for best operation of the FeCaps in the 1.5 volt VDDN domain during write operations. This may be done using the sense amp of bit cell 400, for example.
  • each bit line BL such as BL 1352, which comes from the 1.2 volt VDDL domain, is coupled to transfer gate 402 or 403 within bitcell 400.
  • Sense amp 410 operates in the 1.5v VDDN power domain.
  • the NVL arrays receive signals from the associated NVL controller during both read and write, whereas the first multiplexer 212 receives signals during a write to NVL array process and the second multiplexer 1822 receives signals during a read from NVL arrays process.
  • a nonvolatile FeCap bitcell from an NVL array may be coupled to flip-flop or latch that does not include a low power retention latch.
  • the system would transition between a full power state, or otherwise reduced power state based on reduced voltage or clock rate, and a totally off power state, for example.
  • the state of the flipflops and latches would be saved in distributed NVL arrays.
  • the flipflops When power is restored, the flipflops would be initialized via an input provided by the associated NVL array bitcell.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Software Systems (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Human Computer Interaction (AREA)
  • Computer Security & Cryptography (AREA)
  • Power Sources (AREA)
  • Logic Circuits (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Microcomputers (AREA)
  • Semiconductor Memories (AREA)
PCT/US2013/058990 2012-09-10 2013-09-10 Non-volatile array wakeup and backup sequencing control Ceased WO2014040043A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201380046963.9A CN104603715B (zh) 2012-09-10 2013-09-10 非易失性阵列唤醒和备份排序控制

Applications Claiming Priority (4)

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US201261698906P 2012-09-10 2012-09-10
US61/698,906 2012-09-10
US13/770,280 US9830964B2 (en) 2012-09-10 2013-02-19 Non-volatile array wakeup and backup sequencing control
US13/770,280 2013-02-19

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WO2014040043A1 true WO2014040043A1 (en) 2014-03-13

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Family Applications (9)

Application Number Title Priority Date Filing Date
PCT/US2013/058990 Ceased WO2014040043A1 (en) 2012-09-10 2013-09-10 Non-volatile array wakeup and backup sequencing control
PCT/US2013/059006 Ceased WO2014040051A1 (en) 2012-09-10 2013-09-10 Processing device with restricted power domain wakeup restore from nonvolatile logic array
PCT/US2013/058867 Ceased WO2014040009A1 (en) 2012-09-10 2013-09-10 Nonvolatile logic array and power domain segmentation in processing device
PCT/US2013/059036 Ceased WO2014040065A1 (en) 2012-09-10 2013-09-10 Nonvolatile logic array based computing over inconsistent power supply
PCT/US2013/058871 Ceased WO2014040011A1 (en) 2012-09-10 2013-09-10 Nonvolatile logic array with retention flip flops to reduce switching power during wakeup
PCT/US2013/058875 Ceased WO2014040012A1 (en) 2012-09-10 2013-09-10 Customizable backup and restore from nonvolatile logic array
PCT/US2013/058998 Ceased WO2014040047A1 (en) 2012-09-10 2013-09-10 Control of dedicated non-volatile arrays for specific function availability
PCT/US2013/059030 Ceased WO2014040062A1 (en) 2012-09-10 2013-09-10 Configuration bit sequencing control of nonvolatile domain and array wakeup and backup
PCT/US2013/059020 Ceased WO2014040058A1 (en) 2012-09-10 2013-09-10 Boot state restore from nonvolatile bitcell array

Family Applications After (8)

Application Number Title Priority Date Filing Date
PCT/US2013/059006 Ceased WO2014040051A1 (en) 2012-09-10 2013-09-10 Processing device with restricted power domain wakeup restore from nonvolatile logic array
PCT/US2013/058867 Ceased WO2014040009A1 (en) 2012-09-10 2013-09-10 Nonvolatile logic array and power domain segmentation in processing device
PCT/US2013/059036 Ceased WO2014040065A1 (en) 2012-09-10 2013-09-10 Nonvolatile logic array based computing over inconsistent power supply
PCT/US2013/058871 Ceased WO2014040011A1 (en) 2012-09-10 2013-09-10 Nonvolatile logic array with retention flip flops to reduce switching power during wakeup
PCT/US2013/058875 Ceased WO2014040012A1 (en) 2012-09-10 2013-09-10 Customizable backup and restore from nonvolatile logic array
PCT/US2013/058998 Ceased WO2014040047A1 (en) 2012-09-10 2013-09-10 Control of dedicated non-volatile arrays for specific function availability
PCT/US2013/059030 Ceased WO2014040062A1 (en) 2012-09-10 2013-09-10 Configuration bit sequencing control of nonvolatile domain and array wakeup and backup
PCT/US2013/059020 Ceased WO2014040058A1 (en) 2012-09-10 2013-09-10 Boot state restore from nonvolatile bitcell array

Country Status (4)

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US (18) US9830964B2 (enExample)
JP (4) JP6336985B2 (enExample)
CN (12) CN104603759B (enExample)
WO (9) WO2014040043A1 (enExample)

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