DE60316068T8 - Prüfverfahren und -gerät für Konfigurationsspeicherzellen in programmierbaren logischen Bauelementen (PLDS) - Google Patents

Prüfverfahren und -gerät für Konfigurationsspeicherzellen in programmierbaren logischen Bauelementen (PLDS) Download PDF

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Publication number
DE60316068T8
DE60316068T8 DE60316068T DE60316068T DE60316068T8 DE 60316068 T8 DE60316068 T8 DE 60316068T8 DE 60316068 T DE60316068 T DE 60316068T DE 60316068 T DE60316068 T DE 60316068T DE 60316068 T8 DE60316068 T8 DE 60316068T8
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DE
Germany
Prior art keywords
plds
memory cells
programmable logic
test method
logic devices
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE60316068T
Other languages
English (en)
Other versions
DE60316068D1 (de
DE60316068T2 (de
Inventor
Shalini Pathak
Parvesh Swami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SICRONIC REMOTE KG,LLC, WILMINGTON, DEL., US
Original Assignee
SICRONIC REMOTE KG Wilmington LLC
Sicronic Remote KG LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SICRONIC REMOTE KG Wilmington LLC, Sicronic Remote KG LLC filed Critical SICRONIC REMOTE KG Wilmington LLC
Publication of DE60316068D1 publication Critical patent/DE60316068D1/de
Publication of DE60316068T2 publication Critical patent/DE60316068T2/de
Application granted granted Critical
Publication of DE60316068T8 publication Critical patent/DE60316068T8/de
Active legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/025—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in signal lines
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318516—Test of programmable logic devices [PLDs]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Logic Circuits (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Tests Of Electronic Circuits (AREA)
DE60316068T 2002-05-13 2003-05-12 Prüfverfahren und -gerät für Konfigurationsspeicherzellen in programmierbaren logischen Bauelementen (PLDS) Active DE60316068T8 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
INDE05502002 2002-05-13
IN550DE2002 2002-05-13

Publications (3)

Publication Number Publication Date
DE60316068D1 DE60316068D1 (de) 2007-10-18
DE60316068T2 DE60316068T2 (de) 2008-06-05
DE60316068T8 true DE60316068T8 (de) 2009-02-26

Family

ID=29266776

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60316068T Active DE60316068T8 (de) 2002-05-13 2003-05-12 Prüfverfahren und -gerät für Konfigurationsspeicherzellen in programmierbaren logischen Bauelementen (PLDS)

Country Status (3)

Country Link
US (1) US7167404B2 (de)
EP (1) EP1363132B1 (de)
DE (1) DE60316068T8 (de)

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US7266020B1 (en) 2005-07-19 2007-09-04 Xilinx, Inc. Method and apparatus for address and data line usage in a multiple context programmable logic device
US7212448B1 (en) * 2005-07-19 2007-05-01 Xilinx, Inc. Method and apparatus for multiple context and high reliability operation of programmable logic devices
US7250786B1 (en) 2005-07-19 2007-07-31 Xilinx, Inc. Method and apparatus for modular redundancy with alternative mode of operation
US7409610B1 (en) * 2005-07-20 2008-08-05 Xilinx, Inc. Total configuration memory cell validation built in self test (BIST) circuit
US7539914B1 (en) * 2006-01-17 2009-05-26 Xilinx, Inc. Method of refreshing configuration data in an integrated circuit
KR100746228B1 (ko) * 2006-01-25 2007-08-03 삼성전자주식회사 반도체 메모리 모듈 및 반도체 메모리 장치
US7596744B1 (en) * 2006-02-24 2009-09-29 Lattice Semiconductor Corporation Auto recovery from volatile soft error upsets (SEUs)
US7353474B1 (en) * 2006-04-18 2008-04-01 Xilinx, Inc. System and method for accessing signals of a user design in a programmable logic device
US8065574B1 (en) 2007-06-08 2011-11-22 Lattice Semiconductor Corporation Soft error detection logic testing systems and methods
US8073996B2 (en) * 2008-01-09 2011-12-06 Synopsys, Inc. Programmable modular circuit for testing and controlling a system-on-a-chip integrated circuit, and applications thereof
KR101593603B1 (ko) * 2009-01-29 2016-02-15 삼성전자주식회사 반도체 장치의 온도 감지 회로
JP2013012966A (ja) * 2011-06-30 2013-01-17 Olympus Corp 撮像装置
US9830964B2 (en) * 2012-09-10 2017-11-28 Texas Instruments Incorporated Non-volatile array wakeup and backup sequencing control
US9154137B2 (en) * 2013-07-04 2015-10-06 Altera Corporation Non-intrusive monitoring and control of integrated circuits
US9330040B2 (en) 2013-09-12 2016-05-03 Qualcomm Incorporated Serial configuration of a reconfigurable instruction cell array
US10956265B2 (en) 2015-02-03 2021-03-23 Hamilton Sundstrand Corporation Method of performing single event upset testing
JP2016167669A (ja) * 2015-03-09 2016-09-15 富士通株式会社 プログラマブル論理回路装置及びそのエラー検出方法
US10417078B2 (en) * 2016-04-08 2019-09-17 Lattice Semiconductor Corporation Deterministic read back and error detection for programmable logic devices
US10523209B1 (en) 2017-11-14 2019-12-31 Flex Logix Technologies, Inc. Test circuitry and techniques for logic tiles of FPGA
US12020972B2 (en) * 2020-04-29 2024-06-25 Semiconductor Components Industries, Llc Curved semiconductor die systems and related methods
US11948653B2 (en) * 2021-07-20 2024-04-02 Avago Technologies International Sales Pte. Limited Early error detection and automatic correction techniques for storage elements to improve reliability

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Also Published As

Publication number Publication date
DE60316068D1 (de) 2007-10-18
US7167404B2 (en) 2007-01-23
DE60316068T2 (de) 2008-06-05
EP1363132B1 (de) 2007-09-05
EP1363132A3 (de) 2004-02-04
US20040015758A1 (en) 2004-01-22
EP1363132A2 (de) 2003-11-19

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Legal Events

Date Code Title Description
8327 Change in the person/name/address of the patent owner

Owner name: SICRONIC REMOTE KG,LLC, WILMINGTON, DEL., US

8364 No opposition during term of opposition