DE60316647D1 - Halbleiterspeichereinrichtung und Prüfungsverfahren - Google Patents

Halbleiterspeichereinrichtung und Prüfungsverfahren

Info

Publication number
DE60316647D1
DE60316647D1 DE60316647T DE60316647T DE60316647D1 DE 60316647 D1 DE60316647 D1 DE 60316647D1 DE 60316647 T DE60316647 T DE 60316647T DE 60316647 T DE60316647 T DE 60316647T DE 60316647 D1 DE60316647 D1 DE 60316647D1
Authority
DE
Germany
Prior art keywords
memory device
semiconductor memory
test method
test
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60316647T
Other languages
English (en)
Other versions
DE60316647T2 (de
Inventor
Yuji Nakagawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Semiconductor Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of DE60316647D1 publication Critical patent/DE60316647D1/de
Application granted granted Critical
Publication of DE60316647T2 publication Critical patent/DE60316647T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C29/50016—Marginal testing, e.g. race, voltage or current testing of retention
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40615—Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/46—Test trigger logic
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
DE60316647T 2002-08-08 2003-07-24 Halbleiterspeichereinrichtung und Prüfungsverfahren Expired - Lifetime DE60316647T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2002231645 2002-08-08
JP2002231645A JP4408193B2 (ja) 2002-08-08 2002-08-08 半導体記憶装置及び半導体記憶装置の試験方法

Publications (2)

Publication Number Publication Date
DE60316647D1 true DE60316647D1 (de) 2007-11-15
DE60316647T2 DE60316647T2 (de) 2008-01-31

Family

ID=31492380

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60316647T Expired - Lifetime DE60316647T2 (de) 2002-08-08 2003-07-24 Halbleiterspeichereinrichtung und Prüfungsverfahren

Country Status (7)

Country Link
US (1) US6813203B2 (de)
EP (1) EP1396863B1 (de)
JP (1) JP4408193B2 (de)
KR (1) KR100936418B1 (de)
CN (1) CN100447897C (de)
DE (1) DE60316647T2 (de)
TW (1) TWI227030B (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100583152B1 (ko) * 2004-02-19 2006-05-23 주식회사 하이닉스반도체 데이터 억세스타임 측정모드를 갖는 반도체 메모리 소자
US7632587B2 (en) 2004-05-04 2009-12-15 Angstrom Power Incorporated Electrochemical cells having current-carrying structures underlying electrochemical reaction layers
US7378176B2 (en) * 2004-05-04 2008-05-27 Angstrom Power Inc. Membranes and electrochemical cells incorporating such membranes
JP2006073062A (ja) * 2004-08-31 2006-03-16 Toshiba Corp 半導体記憶装置
JP4591836B2 (ja) 2006-05-22 2010-12-01 エルピーダメモリ株式会社 半導体記憶装置及びそのテスト方法
KR100878301B1 (ko) * 2007-05-10 2009-01-13 주식회사 하이닉스반도체 다중 테스트 모드를 지원하는 테스트 회로
EP2210303B1 (de) 2007-09-25 2017-04-05 Intelligent Energy Limited Brennstoffzellensysteme mit raumsparendem fluidplenum und diesbezügliche verfahren
US7890286B2 (en) * 2007-12-18 2011-02-15 Hynix Semiconductor Inc. Test circuit for performing multiple test modes
KR101022675B1 (ko) 2008-06-04 2011-03-22 주식회사 하이닉스반도체 반도체 소자
KR101062756B1 (ko) * 2009-07-30 2011-09-06 주식회사 하이닉스반도체 테스트 모드 신호 생성 장치
CN103839590B (zh) * 2014-03-18 2016-09-21 龙芯中科技术有限公司 存储器时序参数的测量装置、方法及存储器芯片
JP6429260B1 (ja) * 2017-11-09 2018-11-28 華邦電子股▲ふん▼有限公司Ｗｉｎｂｏｎｄ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏｒｐ． 疑似スタティックランダムアクセスメモリおよびそのリフレッシュ方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0239916B1 (de) * 1986-03-24 1994-06-08 Nec Corporation Halbleiterspeichervorrichtung mit einem Testmodus und einem Standardmodusbetrieb
FR2638865B1 (fr) * 1988-11-04 1990-12-28 Labo Electronique Physique Analyseur logique avec double declenchement
US5563843A (en) * 1995-03-09 1996-10-08 Intel Corporation Method and circuitry for preventing propagation of undesired ATD pulses in a flash memory device
JP4495308B2 (ja) * 2000-06-14 2010-07-07 株式会社アドバンテスト 半導体デバイス試験方法・半導体デバイス試験装置
JP3778417B2 (ja) * 2000-02-29 2006-05-24 富士通株式会社 半導体記憶装置
KR100378198B1 (ko) * 2001-05-08 2003-03-29 삼성전자주식회사 반도체 장치의 모드 제어 회로 및 이를 구비하는 반도체메모리 장치
JP2003066108A (ja) * 2001-08-28 2003-03-05 Mitsubishi Electric Corp 半導体テスト回路

Also Published As

Publication number Publication date
KR20040014237A (ko) 2004-02-14
CN1495796A (zh) 2004-05-12
US6813203B2 (en) 2004-11-02
US20040027895A1 (en) 2004-02-12
EP1396863A1 (de) 2004-03-10
TWI227030B (en) 2005-01-21
JP2004071098A (ja) 2004-03-04
DE60316647T2 (de) 2008-01-31
TW200404305A (en) 2004-03-16
KR100936418B1 (ko) 2010-01-12
CN100447897C (zh) 2008-12-31
EP1396863B1 (de) 2007-10-03
JP4408193B2 (ja) 2010-02-03

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU MICROELECTRONICS LTD., TOKYO, JP

8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU SEMICONDUCTOR LTD., YOKOHAMA, KANAGAWA, JP

8328 Change in the person/name/address of the agent

Representative=s name: SEEGER SEEGER LINDNER PARTNERSCHAFT PATENTANWAELTE