JP4591836B2 - 半導体記憶装置及びそのテスト方法 - Google Patents
半導体記憶装置及びそのテスト方法 Download PDFInfo
- Publication number
- JP4591836B2 JP4591836B2 JP2006141041A JP2006141041A JP4591836B2 JP 4591836 B2 JP4591836 B2 JP 4591836B2 JP 2006141041 A JP2006141041 A JP 2006141041A JP 2006141041 A JP2006141041 A JP 2006141041A JP 4591836 B2 JP4591836 B2 JP 4591836B2
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- input
- signal
- reference voltage
- semiconductor memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/006—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation at wafer scale level, i.e. wafer scale integration [WSI]
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/021—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in voltage or current generators
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
Landscapes
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Dram (AREA)
- Tests Of Electronic Circuits (AREA)
Description
102 冗長メモリセルアレイ
110 周辺回路部
111 切り替え信号生成回路
112 モードレジスタ
113 基準電圧生成回路
114 ヒューズ回路
115 疑似調整回路
116 ヒューズ回路
121 DQレシーバ
122 CLKレシーバ
123 ADDレシーバ
124 CMDレシーバ
131 DQラッチ
133 ADDラッチ
134 CMDデコーダ
141 ORゲート
142 ANDゲート
200 半導体ウェハ
201 プローブカード
201a〜201e プローブ
DQ データ入出力端子
CLK クロック端子
ADD アドレス端子
CMD コマンド端子
cont 調整信号
ICLK 内部クロック
TCLKE 切り替え信号
Vref 基準電圧端子
Claims (3)
- クロック信号に同期して少なくともアドレス信号及びコマンドを受け付け可能な半導体記憶装置であって、
メモリセルアレイと、前記メモリセルアレイに対するデータの書き込み及び読み出しを行う周辺回路部と、データ入出力端子と、クロック端子と、前記アドレス信号が入力されるアドレス端子と、前記コマンドが入力されるコマンド端子と、前記クロック端子に入力された前記クロック信号又は前記データ入出力端子に入力された前記クロック信号を前記周辺回路部へ供給可能に切り替える切り替え手段とを備え、
前記周辺回路部は、所定のコマンドと前記アドレス端子から入力されるコードの組み合わせによって切り替え信号を活性化させる切り替え信号生成回路を備え、前記切り替え手段は、前記切り替え信号の活性化に応答して前記データ入出力端子に入力された前記クロック信号を前記周辺回路へ供給可能に切り替えると共に、前記切り替え信号の非活性化時に前記クロック端子に入力された前記クロック信号を前記周辺回路へ供給し、
前記切り替え信号の活性化に応答した前記切り替え手段による切り替えが、前記半導体記憶装置のテスト中に行われ、
前記周辺回路部は、基準電圧を生成する基準電圧生成回路と、前記基準電圧を調整するための調整信号を恒久的に生成する不揮発性記憶回路と、前記調整信号を一時的に生成する疑似調整回路とをさらに備え、
前記疑似調整回路は、前記切り替え信号が活性化した状態で、前記データ入出力端子に入力された前記クロック信号によって、前記アドレス端子から入力され受け付けられたコードに基づいて前記調整信号を一時的に生成することを特徴とする半導体記憶装置。 - 前記切り替え手段は、
前記切り替え信号が一方の入力端子に供給され、前記データ入出力端子に入力された前記クロック信号が他方の入力端子に供給されるANDゲートと、
前記ANDゲートの出力信号が一方の入力端子に供給され、前記クロック端子に入力された前記クロック信号が他方の入力端子に供給されるORゲートとを有し、
前記ORゲートの出力信号を前記クロック信号として、前記周辺回路部が受け付けることを特徴とする請求項1に記載の半導体記憶装置。 - 前記不揮発性記憶回路がヒューズであることを特徴とする請求項1に記載の半導体記憶装置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006141041A JP4591836B2 (ja) | 2006-05-22 | 2006-05-22 | 半導体記憶装置及びそのテスト方法 |
US11/745,051 US7558135B2 (en) | 2006-05-22 | 2007-05-07 | Semiconductor memory device and test method thereof |
US12/233,278 US7859938B2 (en) | 2006-05-22 | 2008-09-18 | Semiconductor memory device and test method thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006141041A JP4591836B2 (ja) | 2006-05-22 | 2006-05-22 | 半導体記憶装置及びそのテスト方法 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008274100A Division JP4934656B2 (ja) | 2008-10-24 | 2008-10-24 | 半導体記憶装置のテスト方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007310989A JP2007310989A (ja) | 2007-11-29 |
JP4591836B2 true JP4591836B2 (ja) | 2010-12-01 |
Family
ID=38711836
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2006141041A Expired - Fee Related JP4591836B2 (ja) | 2006-05-22 | 2006-05-22 | 半導体記憶装置及びそのテスト方法 |
Country Status (2)
Country | Link |
---|---|
US (2) | US7558135B2 (ja) |
JP (1) | JP4591836B2 (ja) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100604888B1 (ko) * | 2004-07-16 | 2006-07-31 | 삼성전자주식회사 | 개선된 테스트 회로를 구비하는 집적회로 장치 및집적회로 장치 테스트 방법 |
US8582374B2 (en) * | 2009-12-15 | 2013-11-12 | Intel Corporation | Method and apparatus for dynamically adjusting voltage reference to optimize an I/O system |
JP5567956B2 (ja) * | 2010-09-16 | 2014-08-06 | 矢崎総業株式会社 | 複数組電池のセル電圧均等化装置 |
JP5592238B2 (ja) * | 2010-11-18 | 2014-09-17 | ピーエスフォー ルクスコ エスエイアールエル | 半導体装置及びその制御方法 |
KR102087759B1 (ko) * | 2013-11-04 | 2020-03-11 | 에스케이하이닉스 주식회사 | 반도체 메모리 장치의 동작방법 및 다수의 반도체 메모리 장치를 포함하는 반도체 메모리 모듈의 동작방법 |
JP6740762B2 (ja) * | 2016-07-13 | 2020-08-19 | 日亜化学工業株式会社 | 発光装置およびその製造方法 |
KR102538991B1 (ko) * | 2016-07-15 | 2023-06-02 | 에스케이하이닉스 주식회사 | 반도체 테스트 장치 및 반도체 테스트 방법 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002313098A (ja) * | 2001-04-12 | 2002-10-25 | Mitsubishi Electric Corp | 半導体装置 |
JP2002319300A (ja) * | 2001-04-23 | 2002-10-31 | Nec Microsystems Ltd | 半導体記憶装置 |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6212089B1 (en) * | 1996-03-19 | 2001-04-03 | Hitachi, Ltd. | Semiconductor memory device and defect remedying method thereof |
JP2639328B2 (ja) * | 1993-11-12 | 1997-08-13 | 日本電気株式会社 | トリミング方法及び回路 |
US5801985A (en) * | 1995-07-28 | 1998-09-01 | Micron Technology, Inc. | Memory system having programmable control parameters |
US6052321A (en) * | 1997-04-16 | 2000-04-18 | Micron Technology, Inc. | Circuit and method for performing test on memory array cells using external sense amplifier reference current |
US6320785B1 (en) * | 1996-07-10 | 2001-11-20 | Hitachi, Ltd. | Nonvolatile semiconductor memory device and data writing method therefor |
KR100261218B1 (ko) * | 1997-12-08 | 2000-07-01 | 윤종용 | 반도체 메모리 장치의 핀 어사인먼트 방법 및 패킷 단위의 신호를 입력으로 하는 반도체 메모리장치 |
JPH11353900A (ja) * | 1998-06-11 | 1999-12-24 | Mitsubishi Electric Corp | 半導体装置 |
JP2003307545A (ja) | 2002-04-15 | 2003-10-31 | Hitachi Ltd | 半導体検査装置、半導体集積回路装置、検査方法および製造方法 |
JP2004046927A (ja) | 2002-07-09 | 2004-02-12 | Elpida Memory Inc | 半導体記憶装置 |
JP4408193B2 (ja) * | 2002-08-08 | 2010-02-03 | 富士通マイクロエレクトロニクス株式会社 | 半導体記憶装置及び半導体記憶装置の試験方法 |
KR100452334B1 (ko) * | 2002-10-30 | 2004-10-12 | 삼성전자주식회사 | 반도체 메모리 장치의 모드진입 제어회로 및 모드진입 방법 |
JP2004198367A (ja) | 2002-12-20 | 2004-07-15 | Fujitsu Ltd | 半導体装置及びその試験方法 |
JP2005108318A (ja) * | 2003-09-30 | 2005-04-21 | Toshiba Corp | 半導体装置および半導体装置のテスト方法 |
DE102004017863B4 (de) * | 2004-04-13 | 2014-09-25 | Qimonda Ag | Schaltung und Verfahren zum Ermitteln eines Referenzpegels für eine solche Schaltung |
-
2006
- 2006-05-22 JP JP2006141041A patent/JP4591836B2/ja not_active Expired - Fee Related
-
2007
- 2007-05-07 US US11/745,051 patent/US7558135B2/en active Active
-
2008
- 2008-09-18 US US12/233,278 patent/US7859938B2/en not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002313098A (ja) * | 2001-04-12 | 2002-10-25 | Mitsubishi Electric Corp | 半導体装置 |
JP2002319300A (ja) * | 2001-04-23 | 2002-10-31 | Nec Microsystems Ltd | 半導体記憶装置 |
Also Published As
Publication number | Publication date |
---|---|
US20070268776A1 (en) | 2007-11-22 |
US7558135B2 (en) | 2009-07-07 |
US7859938B2 (en) | 2010-12-28 |
US20090016121A1 (en) | 2009-01-15 |
JP2007310989A (ja) | 2007-11-29 |
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