WO2013172060A1 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- WO2013172060A1 WO2013172060A1 PCT/JP2013/053218 JP2013053218W WO2013172060A1 WO 2013172060 A1 WO2013172060 A1 WO 2013172060A1 JP 2013053218 W JP2013053218 W JP 2013053218W WO 2013172060 A1 WO2013172060 A1 WO 2013172060A1
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- WIPO (PCT)
- Prior art keywords
- relay
- semiconductor chip
- relay substrate
- chip
- semiconductor
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Definitions
- the present invention relates to a semiconductor device packaged with a semiconductor chip.
- Patent Document 1 is an example of a CSP structure, and a semiconductor chip is packaged by bonding to a relay substrate made of an organic material (resin). A number of through holes are formed in the relay substrate, and solder bumps are provided above and below each through hole so as to be exposed on both upper and lower surfaces of the relay substrate.
- the external connection pads provided on the semiconductor chip are joined to the upper ends of the solder posts on the relay substrate, and the lower ends of the solder posts are joined to the pads on the motherboard by solder balls or the like. According to this, since the size of the packaged semiconductor device is slightly larger than the size of the individual semiconductor chip, it is considered as a packaging of the minimum size.
- the above-described conventional structure has the following problems because it is a three-dimensional structure in which a semiconductor chip is relay-connected to a printed wiring board through a conductive post vertically penetrating the relay board.
- the wiring pitch of the printed wiring board is increasing in density year by year, it is still not sufficient as compared with a semiconductor process in which a semiconductor chip is manufactured by performing microfabrication on a silicon wafer.
- the formation pitch of external connection pads of a general semiconductor chip is 35 to 75 ⁇ m
- the formation pitch of pads of a printed wiring board is 400 to 800 ⁇ m.
- the formation pitch of pads on both the semiconductor chip and the printed wiring board must be the same.
- the formation pitch of the external connection pads in the semiconductor chip is restricted by the pad formation pitch on the printed wiring board side.
- the pad formation pitch on the printed wiring board side is set to the formation pitch of the external connection pads on the semiconductor chip side. Therefore, the latest fine semiconductor chip cannot be used. That is, the pad formation pitch on the printed wiring board side is a bottleneck.
- a semiconductor chip with a wide line width that conforms to the wiring rules on the printed wiring board side must be used, or a special semiconductor chip with a wide line width only for the external connection pads must be designed. This means that the chip area becomes large even if the number of gates is the same, and there is a problem that the semiconductor chip becomes expensive.
- the semiconductor chip when the semiconductor device is used, the semiconductor chip generates a large amount of heat and rises in temperature.
- the difference in linear thermal expansion coefficient between the silicon substrate constituting the semiconductor chip and the resin-made relay substrate is large.
- a large thermal stress is generated in the solder joint portion and the reliability of the joint is low.
- the thermal resistance of the resin-made relay substrate is larger than that of the silicon substrate, the heat generated in the semiconductor chip does not easily flow to the relay substrate side. It tends to increase the stress further.
- the relay substrate has a three-dimensional structure in which solder posts are embedded in the through holes, it is manufactured through various processes such as formation of through holes, internal plating of the through holes, filling of solder paste, and reflow processing. It must be done and the manufacturing cost is high.
- an object of the present invention is to use a general-purpose semiconductor chip that is miniaturized without being restricted as much as possible by the wiring rule on the printed wiring board side, and has high reliability of an electrical junction and can be manufactured at low cost. It is to provide a semiconductor device.
- a semiconductor device disclosed in this specification is a semiconductor device mounted on a printed wiring board, and includes a predetermined semiconductor integrated circuit and an external connection pad for connecting the semiconductor integrated circuit to an external circuit.
- a relay substrate made of silicon or glass, a chip side pad group formed on one surface of the relay substrate and connected to the external connection pad of the semiconductor chip, and the relay substrate connected to the chip side pad group
- a relay circuit group extending and extending on the outer peripheral side of the circuit board, and a surface circuit pattern comprising a relay pad group connected to the end of each relay wiring opposite to the chip side pad, and a plurality of conductive paths on the surface of the relay substrate.
- the relay substrate is formed to extend in a direction intersecting with each other, and the conductive paths are insulated from each other by an insulating resin. It is connected to the end the relay pads, and the relay substrate of said conductive path is a semiconductor device that includes a post array which opposite end is connected to the printed circuit board side.
- the external connection pads of the semiconductor chip are connected to the printed wiring board via the surface circuit pattern and the post array formed on the surface of the relay board.
- the surface circuit pattern is a form in which the relay wiring group connected to the chip-side pad group connected to the external connection pad of the semiconductor chip extends to the outer peripheral side of the relay substrate and extends to the relay pad group.
- the pitch between lines becomes wider on the outer peripheral side, that is, on the relay pad group side.
- the formation pitch between the chip-side pads on the inner peripheral side can be set to be narrower than the formation pitch between the relay pads.
- a general fine pitch semiconductor chip can be used without being restricted by the wiring pitch of the printed wiring board.
- the surface circuit pattern of the relay substrate is a planar circuit that does not require the use of a through hole
- the material of the relay substrate is an insulator having flatness mainly composed of SiO2 such as silicon or glass, so that semiconductor manufacturing is possible.
- a fine surface circuit pattern can be formed with high accuracy by a general thin film forming method and metal micromachining method used in the process, and the manufacturing cost is low.
- the semiconductor chip as the heat source is mounted on the back side of the relay board with the circuit side up, and the back side of the semiconductor chip is always near the printed board, so the heat generated in the semiconductor chip is relay board Then, heat is dissipated through the printed circuit board, and the temperature rise of the semiconductor chip can be suppressed.
- a heat conductive material such as silicon rubber having a low thermal resistance is inserted into the gap between the semiconductor chip and the printed circuit board, the heat of the semiconductor chip is transferred to the printed circuit board having a large area, and further through the housing of the device. Heat dissipation is also possible.
- Such a heat dissipation structure is the most efficient and inexpensive structure for small and thin housings such as portable information devices that cannot use fan cooling, etc., and a planar circuit configuration using a relay board that does not use through holes This is a unique advantage of the package structure consisting of
- the relay substrate and the semiconductor chip have approximately the same linear thermal expansion coefficient, even if a large temperature difference occurs between the semiconductor chip and the relay substrate, the electrical connection between the semiconductor chip and the relay substrate is possible.
- the thermal stress acting on the part is much less than that of the conventional structure in which the relay substrate is made of resin. Thereby, the reliability of joining can be improved.
- a bypass capacitor for the power supply system of the semiconductor chip or a clamp diode for the I / O terminal is formed on the surface of the relay substrate. Since these passive elements are indispensable for the operation of the semiconductor chip, the conventional structure uses a resin substrate for the relay substrate, so a small discrete component is used for the relay substrate or printed wiring board. In the present invention, since the relay substrate is made of silicon or glass, the bypass capacitor or the clamp diode can be formed on the surface by a general microfabrication process. As a result, the semiconductor device according to the present invention can be handled as a highly functional semiconductor component in which passive elements necessary for the semiconductor chip are packaged.
- the occupied area is large, so the chip size of the semiconductor chip increases and the unit price per unit becomes extremely high.
- an integrated circuit with a high density transistor group can be formed on the semiconductor chip to lower the unit price of the chip, and the relay board is made of ceramics, and the area occupied by the relay chip is large. Since the passive elements are formed on the relay substrate having a sufficient area, the arrangement is extremely rational and efficient. Further, when it is necessary to change the characteristics of the bypass capacitor or the clamp diode, it is only necessary to change the relay substrate, so that it is possible to flexibly cope with the specification change.
- VDDQ, VSSQ power supply terminals for I / O terminals are connected to the internal logic on both sides of the I / O terminal. Separately from the power supply terminals (VDD, VSS) for the circuit.
- VDD, VSS power supply terminals
- a bypass capacitor near the power supply line of the output transistor formed in the semiconductor chip to quickly charge the semiconductor chip. It is desirable to supply.
- a discrete component serving as a bypass capacitor is mounted on the surface or inside of the printed wiring board and connected to each of the power supply terminals by a circuit pattern of the printed wiring board.
- a bypass capacitor composed of a lower surface electrode, a dielectric, and an upper surface electrode is formed on the surface of the relay substrate, and the surface electrode is used for an I / O power source for a semiconductor chip. Since the external connection pad is connected, the bypass capacitor is located in a region overlapping the semiconductor chip, and the power supply terminal and the bypass capacitor are connected with a minimum distance. For this reason, the responsiveness of the semiconductor chip can be improved by minimizing the inductance component of the wiring and making maximum use of the capacitance of the bypass capacitor.
- the post array is manufactured as a separate component from the semiconductor chip and the relay substrate, and this is joined to the relay substrate, so that the throughput of the relay substrate is not affected at all and the productivity of the entire semiconductor device is increased. Can be maintained.
- it is manufactured separately from the semiconductor chip, it is possible to standardize its specifications and make it a general-purpose component that can be applied to various semiconductor chips, eliminating the need for dedicated designs tailored to various semiconductor chips. And reliability test costs can be significantly reduced.
- the component since the component has a simple structure that is simply reflow-connected to the external connection pad of the semiconductor chip, the packaging cost of the semiconductor chip can be drastically reduced.
- the degree of freedom in deformation of each post array is increased. Since it increases, it is more preferable from the viewpoint of relaxation of thermal stress.
- a plurality of metal wires are aligned in the axial direction, and the metal wires are cut in a state in which the distance between the metal wires is maintained by an insulating resin. It is preferable to use what was manufactured by doing.
- the plating method can be used even if the post array is made thick (the metal wires are long).
- this post array can be set to a desired thickness dimension (corresponding to the thickness dimension of the insulating resin or the length dimension of the metal wire) by adjusting the cutting interval.
- the thickness of the insulating resin is set to a dimension suitable for alleviating thermal stress that tends to occur due to the difference in coefficient of linear thermal expansion between the relay board and the printed wiring board. Can be further improved in reliability.
- the circuit pattern can be developed by the relay substrate, it can be directly connected to the narrow pitch electrode of the semiconductor chip without being restricted by the wide pitch wiring on the printed wiring board side, and from the back surface of the semiconductor chip. Since direct heat dissipation to the printed wiring board side can also be expected, the thermal stress is reduced, the reliability of the electrical joint is high, and it can be manufactured at low cost.
- FIG. 1 is a cross-sectional view of the semiconductor device of the embodiment mounted on a circuit board.
- FIG. 2 is a bottom view of the semiconductor device of the embodiment.
- FIG. 3 is a plan view showing a pad arrangement example of the semiconductor chip.
- FIG. 4 is a simplified circuit diagram equivalently showing the circuit pattern of the relay board and the passive element group.
- FIG. 5 is an enlarged cross-sectional view showing the structure of the bypass capacitor.
- FIG. 6A is a plan view showing a manufacturing process of the bypass capacitor.
- FIG. 6B is a plan view showing the manufacturing process of the bypass capacitor.
- FIG. 6C is a plan view showing a manufacturing process of the bypass capacitor.
- FIG. 7 is an enlarged sectional view of the post array.
- FIG. 1 is a cross-sectional view of the semiconductor device of the embodiment mounted on a circuit board.
- FIG. 2 is a bottom view of the semiconductor device of the embodiment.
- FIG. 3 is a plan view showing a pad arrangement example of
- FIG. 8 is a plan view showing a state in which a large number of semiconductor devices of the present embodiment are manufactured from a silicon wafer.
- FIG. 9 is a cross-sectional view showing the manufacturing process of the post array.
- FIG. 10 is an enlarged sectional view showing a modification of the post array.
- FIG. 11 is an exploded cross-sectional view showing another embodiment of a multi-stage relay board.
- FIG. 12 is a cross-sectional view showing another embodiment of a multi-stage semiconductor device.
- FIG. 13 is an enlarged cross-sectional view showing a different structure of the bypass capacitor.
- FIG. 1 is a schematic cross-sectional view including a semiconductor device 1 according to the first embodiment.
- this semiconductor device 1 one semiconductor chip 20 and a plurality of post arrays 30 are bonded to one (lower) surface of the relay substrate 10 by a reflow solder 40 and packaged. It is mounted on a known printed wiring board 50 containing an organic material (resin) made of glass epoxy or the like.
- the semiconductor chip 20 has a well-known configuration in which a predetermined semiconductor integrated circuit (not shown) is formed of a large number of semiconductor elements on one surface (upper surface in FIG. 1) of a silicon substrate.
- the semiconductor chip 20 is a rectangular plate having a side of 5 mm. Shape.
- external connection pads 21 (see FIG. 3) such as a power supply terminal and an input / output terminal for connecting the semiconductor integrated circuit to an external circuit through an opening provided in the passivation film are formed.
- These external connection pads 21 are arranged in a square frame-like region along the outer peripheral edge of the semiconductor chip 20 and arranged alternately at a pitch of, for example, 70 ⁇ m in the arrangement shown in FIG. It is a pad.
- FIG. 3 shows a specific arrangement example of the external connection pad 21 group.
- an LSI having a 64-bit I / O terminal is illustrated.
- 2 on two opposing sides of a square frame-like region located on the left and right in FIG. 3 and the right side is omitted).
- a pair of power supply terminals VDDQ and VSSQ for I / O terminals are alternately arranged so as to sandwich one I / O terminal.
- On the other two sides are a control signal terminal CTRL # (# represents an arbitrary natural number), a data input terminal DIN #, and power supply terminals VDD # and VSS # for internal logic circuits.
- a clock signal terminal CLK and the like are arranged.
- the relay substrate 10 is manufactured by dividing and cutting a silicon wafer or a glass substrate, and has, for example, a rectangular plate shape with a side of 7 mm.
- a surface circuit pattern and various passive elements are formed on one surface of the surface by a well-known wiring formation technique.
- the surface circuit pattern will be described in detail as follows.
- FIG. 4 the surface circuit pattern 11 of the relay substrate 10 and various passive element groups formed therewith are depicted in an equivalent circuit.
- the actual number of pads is very large (actually as shown in FIG. 2). 128 on one side), which is simplified to the number of four pads on one side.
- a rectangular frame region corresponding to the group of external connection pads 21 of the semiconductor chip 20 is formed with the same number, size, and formation pitch as the group of external connection pads 21.
- a group of chip-side pads 12 is formed.
- the same number of relay pad groups 13 as the external connection pad 21 groups are formed outside the chip-side pad 12 group and in a rectangular frame region along the outer peripheral edge of the relay substrate 10.
- the number of relay pads 13 is the same as the number of chip-side pads 12, but the chip-side pad 12 group is located on the inner peripheral side of the relay substrate 10, while the relay pad 13 group is located in the rectangular frame region on the outer peripheral side.
- a larger area than the inner peripheral side can be used, and therefore the formation pitch between the relay pads 13 is wider than the formation pitch of the chip-side pads 12 (for example, a pad having a diameter of 125 ⁇ m has a pitch of 250 ⁇ m). Is formed). Between each chip-side pad 12 and each corresponding relay pad 13, a relay wiring 14 is formed extending from the chip-side pad 12 group to the outer peripheral side of the relay substrate 10.
- the surface circuit pattern 11 as described above is formed on the relay substrate 10, and various passive elements are formed by a thin film forming process and a metal microfabrication process as in the schematic equivalent circuit shown in FIG. 4, for example. Is formed.
- a damper resistor 16 for impedance matching is provided between the chip-side pad 12 connected to the I / O terminals I / O 0 to I / O 3 of the semiconductor chip 20 and the corresponding relay pad 13.
- a clamp diode 15 is provided between the relay wiring 14 connected to the / O terminals I / O 0 to I / O 3 and the relay wiring 14 connected to the power supply terminals VDDQ and VSSQ for the I / O terminals. Yes.
- a pull-up resistor 17 is provided between the relay wiring 14 connected to the I / O terminals I / O 0 to I / O 3 and the relay wiring 14 connected to the power supply terminal VDDQ for the I / O terminal. (Or a pull-down resistor) is provided.
- the damper resistor 16 is desirably a relatively low resistance (10 to 50 ⁇ ) obtained by polysilicon wiring resistance or metal resistance.
- the clamp diode 15 is an ESD protection circuit for overvoltage clamping, requires a relatively high breakdown voltage and a high-speed response, and uses a PN junction that runs parallel to a relatively long metal wiring (100 to 500 ⁇ m), or 2 It is desirable to realize a high-speed clamp by configuring a Schottky barrier diode composed of various kinds of metals and a SiO2 layer.
- As the pull-up resistor 17 (or the pull-up resistor) a resistance value in the vicinity of 4.7 K ⁇ or higher is usually used.
- This type of resistance can be achieved by using a diffusion resistor obtained by diffusing P + and forming an N-well using P-Substrate as the relay substrate 10 and a metal having a high specific resistance (for example, Ni, Cr, etc.) High resistance can be obtained with a small amount of resources by using a metal plating or the like using a metal.
- a plurality of chip-side pads 12 connected to the power supply terminals VDDQ and VSSQ for the I / O terminals are overlapped with the mounting region of the semiconductor chip 20, that is, positioned directly above the semiconductor chip 20.
- the bypass capacitor 18 is provided. Although only four bypass capacitors 18 are schematically shown in FIG. 4, in actuality, for each power supply terminal pair for I / O terminals (64-bit I / O, 32 power supply terminal pairs are provided). When there are pairs, 32 bypass capacitors 18 are formed, or when there are a plurality of pairs of power supply terminals, a plurality of bypass capacitors 18 (multiple times 32 ⁇ n).
- Each bypass capacitor 18 has the structure shown in FIG. 5 and is manufactured as follows. That is, the first surface electrode 18A is formed on the surface (lower surface) of the relay substrate 10 by, for example, a metal sputtering method or a plating method. This is connected to one of the paired power terminals. Further, as shown in FIG. 6A, simultaneously with the first surface electrode 18A, the lead wire portion 18B of the first surface electrode 18A and the signal wiring 18C for the I / O terminal can be formed of the same metal in the same process. This is desirable in terms of process simplification.
- a dielectric layer 18D made of a metal oxide film such as ITO or STO is placed over all the first surface electrodes 18A so as to be common to each bypass capacitor 18. It is formed as a single dielectric layer. This may be formed individually on each first surface electrode 18A.
- the dielectric layer 18D is formed by aerosolizing a solution in which a metal oxide as a raw material of the dielectric layer is dissolved by ultrasonic vibration. By an aerosol deposition method in which the silicon substrate or glass substrate is heated to several hundred degrees in the air, for example, to form a metal oxide thin film while being heated together with the carrier gas. It is desirable to form.
- the second surface electrode 18E is formed by a sputtering method or a plating method in the same manner as the first surface electrode 18A so as to cover the dielectric layer 18D.
- Each of the second surface electrodes 18E is a rectangular electrode having the same shape and the same size as the first surface electrode 18A, as in the case of the first surface electrode 18A, but on the opposite side to the signal wiring 18C.
- the lead wire portion 18F is integrally formed so as to be positioned (see FIG. 6C).
- the bypass capacitor 18 in which the first surface electrode 18A, the dielectric layer 18D, and the second surface electrode 18E are laminated in this order on the relay substrate 10 is connected to each power supply terminal for I / O terminals. This is formed for each pair of VDDQ and VSSQ.
- each of the lead lines 18D and 18F is integrally formed on 18E, and these also serve as lands for connecting the semiconductor chip 20 to the relay substrate 10, and therefore, among the external connection pads 21 of the semiconductor chip 20 , I / O terminals I / O #, I / O # + 1 and power supply terminals VDDQ and VSSQ pairs for them are the signal wiring 18C, the lead line portion 18B of the first surface electrode 18A and the lead line of the second surface electrode 18E.
- the part 18F is connected by reflow soldering.
- the post array 30 is formed by disposing a plurality of metal wires 34 as conductive paths in an insulating resin 32.
- the insulating resin 32 is positioned around each metal wire 34 so that each metal wire 34 is insulated from each other, so that the mutual spacing (arrangement pitch) is maintained substantially constant. Is flush with both end faces of the insulating resin 32.
- the insulating resin 32 its linear thermal expansion coefficient is smaller than the linear thermal expansion coefficient (about 15 ppm) of the printed wiring board 50 and larger than the linear thermal expansion coefficient (about 4 ppm) of the silicon substrate constituting the semiconductor chip 20.
- a synthetic resin has been selected.
- the insulating resin 32 is flexible enough to allow bending deformation of the metal wire 34.
- first pads 36 are formed on the upper surface 32 ⁇ / b> A connected to the relay substrate 10 by, for example, gold flash plating so as to overlap the end surface of the metal wire 34.
- a second pad 38 is provided on the lower surface 32 ⁇ / b> B to be connected to the end surface of the metal wire 34.
- a plurality of the first pads 36 and the second pads 38 are formed at a predetermined pitch on both the front and back surfaces of the insulating resin 32 so as to correspond to the metal wires 34 on a one-to-one basis.
- solder bumps 40 are formed on the surfaces of the first pad 36 and the second pad 38 by attaching and melting solder balls later.
- the post array 30 having the above-described structure is attached to the lower surface of the relay substrate 10 by dividing it into, for example, a total of four post arrays 30A to 30D corresponding to each side of the rectangle.
- These post arrays 30A to 30D are formed as a collective post array by a manufacturing method to be described later and then cut into individual pieces by cutting.
- each of the post arrays 30A to 30D and the semiconductor chip 20 on the relay substrate 10 is performed at the wafer level. That is, after a wiring pattern and a passive element group corresponding to each required number of relay substrates 10 are manufactured on a silicon wafer 60 for forming the relay substrate 10 by a thin film forming process and a metal micromachining process. Before the silicon wafer 60 is divided and cut into individual pieces by dicing, the post arrays 30A to 30D are arranged at predetermined positions on the silicon wafer 60 together with the semiconductor chip 20, as shown in FIG. Connected.
- the substrate 10 that is, a large number of completed semiconductor devices 1 are manufactured at a time. Also in FIG. 8, since the number of semiconductor chips 20 is actually very large, it is simply shown as twelve.
- the post array 30 is manufactured by an insulating resin 32 and a metal wire 34.
- the insulating resin 32 includes an interlayer spacer 32A that partitions the metal wire 34 in the vertical direction of FIG. 9 and an inter-column spacer 32B that partitions the metal wire 34 in the left-right direction, and is a well-known type that is solidified by heat or ultraviolet rays. Can be used.
- the interlayer spacer 32A formed of this type of resin has a sticky surface and is, for example, a flat single sheet having a thickness of about 400 ⁇ m.
- the inter-column spacer 32B has, for example, a rectangular column shape with a thickness of 400 ⁇ m and a width of 400 ⁇ m. It should be noted that a single resin sheet in which a large number of parallel slits are formed may be used instead of the large number of inter-row spacers 32B.
- the metal wire 34 has a cylindrical shape with a diameter of 400 ⁇ m, for example, and is made of copper, a copper alloy, or a low resistance metal such as aluminum.
- FIG. 8 illustrates a state in which the axial direction of the metal wire 34 is oriented in the direction perpendicular to the paper surface.
- the unit structure sheet 35 is obtained by forming a layer having a thickness of 125 ⁇ m on one surface of the interlayer spacer 32A by the metal wire 34 and the inter-column spacer 32B.
- a plurality of unit structure sheets 35 are laminated in the thickness direction of the interlayer spacer 32A to form a laminated structure, and are compressed slightly from the thickness direction and the width direction to eliminate gaps. Heat is applied or ultraviolet rays are applied to solidify the interlayer spacer 41 and the inter-column spacer 42 (this does not mean that flexibility is completely lost).
- a large number of metal wires 34 are fixed by the interlayer spacers 32A and the inter-column spacers 32B so as to be spaced apart from each other so that the metal wires 34 are embedded in the insulating resin. It will be like a state.
- each metal wire 34 having a diameter of 125 ⁇ m is arranged at a pitch of 250 ⁇ m vertically and horizontally with respect to a plane orthogonal to the axial direction.
- the solidified laminated structure is sliced into a plurality of sheets at a desired interval of, for example, 200 ⁇ m to 500 ⁇ m along the surface crossing the metal wire 34.
- the insulating resin and the metal wire 34 are cut to have the insulating resin 32 having a thickness corresponding to the cutting interval, and the metal wire having a length corresponding to the cutting interval in the resin layer.
- a collective post array (not shown) in which 34 is embedded is formed.
- pads are formed on both ends of the metal wire 34 by gold flash plating on both surfaces of the collective post array, and a resist film having openings at positions corresponding to the pads is formed by printing or photolithography.
- solder balls are placed in the openings and heat-treated, whereby a sheet-like collective post array having a large number of solder bumps attached to the surface can be obtained.
- the post arrays 30A to 30D described above can be formed by cutting them into pieces each having the required number of metal wires 34.
- the post arrays 30A to 30D are all standardized into small pieces so as to have a total of 128 metal wires 34 in 4 rows and 32 stages as shown in FIG. 2, for example, and a plurality of pieces (FIG. 2). 4 pieces) are bonded to each semiconductor chip 20.
- the post arrays 30A to 30D are arranged such that the arrangement directions of adjacent ones are alternately arranged vertically and horizontally, and are arranged with a gap therebetween.
- each post array 30A to 30D is placed so as to be in contact with each electrode terminal 14 of the semiconductor chip 20, for example, and is joined by reflow soldering in that state, each post array 30A to 30D is caused by the surface tension of the solder melted during reflow.
- the post arrays 30A to 30D are lifted with respect to the semiconductor chip 20 and naturally move to the optimum bonding position, so-called self-alignment becomes possible.
- the semiconductor device 1 of the present embodiment has a structure in which the semiconductor chip 20 and the post array 30 are integrated with the relay substrate 10, and can handle this as a single packaged independent component.
- the semiconductor chip 20 is connected to the printed wiring board 50 through the surface circuit pattern 11 and the post array 30 formed on the surface of the relay board 10.
- the surface circuit pattern 11 extends from the semiconductor chip 20 located at the center of the relay substrate 10 radially to the outer peripheral side and extends to the group of relay pads 13, the chip located at the center side of the relay substrate 10.
- the formation pitch of the side pad 12 group is narrower than the formation pitch of the relay pad 13 group located on the outer peripheral side. Therefore, even if the formation pitch of the relay pad 13 group on the outer peripheral side is relatively wide due to the restriction of the wiring pitch of the printed wiring board 50, the formation pitch between the chip side pads 12 on the inner peripheral side is sufficient. Since it can be set to a narrow interval, a general fine pitch semiconductor chip 20 can be used.
- the surface circuit pattern 11 of the relay substrate 10 is a planar circuit that does not require the use of through holes, and the material of the relay substrate 10 is silicon or glass. It can be formed with high accuracy, and the manufacturing cost can be reduced.
- the relay substrate 10 is formed using a silicon or glass substrate that is a material of the semiconductor chip 20.
- the semiconductor chip is mounted on the back surface of the relay substrate with the circuit surface up and the back surface down. Since the entire back surface of the semiconductor chip always faces the vicinity of the printed circuit board, it can have a large-area contact with the printed circuit board 50 via the printed circuit board 50 and silicon rubber on the silicon flat surface of the semiconductor chip.
- the semiconductor chip 20 is excellent in heat dissipation and has a structural advantage that the temperature rise of the semiconductor chip 20 is small.
- the relay substrate 10 and the semiconductor chip 20 have substantially the same linear thermal expansion coefficient, even if a temperature difference occurs between the semiconductor chip 20 and the relay substrate 10, the semiconductor chip 20 and the relay substrate 10 Since the thermal stress acting on the solder joint is significantly less than that of the conventional structure in which the relay board is made of resin, the reliability of electrical joining is high. On the other hand, the difference in coefficient of linear thermal expansion between the relay board 10 made of silicon or glass and the printed wiring board 50 that is generally made of resin is relatively large.
- the post array 30 is formed by extending a plurality of metal wires 34 in a direction perpendicular to the surface of the relay substrate 10, and Since the metal wires 34 are insulated from each other by the insulating resin 32, thermal stress is absorbed by the group of the metal wires 34 being bent along the surface direction of the relay substrate 10 together with the insulating resin 32. Is done. Therefore, the reliability of the solder joint portion can be further increased.
- the surface circuit pattern 11 is formed on the relay substrate 10 by using the relay substrate 10 as a passive element, a silicon substrate and a glass substrate capable of fine wiring by a thin film forming process and a metal micromachining process.
- passive elements such as a clamp diode 15 and a resistor 17 necessary for stable operation of the semiconductor chip 20 are formed on the relay substrate 10.
- the semiconductor device 1 of the present embodiment can be handled as one component in which the passive element group essential for the operation together with the semiconductor chip 20 is packaged, and as a result, the printed circuit board 50 side.
- the circuit configuration can be simplified.
- the area occupied by the passive elements is large, so that the chip size increases and the cost per chip increases.
- the occupation area is reduced by specializing in a highly integrated circuit including a transistor group as an active element, and as a result, an inexpensive semiconductor chip 20 can be used.
- the characteristics of the passive element group need to be changed due to the convenience of the circuit on the printed wiring board 50 side, only the relay board 10 needs to be changed, so that it is possible to flexibly cope with the specification change.
- I / O terminal power supply terminals VDDQ, VSSQ
- VDD, VSS power supply terminals
- the surface of the relay substrate 10 is formed using the fact that the relay substrate 10 is formed of a silicon substrate and a glass substrate that can be handled by a thin film forming process and a metal micromachining process.
- a bypass capacitor 18 including a lower surface electrode 18A, a dielectric layer 18D, and an upper surface electrode 18E is formed in a region overlapping with the semiconductor chip 20, and the I / O for the semiconductor chip 20 is formed on the surface electrodes 18A and 18E. Since the external connection pads 21 for the power supplies (VDDQ, VSSQ) are connected, the power supply terminals (VDDQ, VSSQ) and the bypass capacitor 18 are connected with a minimum distance. For this reason, it is possible to improve the responsiveness of the semiconductor chip 20 by minimizing the inductance component of the wiring and maximizing the capacity of the bypass capacitor 18.
- the post array 30 of the present embodiment a plurality of metal wires 34 are aligned in the axial direction, and the metal wires 34 are in a state in which the distance between them is held by the insulating resin 32. What was manufactured by cutting across 34 is used.
- the post array 30 is manufactured as a separate component from the semiconductor chip 20 and the relay substrate 10 and used in combination with the relay substrate 10. The post array 30 does not affect the manufacturing throughput of the relay substrate 10 at all, and the entire semiconductor device 1. High productivity can be maintained.
- it is manufactured separately from the semiconductor chip 20 it is possible to standardize the specifications and to make a general-purpose component that can be applied to various semiconductor chips 20, and a dedicated design tailored to the various semiconductor chips 20 becomes unnecessary. Development costs and reliability testing costs can be significantly reduced.
- the component since the component has a simple structure that is simply reflow-connected to the external connection pad of the semiconductor chip 20, the packaging cost of the semiconductor chip 20 can be drastically reduced.
- the post array 30 is thick (the metal wires 34 are long). Even if manufactured, the longer the conductive path as in the case where the conductive path is formed by plating, the longer the manufacturing time is, and the post array 30 solidified with resin is easy to handle, Productivity is high.
- the post array 30 can be set to a desired thickness dimension (corresponding to the thickness dimension of the insulating resin 32 or the length dimension of the metal wire 34) by adjusting the cutting interval. For this reason, by setting the thickness of the insulating resin 32 to a dimension suitable for alleviating the thermal stress that tends to occur due to the difference in linear thermal expansion coefficient between the relay substrate 10 and the printed wiring board 50. The reliability of the solder joint can be further increased. Further, in the present embodiment, since a plurality (four) of the post arrays 30 are joined to the single relay substrate 10 at intervals, the degree of freedom of deformation of each post array 30 is high. This is more convenient in terms of thermal stress relaxation. ⁇ Other embodiments>
- the post array 30 has a form in which the metal wires 34 are embedded in the insulating resin 32.
- the present invention is not limited to this, and the state is mutually insulated by the insulating resin.
- the conductive path is not limited to a metal wire, and may be a metal foil. Even when a metal wire is used, it is not limited to copper and copper alloy, but may be a low-resistance metal material such as aluminum, or a multi-core wire.
- the metal wire 34 is not limited to being divided and arranged by the unit structure sheet 35 or the interlayer spacer 32A as in the above-described embodiment.
- a plurality of electric wires coated with metal wires with resin may be assembled to solidify the heat-fusible resin, and then sliced so as to cross the metal wires.
- one first pad 36 and one second pad 38 are associated with one metal line 34 of the post array 30, but the present invention is not limited to this.
- a plurality of metal wires 34 having a diameter smaller than their diameter may correspond to each of the first pad 36 and the second pad 38.
- at least one metal wire 34 is formed. Will contact both pads 36,38. Therefore, the formation accuracy of each pad 35 and 36 may be low, and productivity can be improved also from this aspect.
- the post array 30 is described as an example in which the semiconductor chip 20 and the printed wiring board 50 made of glass epoxy are connected.
- the circuit board is not necessarily made of an organic material such as glass epoxy.
- the substrate may not be a circuit substrate, but may be a silicon substrate, a glass substrate, or another inorganic-based circuit substrate such as a semiconductor.
- the substrate material of the relay substrate 10 may be made of glass such as borosilicate glass, quartz glass, or soda glass, as long as thin film forming processing and metal fine processing can be performed.
- the present invention is not limited thereto, and a plurality of semiconductor chips 20 are mounted on one relay substrate 10.
- the semiconductor device 1 in which the semiconductor chip 20 and the post array 30 are mounted on the relay substrate 10 is further connected to the auxiliary relay substrate 200 made of silicon or glass via the post array 30.
- a multi-stage configuration of a relay board connected to a printed wiring board (not shown) via a post array 300 attached to the auxiliary relay board 100 can also be adopted. In this way, the peripheral circuit can be formed on the relay substrate 100 by a thin film forming process and a metal micromachining process to further increase the number of functions.
- a plurality of relay boards 10 and 100 are stacked in multiple stages via post arrays 30 and 300 to further increase the functionality as a multi-chip semiconductor package configured three-dimensionally. You can also. In this case, since it is necessary to form through-holes for electrical connection in the upper and lower stages on relay boards other than the uppermost stage, it is preferable that those relay boards are made of glass.
- the first capacitor 18 ⁇ / b> A connected to one of the power supply terminals VDDQ and VSSQ is formed on the surface of the relay substrate 10 and the second capacitor 18 is connected to the other.
- the two-surface electrode 18 is stacked on the first surface electrode 18A via the dielectric layer 18D, the present invention is not limited to this, and the bypass capacitor 65 may be configured with the structure shown in FIG. In this structure, first, the intermediate electrode 61 is formed on the surface (preferably the entire surface) of the relay substrate 10.
- the intermediate electrode 61 may be formed as a metal surface electrode by a sputtering method or a plating method, and when the material of the relay substrate 10 is silicon, the specific resistance is low (several tens of ⁇ or less) P-type or N-type diffusion. A layer may be formed instead of the metal electrode. Then, the dielectric layer 62 is formed on the surface (preferably the entire surface) of the intermediate electrode 61 in the same manner as in the above embodiment. If the intermediate electrode 61 and the dielectric layer 62 are formed on the entire surface in this way, a photolithography process for masking or etching becomes unnecessary. Further, the first surface electrode 63 and the second surface electrode 64 may be further formed by masking or etching techniques, and these may be connected to the power supply terminals VDDQ and VSSQ by the solder 40.
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Abstract
Description
特許文献1の半導体装置はCSP構造の一例であり、半導体チップを有機材料(樹脂)製の中継基板に接合してパッケージ化してある。中継基板には多数の貫通孔が形成され、各貫通孔の上下に半田バンプが中継基板の上下両面に露出するように設けられている。半導体チップに設けられている外部接続パッドは中継基板の半田ポストの上端に接合され、その半田ポストの下端がマザーボードのパッドに半田ボール等によって接合される。これによると、パッケージ化された半導体装置のサイズは、半導体チップの個片よりも僅かに大きい程度となるから、最小サイズのパッケージングであるかのように考えられている。
ところが、半導体チップとプリント配線基板とを上下貫通型の導電ポストを有する中継基板によって接続する従来構造では半導体チップ及びプリント配線基板の両者のパッドの形成ピッチを同一にしなくてはならない。このため、半導体チップにおける外部接続パッドの形成ピッチはプリント配線基板側のパッド形成ピッチの制約を受ける。すなわち、従来構造の半導体パッケージでは、十分に微細化された配線ルールによって形成された汎用の半導体チップを使用しようとしても、プリント配線基板側のパッド形成ピッチを半導体チップ側の外部接続パッドの形成ピッチに合致させることができないため、最新の微細な半導体チップを使用できない。すなわち、プリント配線基板側のパッド形成ピッチがボトルネックとなっているのである。このことは、プリント配線基板側の配線ルールに合致する広い線幅の半導体チップを使用しなくてはならない、または外部接続パッド群だけを広い線幅にした特別な半導体チップを設計しなくてはならないことを意味するから、同一ゲート数でもチップ面積が広くなるため、半導体チップが高価になるという問題があった。
1.半導体装置の構成
図1は、本実施形態1の半導体装置1を含んだ概略的な断面図である。この半導体装置1は、中継基板10の一方(下方)の面に1個の半導体チップ20及び複数個のポストアレイ30をリフロー半田40によって接合してパッケージ化したもので、ポストアレイ30を介してガラスエポキシ製等の有機材料(樹脂)を含む周知のプリント配線基板50に実装されている。
この誘電体層18Dは、例えば本出願人の出願に係る特開2008-141121号公報に記載されているように、誘電体層の原料となる金属酸化物を溶解した溶液を超音波振動によってエアロゾル化してキャリアガスと共に加熱しつつシリコン基板上或いはガラス基板上に供給し、シリコン基板或いはガラス基板を例えば大気中で数百度に加熱することで金属酸化物の薄膜として成膜させるエアロゾルデポジション法によって形成することが望ましい。
この製法例ではポストアレイ30を、絶縁性樹脂32と金属線34とによって製造する。絶縁性樹脂32は、図9の上下方向において金属線34を区画する層間スペーサ32Aと、左右方向において金属線34を区画する列間スペーサ32Bとからなり、熱又は紫外線により固化する周知タイプのものが使用可能である。
3.本実施形態の効果
一方、シリコン製或いはガラス製の中継基板10と、一般に樹脂製であるプリント配線基板50との間では線熱膨張率の相違が比較的大きい。しかし、本実施形態ではこれらの間はポストアレイ30によって接続することとしており、そのポストアレイ30は複数本の金属線34が中継基板10の表面に対して直交する方向に延びて形成され、かつ各金属線34が絶縁性樹脂32によって相互に絶縁された状態とされているから、金属線34群が絶縁性樹脂32と共に中継基板10の面方向に沿うように撓むことによって熱応力が吸収される。したがって、一層、半田接合部分の信頼性を高く維持することができる。
<他の実施形態>
(1)上記実施形態では、ポストアレイ30として金属線34を絶縁性樹脂32内に埋め込んだ形態のものを使用したが、本発明はこれに限らず、絶縁性樹脂によって相互に絶縁された状態となっている複数の導電路を有するものであればよく、その導電路としては金属線に限らず、金属箔であってもよい。また、金属線を使用する場合でも、銅、銅合金に限らず、アルミニウム等の低抵抗の金属材料であってもよく、多芯線を使用しても良い。
Claims (5)
- プリント配線基板に実装される半導体装置であって、
所定の半導体集積回路及びその半導体集積回路を外部回路に接続するための外部接続パッドを備えた半導体チップと、
シリコン或いはガラス製の中継基板と、
この中継基板の一方の表面に形成され、前記半導体チップの前記外部接続パッドと接続されたチップ側パッド群、このチップ側パッド群に連なって前記中継基板の外周側に展開して延びる中継配線群及び各中継配線の前記チップ側パッドとは反対側の端部に連なる中継パッド群からなる表面回路パターンと、
複数の導電路が前記中継基板の表面に対して交差する方向に延びて形成され、かつ前記各導電路が絶縁性樹脂によって相互に絶縁された状態とされ、前記導電路の前記中継基板側の端部が前記中継パッドに接続され、前記導電路の前記中継基板とは反対側の端部が前記プリント基板側に接続されるポストアレイとを備えた半導体装置。 - 前記中継基板の前記表面回路パターンを形成した表面には、前記半導体チップの電源系のためのバイパスコンデンサ又はI/O端子のためのクランプダイオードが形成されている請求項1記載の半導体装置。
- 前記中継基板の表面に形成されて前記バイパスコンデンサを構成する面電極には、前記半導体チップのI/O用電源のための前記外部接続パッドが半田を介して接続されている請求項2記載の半導体装置。
- 前記ポストアレイは、複数本の金属線が軸方向を揃えて並べられ、かつ前記各金属線が絶縁性樹脂によって相互の間隔が保持された状態としたものを前記金属線を横断して切断することで製造されたものである請求項1ないし請求項3のいずれか一項に記載の半導体装置。
- 前記半導体チップに、複数個の前記ポストアレイが互いに間隔を空けて接合されている請求項1ないし請求項4のいずれか一項に記載の半導体装置。
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EP2704189A1 (en) | 2014-03-05 |
KR20140012680A (ko) | 2014-02-03 |
JP5474127B2 (ja) | 2014-04-16 |
CN103582945B (zh) | 2016-10-12 |
US20140070368A1 (en) | 2014-03-13 |
JP2013239530A (ja) | 2013-11-28 |
EP2704189B1 (en) | 2018-08-29 |
EP2704189A4 (en) | 2015-10-07 |
CN103582945A (zh) | 2014-02-12 |
US9153549B2 (en) | 2015-10-06 |
KR101531552B1 (ko) | 2015-06-26 |
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