JP2008098273A - 複合部品 - Google Patents
複合部品 Download PDFInfo
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- JP2008098273A JP2008098273A JP2006276199A JP2006276199A JP2008098273A JP 2008098273 A JP2008098273 A JP 2008098273A JP 2006276199 A JP2006276199 A JP 2006276199A JP 2006276199 A JP2006276199 A JP 2006276199A JP 2008098273 A JP2008098273 A JP 2008098273A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19106—Disposition of discrete passive components in a mirrored arrangement on two different side of a common die mounting substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
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Abstract
【解決手段】複合部品10は、複数の表面電極が配置された主面12bを有する平板状基体12と、複数の第1表面電極32が配置された第1主面と、複数の第2表面電極36が配置された第2主面とを有する枠状基体20とを備え、平板状基体12の主面12bに配置された複数の表面電極と枠状基体20の第1主面に配置された第1表面電極32とを介して、平板状基体12と枠状基体20とが貼り合わされてなる。枠状基体20は、第2表面電極36の間において第2主面22aに連通するスリット26が形成されている。
【選択図】図3
Description
12 基板(平板状基体)
12a 他方主面
12b 一方主面
16 端子(表面電極)
20 枠体(枠状基体)
22 枠部材
22a 面(第1主面)
22b 面(第2主面)
23 貫通穴
30 接続部材
32 第1片(第1表面電極)
34 中間片
36 第2片(第2表面電極)
Claims (6)
- 複数の表面電極が配置された主面を有する平板状基体と、
複数の第1表面電極が配置された第1主面と、複数の第2表面電極が配置された第2主面とを有する枠状基体とを備え、
前記平板状基体の前記主面に配置された複数の前記表面電極と前記枠状基体の前記第1主面に配置された前記第1表面電極とを介して、前記平板状基体と前記枠状基体とが貼り合わされてなる複合部品であって、
前記枠状基体は、前記第2表面電極の間において前記第2主面に連通するスリットが形成されていることを特徴とする、複合部品。 - 前記枠状基体は、樹脂製の枠部材から前記第1表面電極及び前記第2表面電極が露出していることを特徴とする、請求項1に記載の複合部品。
- 前記枠状基体は、金属薄板の打ち抜き加工及び折り曲げ加工により前記第1表面電極と前記第2表面電極とが形成されている接続部材を有し、
前記枠体の前記枠部材は、金型内に前記接続部材となる部分を挿入した状態で成形された樹脂であることを特徴とする、請求項2に記載の複合部品。 - 前記接続部材は可撓性を有していることを特徴とする、請求項3に記載の複合部品。
- 前記枠状基体の前記第2表面電極は、前記複合部品を回路基板に接続するための端子電極であることを特徴とする、請求項1〜4のいずれか一項に記載の複合部品。
- 前記平板状基体は、複数のセラミック層を積層してなるセラミック多層基板であることを特徴とする、請求項1〜4のいずれか一項に記載の複合部品。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006276199A JP4957163B2 (ja) | 2006-10-10 | 2006-10-10 | 複合部品 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006276199A JP4957163B2 (ja) | 2006-10-10 | 2006-10-10 | 複合部品 |
Publications (2)
Publication Number | Publication Date |
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JP2008098273A true JP2008098273A (ja) | 2008-04-24 |
JP4957163B2 JP4957163B2 (ja) | 2012-06-20 |
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JP2006276199A Active JP4957163B2 (ja) | 2006-10-10 | 2006-10-10 | 複合部品 |
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Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010171307A (ja) * | 2009-01-26 | 2010-08-05 | Panasonic Corp | 撮像装置 |
JP2010212481A (ja) * | 2009-03-11 | 2010-09-24 | Panasonic Corp | 撮像装置 |
JP2011228321A (ja) * | 2010-04-15 | 2011-11-10 | Furukawa Electric Co Ltd:The | 基板および基板の製造方法 |
WO2013172060A1 (ja) * | 2012-05-14 | 2013-11-21 | 株式会社野田スクリーン | 半導体装置 |
JP5531122B1 (ja) * | 2013-01-25 | 2014-06-25 | 株式会社野田スクリーン | 半導体装置 |
KR20140085875A (ko) * | 2012-12-28 | 2014-07-08 | 에스케이하이닉스 주식회사 | 반도체 패키지용 기판, 이를 이용한 반도체 패키지 및 그 제조방법 |
KR20140113321A (ko) * | 2013-03-15 | 2014-09-24 | 가부시키가이샤 무라타 세이사쿠쇼 | 모듈 및 그 제조 방법 |
JPWO2014128795A1 (ja) * | 2013-02-22 | 2017-02-02 | パナソニック株式会社 | 電子部品パッケージ |
JP2021128526A (ja) * | 2020-02-13 | 2021-09-02 | パナソニックIpマネジメント株式会社 | 耐タンパ壁、及び、情報処理装置 |
WO2022209729A1 (ja) * | 2021-03-31 | 2022-10-06 | 株式会社村田製作所 | 高周波モジュール及び通信装置 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61280627A (ja) * | 1985-05-08 | 1986-12-11 | Sanyo Electric Co Ltd | 半導体装置 |
JPH06169037A (ja) * | 1992-11-30 | 1994-06-14 | Nec Corp | 半導体パッケージ |
JPH06302709A (ja) * | 1993-04-15 | 1994-10-28 | Kokusai Electric Co Ltd | 表面実装型混成集積回路装置 |
JP2000101348A (ja) * | 1998-09-17 | 2000-04-07 | Toyo Commun Equip Co Ltd | 電子部品用パッケージ |
WO2006027888A1 (ja) * | 2004-09-08 | 2006-03-16 | Murata Manufacturing Co., Ltd. | 複合セラミック基板 |
-
2006
- 2006-10-10 JP JP2006276199A patent/JP4957163B2/ja active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61280627A (ja) * | 1985-05-08 | 1986-12-11 | Sanyo Electric Co Ltd | 半導体装置 |
JPH06169037A (ja) * | 1992-11-30 | 1994-06-14 | Nec Corp | 半導体パッケージ |
JPH06302709A (ja) * | 1993-04-15 | 1994-10-28 | Kokusai Electric Co Ltd | 表面実装型混成集積回路装置 |
JP2000101348A (ja) * | 1998-09-17 | 2000-04-07 | Toyo Commun Equip Co Ltd | 電子部品用パッケージ |
WO2006027888A1 (ja) * | 2004-09-08 | 2006-03-16 | Murata Manufacturing Co., Ltd. | 複合セラミック基板 |
Cited By (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010171307A (ja) * | 2009-01-26 | 2010-08-05 | Panasonic Corp | 撮像装置 |
JP2010212481A (ja) * | 2009-03-11 | 2010-09-24 | Panasonic Corp | 撮像装置 |
JP2011228321A (ja) * | 2010-04-15 | 2011-11-10 | Furukawa Electric Co Ltd:The | 基板および基板の製造方法 |
US9153549B2 (en) | 2012-05-14 | 2015-10-06 | Noda Screen Co., Ltd. | Semiconductor device |
WO2013172060A1 (ja) * | 2012-05-14 | 2013-11-21 | 株式会社野田スクリーン | 半導体装置 |
KR101963722B1 (ko) * | 2012-12-28 | 2019-07-31 | 에스케이하이닉스 주식회사 | 반도체 패키지용 기판, 이를 이용한 반도체 패키지 및 그 제조방법 |
KR20140085875A (ko) * | 2012-12-28 | 2014-07-08 | 에스케이하이닉스 주식회사 | 반도체 패키지용 기판, 이를 이용한 반도체 패키지 및 그 제조방법 |
JP5531122B1 (ja) * | 2013-01-25 | 2014-06-25 | 株式会社野田スクリーン | 半導体装置 |
JPWO2014128795A1 (ja) * | 2013-02-22 | 2017-02-02 | パナソニック株式会社 | 電子部品パッケージ |
KR20140113321A (ko) * | 2013-03-15 | 2014-09-24 | 가부시키가이샤 무라타 세이사쿠쇼 | 모듈 및 그 제조 방법 |
JP2014179472A (ja) * | 2013-03-15 | 2014-09-25 | Murata Mfg Co Ltd | モジュールおよびその製造方法 |
US9456503B2 (en) | 2013-03-15 | 2016-09-27 | Murata Manufacturing Co., Ltd. | Module and method of manufacturing the same |
KR101665992B1 (ko) * | 2013-03-15 | 2016-10-13 | 가부시키가이샤 무라타 세이사쿠쇼 | 모듈 및 그 제조 방법 |
JP2021128526A (ja) * | 2020-02-13 | 2021-09-02 | パナソニックIpマネジメント株式会社 | 耐タンパ壁、及び、情報処理装置 |
US11432399B2 (en) | 2020-02-13 | 2022-08-30 | Panasonic Intellectual Property Management Co., Ltd. | Tamper resistance wall structure |
WO2022209729A1 (ja) * | 2021-03-31 | 2022-10-06 | 株式会社村田製作所 | 高周波モジュール及び通信装置 |
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