JP4788581B2 - 複合基板 - Google Patents
複合基板 Download PDFInfo
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- JP4788581B2 JP4788581B2 JP2006329763A JP2006329763A JP4788581B2 JP 4788581 B2 JP4788581 B2 JP 4788581B2 JP 2006329763 A JP2006329763 A JP 2006329763A JP 2006329763 A JP2006329763 A JP 2006329763A JP 4788581 B2 JP4788581 B2 JP 4788581B2
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- piece
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- frame member
- substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Description
12,12t 基板本体
12a 他方主面
12b 一方主面
18 端子
20 枠体
22 枠部材
23 貫通穴
30 接続部材
32 第1片
34 中間片
36 第2片
40,42,50,55 チップ状電子部品
Claims (14)
- 少なくとも一方主面に端子を有する基板本体と、
前記基板本体の前記一方主面に接合される枠体と、
を備えた複合基板であって、
前記枠体は、
絶縁材料からなり、中央に貫通穴を有し、前記基板本体の前記一方主面の周縁部に沿って枠状に延在する枠部材と、
金属薄板の折り曲げ加工により形成され、中間片の両端にそれぞれ屈曲部を介して第1片と第2片とが連続する複数の接続部材と、
を有し、
前記複数の接続部材は、
前記枠部材に配置され、
前記中間片が、前記枠部材に埋め込まれ、又は前記枠部材の前記貫通穴の内面に沿って配置され、少なくとも前記中間片の前記第1片側と前記第2片側との間の中間部分が前記枠部材に固定され、
前記中間片と前記第1片との間の前記屈曲部が、前記枠部材の前記基板本体に対向する面に配置され、前記中間片と前記第2片との間の前記屈曲部が、前記枠部材の前記基板本体とは反対側の面とに配置され、
前記第1片が、前記枠部材の前記基板本体側に露出して、前記基板本体の前記一方主面の前記端子に接合され、
前記第2片が、前記枠部材の前記基板本体とは反対側に露出し、
前記第1片又は前記第2片の少なくとも一方が、前記枠部材から離間して可動であることを特徴とする複合基板。 - 前記接続部材の前記第1片は、前記中間片とは反対側の部分が前記枠部材に埋め込まれていることを特徴とする、請求項1に記載の複合部材。
- 前記接続部材の前記中間片は、
前記枠部材の前記貫通穴の前記内面に沿って配置され、
前記第1片側と前記第2片側との間の前記中間部分のみが、前記枠部材に固定され、
前記中間片の前記第1片側及び前記第2片側の両端部分が、前記枠部材の前記貫通穴の前記内面から接離可能であることを特徴とする、請求項1に記載の複合基板。 - 前記枠部材の前記基板本体の前記一方主面に対向する面に、突起部が設けられ、
前記接続部材の前記第1片は、前記突起部の前記基板本体の前記一方主面に対向する面に沿って延在することを特徴とする、請求項1に記載の複合基板。 - チップ状電子部品が前記枠状部材の前記貫通穴内に配置され、前記基板本体の前記一方主面に搭載されていることを特徴とする、請求項1〜4のいずれか一項に記載の複合基板。
- 前記チップ状電子部品が樹脂で封止され、該樹脂が前記枠体の一部に接着又は当接していることを特徴とする、請求項5に記載の複合基板。
- 前記枠体の前記接続部材は、金属薄板の打ち抜き加工及び折り曲げ加工により形成され、
前記枠体の前記枠部材は、金型内に前記接続部材となる部分を挿入した状態で成形した樹脂であることを特徴とする、請求項1〜6のいずれか一項に記載の複合基板。 - 前記基板本体がセラミック基板であることを特徴とする、請求項1〜7のいずれか一項に記載の複合基板。
- 前記基板本体は、1050℃以下で焼結する複数のセラミック層を積層してなるセラミック多層基板であることを特徴とする、請求項1〜8のいずれか一項に記載の複合基板。
- 前記枠体の前記接続部材の前記金属薄板は可撓性を有することを特徴とする、請求項7に記載の複合基板。
- 前記接続部材の厚みは、50μm以上、かつ300μm以下であることを特徴とする、請求項1〜10のいずれか一項に記載の複合基板。
- 前記基板本体の他方主面に、チップ状電子部品が搭載されていることを特徴とする、請求項1〜11のいずれか一項に記載の複合基板。
- 外部回路基板の端子に、請求項1〜12のいずれか一項に記載の複合基板の前記接続部材の前記第2片が接合されていることを特徴とする、複合部品。
- 少なくとも一方主面に端子が設けられた基板本体と、枠体とを準備する第1の工程と、
前記基板本体の前記一方主面に、前記枠体を接合する第2の工程とを備えた、複合基板の製造方法であって、
前記第1の工程において、
前記枠体は、
絶縁材料からなり、中央に貫通穴を有する枠部材と、
金属薄板の折り曲げ加工により形成され、中間片の両端にそれぞれ屈曲部を介して第1片と第2片とが連続する複数の接続部材と、
を有し、
前記複数の接続部材は、
前記枠部材に配置され、
前記中間片が、前記枠部材に埋め込まれ、又は前記枠部材の前記貫通穴の内面に沿って配置され、少なくとも前記中間片の前記第1片側と前記第2片側との間の中間部分が前記枠部材に固定され、
前記中間片と前記第1片との間の前記屈曲部が前記枠部材の一方主面に配置され、前記中間片と前記第2片との間の前記屈曲部が前記枠部材の他方主面に配置され、
前記第1片及び第2片が、前記枠部材の前記貫通穴の周囲に延在する前記枠部材の前記両主面にそれぞれ露出し、
前記第1片及び前記第2片が、前記接続部材が前記枠部材の前記貫通穴を介して対向する方向に延在し、
前記第2の工程において、
前記枠体は、前記基板本体の前記一方主面に、前記枠部材が前記基板本体の前記一方主面の周縁部に沿って枠状に延在するように配置され、
前記枠体の前記接続部材の前記第1片が、前記基板本体の前記一方主面に設けられた前記端子に接合されることを特徴とする、複合基板の製造方法。
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JP2006329763A JP4788581B2 (ja) | 2006-12-06 | 2006-12-06 | 複合基板 |
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JP2006329763A JP4788581B2 (ja) | 2006-12-06 | 2006-12-06 | 複合基板 |
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JP2008147251A JP2008147251A (ja) | 2008-06-26 |
JP4788581B2 true JP4788581B2 (ja) | 2011-10-05 |
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JP5406767B2 (ja) * | 2010-03-24 | 2014-02-05 | ユニオンマシナリ株式会社 | 温度センサーユニット |
KR102556327B1 (ko) * | 2016-04-20 | 2023-07-18 | 삼성전자주식회사 | 패키지 모듈 기판 및 반도체 모듈 |
US11778747B2 (en) * | 2018-11-08 | 2023-10-03 | Kyocera Corporation | Wiring board, composite substrate, and electric device |
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JP3232723B2 (ja) * | 1992-03-09 | 2001-11-26 | 松下電器産業株式会社 | 電子回路装置およびその製造方法 |
JPH0685102A (ja) * | 1992-08-31 | 1994-03-25 | Nec Corp | 半導体集積回路装置 |
JP4572467B2 (ja) * | 2001-01-16 | 2010-11-04 | 株式会社デンソー | マルチチップ半導体装置およびその製造方法 |
JP2005235807A (ja) * | 2004-02-17 | 2005-09-02 | Murata Mfg Co Ltd | 積層型電子部品およびその製造方法 |
JP4258432B2 (ja) * | 2004-05-21 | 2009-04-30 | パナソニック株式会社 | 基板接合部材ならびにそれを用いた三次元接続構造体 |
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