JPWO2014128795A1 - 電子部品パッケージ - Google Patents
電子部品パッケージ Download PDFInfo
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- JPWO2014128795A1 JPWO2014128795A1 JP2015501086A JP2015501086A JPWO2014128795A1 JP WO2014128795 A1 JPWO2014128795 A1 JP WO2014128795A1 JP 2015501086 A JP2015501086 A JP 2015501086A JP 2015501086 A JP2015501086 A JP 2015501086A JP WO2014128795 A1 JPWO2014128795 A1 JP WO2014128795A1
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K5/00—Casings, cabinets or drawers for electric apparatus
- H05K5/02—Details
- H05K5/0247—Electrical details of casings, e.g. terminals, passages for cables or wiring
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K5/00—Casings, cabinets or drawers for electric apparatus
- H05K5/0004—Casings, cabinets or drawers for electric apparatus comprising several parts forming a closed casing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/20—Details of printed circuits not provided for in H05K2201/01 - H05K2201/10
- H05K2201/2018—Presence of a frame in a printed circuit or printed circuit assembly
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
Description
第1の実施形態に係る電子部品パッケージの構造について、図1A〜図3を用いて説明する。図1Aは本実施形態に係る電子部品パッケージを外部端子側から見た平面図である。図1Bは、図1AにおけるX−X間の断面図であり、図1Cは、図1AにおけるY−Y間の断面図である。
次に上述した実施形態の変形例として半導体チップ2が長方形である場合について図8Aおよび図8Bを用いて説明する。ここでは、半導体チップ2が正方形である場合との差異を中心に説明する。
別の変形例として、複数の半導体チップ2A,2Bが搭載されている場合について図11A〜図11Cおよび図12A、図12Bを用いて説明する。本変形例では、半導体チップが1つの場合との差異を中心に説明する。
さらに変形例として面積の異なる複数の半導体チップ2A,2Bが搭載されている場合について図14A〜図16を用いて説明する。ここでは、変形例2との差異を中心に説明する。
図17A〜図17Cは、変形例4に係る電子部品パッケージの平面および断面を示す模式図である。なお、図17Aでは、半導体チップ2の形状が正方形であるが、長方形であってもよい。本変形例では、図1Aとの差を中心に説明する。
図18は、第2の実施形態に係る電子部品パッケージの断面を示す模式図である。本実施形態に係る電子部品パッケージにおいて、枠体5の外部端子4A、枠体5を介して外部端子4Aと対向する接続端子65A、接続端子65Aと対向する主基板1の接続端子61A、および接続端子61Aと接続端子65Aとの間に形成された接合金属7Aは、それぞれ、他の外部端子4、他の接続端子65、他の接続端子61、および他の接合金属7よりも面積が大きくなっている。つまり、図18は、これら接続部の面積が大きくなっている箇所の断面図である。
図19は、第3の実施形態に係る電子部品パッケージの断面を示す模式図である。本実施形態では、主に第2の実施形態との差異について説明する。
図20は、第4の実施形態に係る電子部品パッケージの断面を示す模式図である。本実施形態では、主に第3の実施形態との差異について説明する。
2,2A,2B 半導体チップ
3,3A,3B,31 アンダーフィル
4,4A,4B,4A’ 外部端子
5,50 枠体
7,7A,7B,7B’ 接合金属
8,8A,8B 接合金属
9 基板
10 接合金属
32 樹脂ペースト
50’ 仕切り部
51,51A,51B,51C,
51A’,51B’,52 配線
53 切り欠き部
61,61A,61B,61B’ 接続端子
65,65A,65B,65B’ 接続端子
81 ワイヤーボンド
Claims (15)
- 主基板と、
前記主基板の主面上に設けられた第1の電子部品と、
前記主基板の主面と対向するように配置された枠体と、
前記主基板の主面上において、前記枠体の第1の辺に沿って配置された第1の接続端子と第2の接続端子とを備え、
前記第2の接続端子は、前記枠体の第1の辺における、前記第1の電子部品の辺の中点近傍に対向する位置に配置され、
前記第2の接続端子は前記第1の接続端子よりも面積が大きい
ことを特徴とする電子部品パッケージ。 - 前記第2の接続端子は、前記第1の辺と平行方向の辺が前記第1の接続端子よりも長い
ことを特徴とする請求項1に記載の電子部品パッケージ。 - 前記第2の接続端子は、前記第1の辺と垂直方向の辺が前記第1の接続端子よりも長い
ことを特徴とする請求項1に記載の電子部品パッケージ。 - 前記第1の辺の一部における、前記主基板の主面と前記枠体との間には、樹脂が充填されている
ことを特徴とする請求項1〜3のうちのいずれか1項に記載の電子部品パッケージ。 - 前記第1の電子部品は、前記主基板の主面と前記枠体との間に充填された樹脂と同一の樹脂を介して前記主基板の主面上に配置されている
ことを特徴とする請求項4に記載の電子部品パッケージ。 - 前記主基板の主面上には第2の電子部品が設けられ、
前記第1の電子部品は前記第2の電子部品よりも面積が大きい
ことを特徴とする請求項1〜5のうちのいずれか1項に記載の電子部品パッケージ。 - 前記第1の電子部品は、半導体チップである
ことを特徴とする請求項1〜6のうちのいずれか1項に記載の電子部品パッケージ。 - 前記第2の接続端子に対向する位置における前記枠体の底面の辺の幅は、他の位置における前記枠体の底面の辺の幅よりも広い
ことを特徴とする請求項1〜7のうちのいずれか1項に記載の電子部品パッケージ。 - 前記第2の接続端子は、ダミー端子である
ことを特徴とする請求項1〜8のうちのいずれか1項に記載の電子部品パッケージ。 - 前記第2の接続端子は、グラウンド部に接続されている
ことを特徴とする請求項1〜9のうちのいずれか1項に記載の電子部品パッケージ。 - 前記枠体の底面上には第1の外部端子及び第2の外部端子が配置され、
前記第2の外部端子は前記第2の接続端子と電気的に接続され、
前記第2の外部端子は前記第1の外部端子よりも面積が大きい
ことを特徴とする請求項1〜10のうちのいずれか1項に記載の電子部品パッケージ。 - 前記枠体の主面上には第3の外部端子及び第4の外部端子が配置され、
前記第4の外部端子は前記第3の外部端子よりも面積が大きい
ことを特徴とする請求項11に記載の電子部品パッケージ。 - 前記第4の外部端子は、前記第2の外部端子と対向する位置に設けられている
ことを特徴とする請求項12に記載の電子部品パッケージ。 - 前記第4の外部端子は、前記枠体の主面上において、当該主面上の辺のうち前記第1の辺と対向する辺の角部に設けられている
ことを特徴とする請求項12に記載の電子部品パッケージ。 - 前記枠体の第1の辺は、前記枠体の各辺のうち前記第1の電子部品との距離が最も短い辺である
ことを特徴とする請求項1〜14のうちのいずれか1項に記載の電子部品パッケージ。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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JP2013033325 | 2013-02-22 | ||
JP2013033325 | 2013-02-22 | ||
PCT/JP2013/005898 WO2014128795A1 (ja) | 2013-02-22 | 2013-10-03 | 電子部品パッケージ |
Publications (2)
Publication Number | Publication Date |
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JPWO2014128795A1 true JPWO2014128795A1 (ja) | 2017-02-02 |
JP6245249B2 JP6245249B2 (ja) | 2017-12-13 |
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JP (1) | JP6245249B2 (ja) |
WO (1) | WO2014128795A1 (ja) |
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WO2016105435A1 (en) * | 2014-12-26 | 2016-06-30 | Intel Corporation | Assembly architecture employing organic support for compact and improved assembly throughput |
JPWO2017094062A1 (ja) * | 2015-11-30 | 2018-06-14 | ルネサスエレクトロニクス株式会社 | 電子装置 |
CN210443547U (zh) | 2017-03-31 | 2020-05-01 | 株式会社村田制作所 | 电子设备 |
US11848280B2 (en) * | 2020-11-25 | 2023-12-19 | ADVANCED SEMlCONDUCTOR ENGINEERING, INC. | Method for manufacturing assembly structure by using frame structure on substrate |
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