JP2020136624A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP2020136624A JP2020136624A JP2019032322A JP2019032322A JP2020136624A JP 2020136624 A JP2020136624 A JP 2020136624A JP 2019032322 A JP2019032322 A JP 2019032322A JP 2019032322 A JP2019032322 A JP 2019032322A JP 2020136624 A JP2020136624 A JP 2020136624A
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- Prior art keywords
- interposer
- wiring
- semiconductor device
- electrode
- back surface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15173—Fan-out arrangement of the internal vias in a single layer of the multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Description
Claims (4)
- 金属バンプを有する半導体チップと、有機基板の表面に前記金属バンプとフリップチップ接合する配線を配置し前記有機基板の裏面に前記配線と貫通孔を介して接続する裏面電極と該裏面電極に重ならないように補強電極を配置したインターポーザを備えた半導体装置において、
前記金属バンプと前記配線との接合部直下の前記インターポーザの縦構造が全て同一であることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、裏面に前記裏面電極と前記補強電極のない領域の前記インターポーザの表面に前記配線を延出し、前記接合部を配置していることを特徴とする半導体装置。
- 請求項1記載の半導体装置において、裏面に前記補強電極のある領域の前記インターポーザの表面に前記配線を延出し、前記接合部を配置していることを特徴とする半導体装置。
- 請求項1記載の半導体装置において、表面に前記接合部のある領域の前記インターポーザの裏面に前記裏面電極を延出して配置していることを特徴とする半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2019032322A JP7260220B2 (ja) | 2019-02-26 | 2019-02-26 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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JP2019032322A JP7260220B2 (ja) | 2019-02-26 | 2019-02-26 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
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JP2020136624A true JP2020136624A (ja) | 2020-08-31 |
JP7260220B2 JP7260220B2 (ja) | 2023-04-18 |
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JP2019032322A Active JP7260220B2 (ja) | 2019-02-26 | 2019-02-26 | 半導体装置 |
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JP (1) | JP7260220B2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2022195939A1 (ja) * | 2021-03-18 | 2022-09-22 | 株式会社村田製作所 | 電子部品及び電子装置 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11307886A (ja) * | 1998-04-21 | 1999-11-05 | Matsushita Electric Ind Co Ltd | フリップチップ接合ランドうねり防止パターン |
JP2004095612A (ja) * | 2002-08-29 | 2004-03-25 | Fujitsu Ltd | 半導体装置及び配線基板 |
JP2004327721A (ja) * | 2003-04-24 | 2004-11-18 | Shinko Electric Ind Co Ltd | 配線基板及び電子部品実装構造 |
JP2011198810A (ja) * | 2010-03-17 | 2011-10-06 | Renesas Electronics Corp | 半導体装置の実装構造及び実装方法 |
-
2019
- 2019-02-26 JP JP2019032322A patent/JP7260220B2/ja active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11307886A (ja) * | 1998-04-21 | 1999-11-05 | Matsushita Electric Ind Co Ltd | フリップチップ接合ランドうねり防止パターン |
JP2004095612A (ja) * | 2002-08-29 | 2004-03-25 | Fujitsu Ltd | 半導体装置及び配線基板 |
JP2004327721A (ja) * | 2003-04-24 | 2004-11-18 | Shinko Electric Ind Co Ltd | 配線基板及び電子部品実装構造 |
JP2011198810A (ja) * | 2010-03-17 | 2011-10-06 | Renesas Electronics Corp | 半導体装置の実装構造及び実装方法 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2022195939A1 (ja) * | 2021-03-18 | 2022-09-22 | 株式会社村田製作所 | 電子部品及び電子装置 |
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JP7260220B2 (ja) | 2023-04-18 |
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