Classifications

• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
  • G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
  • G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
  • G11C19/184—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
  • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2310/00—Command of the display device
  • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
  • G09G2310/0264—Details of driving circuits
  • G09G2310/0283—Arrangement of drivers for different directions of scanning
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2310/00—Command of the display device
  • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
  • G09G2310/0264—Details of driving circuits
  • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2310/00—Command of the display device
  • G09G2310/06—Details of flat display driving waveforms
  • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2320/00—Control of display operating conditions
  • G09G2320/02—Improving the quality of display appearance
  • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
  • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
  • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
  • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
  • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
  • G09G3/3266—Details of drivers for scan electrodes
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
  • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
  • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
  • G09G3/3611—Control of matrices with row and column drivers
  • G09G3/3685—Details of drivers for data electrodes
  • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only

Definitions

• the present invention relates to the field of display technologies, and in particular, to a shift register and a display. Background technique
• the shift register is used to provide a drive signal for the gate line, and includes a multi-stage shift register unit.
• FIG. 1A is a schematic structural diagram of a shift register unit in the prior art
• FIG. 1B is a timing diagram of the shift register unit in FIG. 1A.
• the shift register unit includes 12 thin film transistors and a storage capacitor. The shift register unit allows the shift register to implement only the forward scan drive, and the bidirectional scan drive cannot be realized. Summary of the invention
• the embodiment of the present invention provides a shift register for solving the problem that the existing shift register can only implement forward scan driving and cannot realize bidirectional scan driving, and also provides a display including a shift register.
• An embodiment of the present invention provides a shift register including a multi-stage shift register unit, and each stage shift register unit in the multi-stage shift register unit includes:
• a first thin film transistor for charging or discharging a pull-up node under control of a driving input signal and a scan direction selection signal, wherein the first thin film transistor serves as a shift register of the stage during forward scan driving a start switch of the unit, charging the pull-up node, and when the reverse scan is driven, the first thin film transistor acts as a reset switch of the shift register unit of the stage, and discharges the pull-up node;
• a second thin film transistor for discharging or charging the pull-up node under control of the first reset signal and the scan direction selection signal, wherein the second thin film transistor is used as a forward scan drive a reset switch of the shift register unit of the stage, discharging the pull-up node, and in the reverse scan driving, the second thin film transistor is used as a start switch of the shift register unit of the stage, and the pull-up is Point to charge;
• a reset unit configured to reset the pull-up node and the output end
• a pull-up unit for pulling the potential of the output high during the output phase.
• the gate of the first thin film transistor is connected to the input end, and the source is connected to the pull-up Point and drain are connected to the first scanning direction selection signal input end;
• the gate of the second thin film transistor is connected to the first reset signal input terminal, the source is connected to the pull-up node, and the drain is connected to the first scan direction selection signal input terminal.
• the pull-up unit may include:
• a third thin film transistor having a gate connected to the first end of the storage capacitor, a source connected to the output end, and a drain connected to the first clock signal input end;
• the storage capacitor has a first end connected to the pull-up node and a second end connected to the output end.
• the resetting unit may include:
• a fourth thin film transistor having a gate connected to the second clock signal input terminal, a source connected to the low level, and a drain connected to the output terminal;
• a fifth thin film transistor having a gate connected to the pull-down control node, a source connection pull-down node, and a drain connected to the second clock signal input terminal;
• a sixth thin film transistor having a gate connected to the pull-up node, a source connected to the low level, and a drain connected to the pull-down node;
• a seventh thin film transistor having a gate and a drain connected to the second clock signal input end and a source connected to the pull-down control node;
• An eighth thin film transistor having a gate connected to the pull-up node, a source connected to the low level, and a drain connected to the pull-down control node;
• a ninth thin film transistor having a gate connected to the pull-down node, a source connected to the low level, and a drain connected to the pull-up node;
• a tenth thin film transistor having a gate connected to the pull-down node, a source connected to the low level, and a drain connected to the output terminal.
• the shift register unit of each stage may further include:
• the first reset control unit is configured to ensure resetting of the output by the reset unit.
• the first reset control unit may include:
• the eleventh thin film transistor has a gate connected to the first reset signal input end, a source connected low level, and a drain connected output end;
• the twelfth thin film transistor has a gate connected to the input terminal, a source connected to the low level, and a drain connected to the output terminal.
• the resetting unit may include:
• the fifth thin film transistor has a gate connected to the pull-down control node, a source connection pull-down node, and a drain connection Connected to the second clock signal input terminal;
• a sixth thin film transistor having a gate connected to the pull-up node, a source connected to a low level, and a drain connected to the pull-down node;
• a seventh thin film transistor having a gate and a drain connected to the second clock signal input end and a source connected to the pull-down control node;
• An eighth thin film transistor having a gate connected to the pull-up node, a source connected to the low level, and a drain connected to the pull-down control node;
• a ninth thin film transistor having a gate connected to the pull-down node, a source connected to the low level, and a drain connected to the pull-up node;
• a tenth thin film transistor having a gate connected to the pull-down node, a source connected to the low level, and a drain connected to the output terminal;
• a thirteenth thin film transistor having a gate connected to the second reset control unit, a source connected to a low level, and a drain connected to the output terminal;
• the second reset control unit is configured to ensure that the reset unit resets the output end.
• the second reset control unit may include: a fourteenth thin film transistor having a gate connected to the first reset signal input end and a source connected to the gate of the thirteenth thin film transistor The drain is connected to the second scan direction selection signal input end;
• a fifteenth thin film transistor having a gate connected to the input end, a source connected to the gate of the thirteenth thin film transistor, and a drain connected to the second scan direction selection signal input end;
• the sixteenth thin film transistor has a gate connected to the first scan direction selection signal input terminal, a source connected to the low level, and a drain connected to the gate of the thirteenth thin film transistor.
• the second reset control unit may include: a seventeenth thin film transistor having a gate connected to the first reset signal input terminal and a source connected to the thirteenth thin film transistor a gate electrode and a drain connected to the second scan direction selection signal input terminal; an eighteenth thin film transistor having a gate connection input terminal, a source connected to the gate of the thirteenth thin film transistor, and a drain connection a second scanning direction selection signal input end;
• a nineteenth thin film transistor having a gate connected to the second reset signal input terminal, a source connected to the low level, and a drain connected to the gate of the thirteenth thin film transistor;
• the twentieth thin film transistor has a gate connected to the third reset signal input terminal, a source connected to the low level, and a drain connected to the gate of the thirteenth thin film transistor.
• Embodiments of the present invention provide a display including any of the shift registers described.
• the above shift register and display provided by the embodiments of the present invention can implement bidirectional scan driving. DRAWINGS
• 1A is a schematic structural diagram of a conventional shift register unit
• 1B is a timing chart of driving of the shift register unit of FIG. 1A;
• 2A is a schematic structural diagram of a shift register unit according to an embodiment of the present invention.
• FIG. 2B is a schematic structural diagram of another shift register unit according to an embodiment of the present invention
• FIG. 3 is a schematic structural diagram of a shift register unit according to Embodiment 1 of the present invention
• FIG. 4 is a shift register unit having the shift register unit of FIG. Schematic diagram of the shift register
• FIG. 5 is a timing chart of the forward scan drive of the shift register of FIG. 4;
• FIG. 6 is a timing chart of a reverse scan driving of the shift register of FIG. 4;
• FIG. 7 is a schematic structural diagram of a shift register unit in a second embodiment of the present invention
• FIG. 8 is a schematic structural diagram of a shift register having five drive signals in the shift register unit of FIG. 7;
• Figure 10 is a timing chart of the reverse scan driving of the shift register of Figure 8.
• Figure 11 is a block diagram showing the structure of a shift register having six drive signals of the shift register unit of Figure 7;
• Figure 13 is a timing chart of the reverse scan driving of the shift register of Figure 11;
• FIG. 14 is a schematic structural diagram of a shift register unit in a third embodiment of the present invention.
• FIG. 15 is a schematic diagram showing a structure of a shift register having four drive signals in the shift register unit of FIG.
• Figure 16 is a block diagram showing the structure of a shift register unit in a fourth embodiment of the present invention
• Figure 17 is a block diagram showing the structure of a shift register having four drive signals in the shift register unit of Figure 16; detailed description
• Embodiments of the present invention provide a shift register including a multi-stage shift register unit, as shown in the figure As shown in 2A, each stage of the shift register unit in the multi-stage shift register unit includes:
• the first thin film transistor T1 is configured to charge or discharge the pull-up node PU under the control of the driving input signal and the scanning direction selection signal, wherein, in the forward scanning driving, the first thin film transistor
• T1 is used as a start switch of the shift register unit of the stage to charge the pull-up node PU.
• the first thin film transistor T1 acts as a reset switch of the shift register unit of the stage, and the pull-up node PU Perform discharge
• a second thin film transistor T2 for discharging or charging the pull-up node PU under the control of the first reset signal and the scan direction selection signal, wherein, in the forward scan driving, the second thin film transistor
• the second thin film transistor T2 is used as a reset switch of the shift register unit of the stage to discharge the pull-up node PU.
• the second thin film transistor T2 acts as a start switch of the shift register unit of the stage, and pulls up the node PU.
• a reset unit for resetting the pull-up node PU and the output terminal OUT;
• Pull-up unit for pulling the potential of the output OUT high during the output phase.
• the gate of the first thin film transistor T1 can be connected to the input terminal INPUT, the source is connected to the pull-up node PU, and the drain is connected to the first scan direction selection signal input terminal CLK';
• the gate of the thin film transistor T2 is connected to the first reset signal input terminal RESET, the source connection pull-up node PU, and the drain connection first scan direction selection signal input terminal CLK'.
• the above pull-up unit may include:
• the third thin film transistor T3 has a first terminal connected to the storage capacitor C1, a source connected to the output terminal OUT, and a drain connected to the first clock signal input terminal CLK;
• the storage capacitor C1 has a first end connected to the pull-up node PU and a second end connected to the output end ⁇ .
• the foregoing resetting unit may specifically include:
• the fourth thin film transistor ⁇ 4 has a gate connected to the second clock signal input terminal CLKB, a source connected to the low level VSS, and a drain connected to the output terminal OUT;
• the fifth thin film transistor T5 has a gate connected to the pull-down control node PD-CN, a source connection pull-down node PD, and a drain connection second clock signal input terminal CLKB;
• the sixth thin film transistor T6 has a gate connected to the pull-up node PU, a source connected low level VSS, and a drain connected pull-down node PD; a seventh thin film transistor T7 having a gate and a drain connected to the second clock signal input terminal CLKB and a source connection pull-down control node PD-CN;
• the eighth thin film transistor T8 has a gate connected to the pull-up junction PU, a source connected low level VSS, and a drain connection pull-down control node PD-CN;
• the ninth thin film transistor T9 has a gate connected to the pull-down node PD, a source connected to the low level VSS, and a drain connected to the pull-up node PU;
• the tenth thin film transistor T10 has a gate connected to the pull-down node PD, a source connected to the low level VSS, and a drain connected to the output terminal OUT.
• the structure of the shift register having the shift register unit shown in Fig. 3 is as shown in Fig. 4, and the forward scan drive timing is as shown in Fig. 5, and the reverse scan drive timing is as shown in Fig. 6.
• the main feature of the shift register is that the first clock signal input terminal CLK and the second clock signal input terminal CLKB of the adjacent shift register unit are alternately connected to the driving signals CLK and CLKB, respectively;
• the first scanning direction selection signal input terminal CLK of the bit register unit is respectively connected to the driving signals clk3, clk4, wherein two adjacent ones are connected to the same driving signal, and the other two are connected to another driving signal (such as clk3, clk3, clk4) , clk4, or clk4, clk4, clk3, clk3, or clk3, clk4, clk4, clk3, or clk4, clk4, clk3, or clk4, clk3, or clk4, clk3, clk3, clk4, drive timing needs to match the connection mode);
• input register INPUT of the shift register unit is connected to the previous one
• the driving signal of the first scanning direction selection signal input terminal CLK' connected to the shift register unit should satisfy three requirements: one is that the input (INPUT) phase is high level, and the other is that the reset phase is low level, and at the same time, When the frame start signal is high, the signal connected to the first scan direction selection signal input terminal CLK' of the first stage shift register unit and the last stage shift register unit is one high level and one low level. level.
• the first thin film transistor T1 is turned on.
• the clk3 connected to the first scan direction selection signal input terminal CLK' is also at a high level, and the PU node is charged.
• the first clock signal CLK becomes a high level
• the output GL1 also becomes a high level
• GL1 also serves as a gate input signal of the second stage shift register unit, then the second stage
• the first thin film transistor T1 of the shift register unit is also turned on.
• the clk3 connected to the first scan direction selection signal input terminal CLK' of the second stage shift register unit is still at a high level, and the second stage shift The pull-up node PU of the register unit is charged.
• the Reset signal of the first stage shift register unit becomes a high level
• the second thin film transistor T2 is turned on, and this
• the first scan direction of the first stage shift register unit selects the signal input terminal CLK, and the connected clk3 becomes a low level
• the pull-up node PU is pulled low, thereby realizing the pull-up node PU reset;
• the clock signal input terminal CLK becomes a low level
• the second clock signal input terminal CLKB becomes a high level
• the fourth thin film transistor T4 is turned on
• the seventh thin film transistor T7 is turned on
• the eighth thin film transistor T8 and the sixth thin film are turned on.
• the pull-down control node PD_CN becomes a high level
• the fifth thin film transistor ⁇ 5 is turned on
• the pull-down node PD also becomes a high level
• the tenth thin film transistor ⁇ 10 and the ninth thin film transistor ⁇ 9 are also On, the output OUT is pulled low to VSS to reset.
• the other shift register units are similar here, and the scan control signal output is implemented row by row.
• the shift register drive signal CLK is swapped with the CLKB timing, and the direction select signal clk3 is interchanged with clk4.
• the timing is as shown in FIG. 6.
• the second thin film transistor T2 is turned on.
• the clk4 connected to the first scan direction selection signal input terminal CLK' is also at a high level, and then the pull-up is performed. Point PU charging.
• the second clock signal CLKB becomes a high level
• the output GLn also becomes a high level
• GLn also serves as an input signal of the n-1th stage shift register unit
• the n-th The second thin film transistor T2 of the 1-stage shift register unit is also turned on.
• the clk4 connected to the first scan direction selection signal input terminal CLK' of the n-1th stage shift register unit is still at the high level, then The pull-up node PU of the n-1 stage shift register unit is charged.
• the RESET phase which is also the output stage of the n-1th stage shift register unit
• GL(nl) goes high
• the reset signal of the nth stage shift register unit that is, the first input signal INPUT end becomes high.
• the first thin film transistor T1 is turned on, and at this time, the clk4 connected to the first scan direction selection signal input terminal CLK' becomes a low level, and the pull-up node PU is pulled low, and the pull-up is realized.
• the second clock signal input terminal CLKB becomes low level
• the first clock signal input terminal CLK changes
• the fourth thin film transistor T4 is turned on
• the seventh thin film transistor ⁇ 7 is turned on
• the eighth thin film transistor ⁇ 8 and the sixth thin film transistor ⁇ 6 are turned off
• the pull-down control node PD-CN becomes high level
• the thin film transistor ⁇ 5 is turned on and the pull-down node PD is also turned to the high level
• the tenth thin film transistor ⁇ 10 and the ninth thin film transistor ⁇ 9 are also turned on, and the output is pulled down to VSS to be reset.
• the other shift register units are similar to this, and the scan control signal output is implemented row by row.
• STV-F and STV- ⁇ are the same signal, they are collectively referred to as STV.
• STV In the forward scan drive, when STV is high, clk3 is high, then the first thin film transistor T1 of the first stage shift register unit is turned on, and the pull-up node PU is charged; at this time, clk4 is low.
• the first thin film transistor T1 of the last stage shift register unit is also turned on, the pull-up node PU is not charged, is still low, and does not activate the unit.
• the reverse scan is driven, the last stage shift register unit is activated, and the first stage shift register unit is not activated. Thereby a two-way scan drive can be implemented.
• the shift register unit connection period of FIG. 4 is 4, and n is exactly an integer multiple of 4, if not, the drive timing, the connection mode, or the empty shift register unit should be adjusted to satisfy Three requirements for the scan direction selection signal.
• the shift register unit shown in Figure 3 can realize 8-clock drive by two repetitive structures and shifted drive clock signals, which can effectively reduce the power consumption of the gate driver.
• the scanning direction selection signal can be two, three, four or more, and the driving timing and connection mode can be adjusted accordingly.
• the above-mentioned shift register unit of each stage can also add a first reset control unit based on the structure shown in FIG. 3 to ensure the reset of the output terminal by the reset unit shown in FIG.
• the first reset control unit may include:
• the eleventh thin film transistor T11 has a gate connected to the first reset signal input terminal RESET, a source connected low level VSS, and a drain connected output terminal OUT;
• the twelfth thin film transistor T12 has a gate connected to the input terminal INPUT, a source connected to the low level VSS, and a drain connected to the output terminal OUT.
• the structure of the shift register of the five drive signals (5-clock) having the shift register unit shown in FIG. 7 is as shown in FIG. 8; the forward scan drive timing is as shown in FIG.
• the drive timing is shown in Figure 10.
• the structure of the shift register of the six drive signals (6-clock) having the shift register unit shown in FIG. 7 is as shown in FIG. 11; the forward scan drive timing is as shown in FIG. 12, and the reverse scan drive timing is as shown in FIG. Figure 13 shows.
• the fourth thin film transistor T4 is subjected to a large voltage, the duty ratio is about 50%, which causes a large threshold voltage shift, which is not conducive to the stability of the gate driving; and the eleventh thin film transistor T11 is added.
• the twelfth thin film transistor T12 can ensure the reliability of the output reset, thereby enhancing the reliability of the gate drive.
• the output terminal OUT is reset by the eleventh thin film transistor T11; when the reverse scanning is performed, the output terminal OUT is reset by the twelfth thin film transistor T12.
• the reset unit may further include:
• the fifth thin film transistor T5 has a gate connected to the pull-down control node PD-CN, a source connection pull-down node PD, and a drain connection second clock signal input terminal CLKB;
• the sixth thin film transistor T6 has a gate connected to the pull-up node PU, a source connected to the low level VSS, and a drain connected to the pull-down node PD;
• a seventh thin film transistor T7 having a gate and a drain connected to the second clock signal input terminal CLKB and a source connection pull-down control node PD-CN;
• the eighth thin film transistor T8 has a gate connected to the pull-up junction PU, a source connected low level VSS, and a drain connection pull-down control node PD-CN;
• the ninth thin film transistor T9 has a gate connected to the pull-down node PD, a source connected to the low level VSS, and a drain connected to the pull-up node PU;
• the tenth thin film transistor T10 has a gate connected to the pull-down node PD, a source connected to the low level VSS, and a drain connected to the output terminal OUT;
• the thirteenth thin film transistor T13 has a gate connected to the second reset control unit, a source connected to the low level VSS, and a drain connected output terminal OUT;
• the second reset control unit is configured to ensure that the reset unit resets the output terminal OUT.
• the foregoing second reset control unit includes:
• the fourteenth thin film transistor T14 has a gate connected to the first reset signal input terminal RESET, a source connected to the gate of the thirteenth thin film transistor T13, and a drain connected to the second scan direction selection signal input terminal CLK'B;
• the fifteenth thin film transistor T15 has a gate connected to the input terminal INPUT, a source connected to the gate of the thirteenth thin film transistor T13, and a drain connected to the second scan direction selection signal input terminal CLK'B;
• the sixteenth thin film transistor T16 has a gate connected to the first scanning direction selection signal input terminal CLK, a source connected to the low level VSS, and a drain connected to the gate of the thirteenth thin film transistor T13.
• the structure of the shift register of the four drive signals (4-clock) having the shift register unit shown in FIG. 14 is as shown in FIG. 15; the forward drive timing is the same as that shown in FIG. 5, and the reverse drive is performed. The timing is the same as that shown in FIG. 6.
• the first scanning direction selection signal input terminal CLK', the input terminal INPUT is at a high level
• the second scanning direction selection signal input terminal CLK'B, and the first reset signal input terminal Reset are at a low level
• the fourteenth thin film transistor T14 is turned off, the fifteenth thin film transistor T15 and the sixteenth thin film transistor T16 are turned on, the gate of the thirteenth thin film transistor T13 is pulled low, and the thirteenth thin film transistor T13 is turned off;
• the input terminal INPUT and the first reset signal input terminal Reset are at a low level, (the first scan direction selection signal input terminal CLK', and the second scan direction selection signal input terminal CLK'B are high level or If the low level is OK, the fourteenth thin film transistor T14 and the fifteenth thin film transistor T15 are turned off (the sixteenth thin film transistor T16 can be turned on or off), and the gate of the thirteenth thin film transistor T13 is kept low. Flat, that is, the thirteenth thin film transistor T13 is kept off;
• the second scan direction selection signal input terminal CLK'B, the first reset signal input terminal Reset is at a high level, the first scan direction selection signal input terminal CLK', and the input terminal INPUT are at a low level, then
• the fourteenth thin film transistor T14 is turned on, the fifteenth thin film transistor T15 and the sixteenth thin film transistor T16 are turned off, and the gate of the thirteenth thin film transistor T13 is turned to a high level, that is, the thirteenth thin film transistor T13 is turned on, and the output is Terminal OUT reset;
• the input terminal INPUT and the first reset signal input terminal Reset are kept at a low level, that is, the fourteenth thin film transistor T14 is turned off, and the fifteenth thin film transistor T15 is turned off; the first scan direction selection signal input terminal CLK
• the sixteenth thin film transistor T16 is turned on, and the gate of the thirteenth thin film transistor T13 is pulled low, the thirteenth thin film transistor T13 is kept turned off, thereby reducing the bias of the thirteenth thin film transistor T13.
• the applied voltage is beneficial to extend the working life of the thirteenth thin film transistor T13, that is, the reset reliability of the shift register.
• Reverse scan is similar to forward scan, mainly because the drive signal needs to be changed.
• the foregoing second reset control unit may further include:
• the seventeenth thin film transistor T17 has a gate connected to the first reset signal input terminal RESET, a source connected to the gate of the thirteenth thin film transistor T13, and a drain connected to the second scan direction selection signal input end.
• the eighteenth thin film transistor T18 has a gate connected to the input terminal INPUT, a source connected to the gate of the thirteenth thin film transistor T13, and a drain connected to the second scan direction selection signal input terminal CLK'B;
• the nineteenth thin film transistor T19 has a gate connected to the second reset signal input terminal RESET2, a source connected to the low level VSS, and a drain connected to the gate of the thirteenth thin film transistor T13;
• the twentieth thin film transistor T20 has a gate connected to the third reset signal input terminal RESET3, a source connected to the low level VSS, and a drain connected to the gate of the thirteenth thin film transistor T13.
• the structure of the shift register of the four drive signals (4-clock) having the shift register unit shown in FIG. 16 is as shown in FIG. 17; the forward drive timing is the same as that shown in FIG. The timing is the same as that shown in FIG. 6.
• the shift register unit 16 has an advantage over the shift register unit shown in FIG. 3 in that the stability is better; and the shift register unit shown in FIG. 7 has the advantage of reducing the thin film transistor directly used for resetting the output terminal OUT, The area required for the shift register unit can be effectively reduced (since the thin film transistor directly used for resetting the output terminal OUT is large in size).
• the input terminal INPUT, the first reset signal input terminal Reset, the third reset signal input terminal Reset3 are at a low level, and the second reset signal input terminal Reset2 is at a high level, then the seventeenth thin film transistor T17, The eighteenth thin film transistor ⁇ 18, the twentieth thin film transistor ⁇ 20 is turned off, the nineteenth thin film transistor T19 is turned on, the thirteenth thin film transistor T13 gate is pulled low, and the thirteenth thin film transistor T13 is turned off;
• the input terminal INPUT is high, the second scan direction selection signal input terminal CLK, B, the first reset signal input terminal Reset, the second reset signal input terminal Reset2, and the third reset signal input terminal Reset3 are low.
• the seventeenth thin film transistor T17, the nineteenth thin film transistor T19, and the twentieth thin film transistor T20 are turned off, and although the eighteenth thin film transistor T18 is turned on, the gate of the thirteenth thin film transistor T13 remains low. , the thirteenth thin film transistor T13 is turned off;
• the input terminal INPUT, the first reset signal input terminal Reset, the second reset signal input terminal Reset2, and the third reset signal input terminal Reset3 are at a low level, (the second scan direction selection signal input terminal CLK'B is regardless of Whether it is a high level or a low level, the seventeenth thin film transistor T17, the eighteenth thin film transistor ⁇ 18, the nineteenth thin film transistor ⁇ 19, the twentieth thin film transistor ⁇ 20 are turned off, and the thirteenth thin film transistor T13 is gated. Extremely low, the thirteenth thin film transistor T13 remains cut off;
• the second scan direction selection signal input terminal CLK'B, the first reset signal input terminal Reset is at a high level, the input terminal INPUT, the second reset signal input terminal Reset2, and the third reset signal input terminal Reset3 are low.
• the seventeenth thin film transistor T17 is turned on, the eighteenth thin film transistor T18, the nineteenth thin film transistor ⁇ 19, and the twentieth thin film transistor ⁇ 20 are turned off, and the gate of the thirteenth thin film transistor T13 is turned to a high level. That is, the thirteenth thin film transistor T13 is turned on, and the output terminal OUT is reset;
• the input terminal INPUT, the first reset signal input terminal Reset, the second reset signal input terminal Reset2 are at a low level, and the third reset signal input terminal Reset3 is at a high level, then
• the seventeenth thin film transistor T17, the eighteenth thin film transistor ⁇ 18, the nineteenth thin film transistor T19 are turned off, the twentieth thin film transistor ⁇ 20 is turned on, the gate of the thirteenth thin film transistor T13 is pulled low, and the thirteenth thin film transistor T13 is turned off. , completing resetting of the thirteenth thin film transistor T13;
• the input terminal INPUT, the first reset signal input terminal Reset, the second reset signal input terminal Reset2, and the third reset signal input terminal Reset3 are directly maintained at a low level, that is, the seventeenth thin film transistor T17, tenth
• the eight thin film transistor ⁇ 18, the nineteenth thin film transistor ⁇ 19, and the twentieth thin film transistor ⁇ 20 are kept off; then the gate voltage of the thirteenth thin film transistor T13 is kept at a low level, thereby reducing the bias effect of the thirteenth thin film transistor T13.
• the voltage is beneficial to extend the operational life of the thirteenth thin film transistor T13, that is, the reset reliability of the shift register.
• the shift register of the shift register unit of Fig. 3, Fig. 7 (or the same or similar interface) can be used in the structure shown in Fig. 4 or in addition to the structure shown in Fig. Its derived structure.
• Figure 8 shows a direction selection signal clk5 with respect to Figure 4, as shown in Figure 8.
• the driving timing of this structure is shown in FIGS. 9 and 10.
• the specific driving process is similar to that of Figure 3.
• the shift register drive signal CLK is swapped with the CLKB timing, and the direction select signal clk3 is interchanged with clk5.
• the timing is as shown in FIGS. 9 and 10.
• the advantage is that the number of cells connected to each selection signal clkx is reduced (from the original n/2 to n/3), which can reduce the power consumption of the storage capacitor; the other is to reduce the shift register unit does not work.
• the advantage is that the number of cells connected by each scanning direction selection signal clkx is reduced (from the original n/2 to n/4), which can reduce the power consumption of the storage capacitor; the other is to reduce the shift register unit.
• the duty ratio of the direction selection signal is not working (from the original 50% to 25%), the possibility of accidental opening can be effectively reduced, thereby improving reliability.
• an embodiment of the present invention further provides a display, including any one of the foregoing shift registers provided by the embodiments of the present invention.

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• 2012
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