WO2013058002A1 - 光検出装置 - Google Patents
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- WO2013058002A1 WO2013058002A1 PCT/JP2012/069728 JP2012069728W WO2013058002A1 WO 2013058002 A1 WO2013058002 A1 WO 2013058002A1 JP 2012069728 W JP2012069728 W JP 2012069728W WO 2013058002 A1 WO2013058002 A1 WO 2013058002A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/02002—Arrangements for conducting electric current to or from the device in operations
- H01L31/02005—Arrangements for conducting electric current to or from the device in operations for device characterised by at least one potential jump barrier or surface barrier
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/1443—Devices controlled by radiation with at least one potential jump or surface barrier
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/1446—Devices controlled by radiation in a repetitive configuration
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
- H01L27/14605—Structural or functional details relating to the position of the pixel elements, e.g. smaller pixel elements in the center of the imager compared to pixel elements at the periphery
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/20—Resistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0232—Optical elements or arrangements associated with the device
- H01L31/02322—Optical elements or arrangements associated with the device comprising luminescent members, e.g. fluorescent sheets upon the device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by at least one potential-jump barrier or surface barrier, e.g. phototransistors
- H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
- H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier
- H01L31/107—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier working in avalanche mode, e.g. avalanche photodiode
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Definitions
- the present invention relates to a photodetection device.
- a photodiode array including a plurality of avalanche photodiodes operating in Geiger mode and a quenching resistor connected in series to each avalanche photodiode is known (for example, , See Patent Document 1).
- this photodiode array when the avalanche photodiode constituting the pixel detects photons and performs Geiger discharge, a pulsed signal is obtained by the action of a quenching resistor connected to the avalanche photodiode.
- Each avalanche photodiode counts photons. Therefore, even when a plurality of photons are incident at the same timing, the number of incident photons is determined according to the output charge amount or signal intensity of the total output pulse.
- a semiconductor photodetection element having a plurality of channels with the photodiode array described above as one channel may be used.
- the distance of wiring for guiding a signal output from each channel (hereinafter referred to as “wiring distance”) may differ between channels. If they are different from each other, the time resolution differs between channels due to the influence of the resistance and capacitance of the wiring.
- An object of the present invention is to provide a photodetection device capable of further improving the time resolution while increasing the area.
- the present invention relates to a photodetection device, a semiconductor photodetection element having a semiconductor substrate including first and second main surfaces facing each other, a second photodetection element disposed opposite to the semiconductor photodetection element, A mounting substrate having a third main surface facing the surface and a fourth main surface facing the third main surface, wherein the semiconductor photodetecting element is formed in the semiconductor substrate while operating in Geiger mode
- a plurality of channels with a photodiode array including a signal line arranged on the first main surface side of each channel as a single channel, and a mounting substrate for each channel
- a plurality of corresponding first electrodes are arranged on the third main surface side, and a signal processing unit that is electrically connected to the plurality of first electrode
- the semiconductor photodetecting element has a plurality of channels with the photodiode array described above as one channel. Thereby, it is possible to realize a photodetection device with a large area.
- a through electrode that is electrically connected to the signal line and penetrates from the first main surface side to the second main surface side is formed for each channel on the semiconductor substrate of the semiconductor photodetection device.
- the through electrode and the first electrode of the mounting substrate are electrically connected via the bump electrode.
- a glass substrate which is disposed on the first main surface side of the semiconductor substrate and has a fifth main surface facing the first main surface of the semiconductor substrate and a sixth main surface facing the fifth main surface.
- the side surface of the semiconductor substrate and the side surface of the glass substrate may be flush with each other.
- the mechanical strength of the semiconductor substrate can be increased by the glass substrate. Since the side surface of the semiconductor substrate and the side surface of the glass substrate are flush with each other, dead space can be reduced.
- the sixth main surface of the glass substrate may be flat.
- the scintillator can be installed on the glass substrate very easily.
- the through electrode may be located in the central region of the channel. In this case, in each channel, the wiring distance from the avalanche photodiode to the through electrode can be shortened.
- the through electrode may be located in a region between each channel. In this case, it is possible to prevent a decrease in the aperture ratio in each channel.
- the semiconductor photodetecting element may further include a second electrode disposed on the first main surface side of the semiconductor substrate and connecting the signal line and the through electrode.
- the signal line and the through electrode can be reliably electrically connected.
- FIG. 1 is a schematic perspective view showing a photodetection device according to an embodiment of the present invention.
- FIG. 2 is a diagram for explaining a cross-sectional configuration of the photodetecting device according to the present embodiment.
- FIG. 3 is a schematic plan view of the semiconductor photodetecting element.
- FIG. 4 is a schematic plan view of the semiconductor photodetecting element.
- FIG. 5 is a schematic plan view of the photodiode array.
- FIG. 6 is a circuit diagram of the photodetector.
- FIG. 7 is a schematic plan view of the mounting substrate.
- FIG. 8 is a diagram for explaining a manufacturing process of the photodetecting device according to the present embodiment.
- FIG. 9 is a diagram for explaining a manufacturing process of the photodetecting device according to the present embodiment.
- FIG. 9 is a diagram for explaining a manufacturing process of the photodetecting device according to the present embodiment.
- FIG. 10 is a diagram for explaining a manufacturing process of the photodetecting device according to the present embodiment.
- FIG. 11 is a diagram for explaining a manufacturing process of the photodetecting device according to the present embodiment.
- FIG. 12 is a diagram for explaining a manufacturing process of the photodetecting device according to the present embodiment.
- FIG. 13 is a diagram for explaining a manufacturing process of the photodetecting device according to the present embodiment.
- FIG. 14 is a diagram for explaining a manufacturing process of the photodetecting device according to the present embodiment.
- FIG. 15 is a diagram for explaining a manufacturing process of the photodetecting device according to the present embodiment.
- FIG. 16 is a diagram for explaining a manufacturing process of the photodetecting device according to the present embodiment.
- FIG. 17 is a diagram for explaining a manufacturing process of the photodetecting device according to the present embodiment.
- FIG. 18 is a schematic plan view of the semiconductor photodetector element.
- FIG. 19 is a schematic plan view of the photodiode array.
- FIG. 20 is a diagram for explaining a cross-sectional configuration of a photodetection device according to a modification of the present embodiment.
- FIG. 21 is a schematic plan view of the semiconductor photodetector element.
- FIG. 1 is a schematic perspective view showing a photodetecting device according to the present embodiment.
- FIG. 2 is a diagram for explaining a cross-sectional configuration of the photodetecting device according to the present embodiment.
- 3 and 4 are schematic plan views of the semiconductor photodetector element.
- FIG. 5 is a schematic plan view of the photodiode array.
- FIG. 6 is a circuit diagram of the photodetector.
- FIG. 7 is a schematic plan view of the mounting substrate.
- the photodetecting device 1 includes a semiconductor photodetecting element 10, a mounting substrate 20, and a glass substrate 30, as shown in FIGS.
- the mounting substrate 20 is disposed to face the semiconductor light detection element 10.
- the glass substrate 30 is disposed to face the semiconductor light detection element 10.
- the semiconductor light detection element 10 is disposed between the mounting substrate 20 and the glass substrate 30.
- the semiconductor photodetecting element 10 has a plurality of channels, that is, a plurality of photodiode arrays PDA, with one photodiode array PDA as one channel.
- the semiconductor photodetector 10 has a semiconductor substrate 1N that has a rectangular shape in plan view.
- the semiconductor substrate 1N includes a main surface 1Na and a main surface 1Nb facing each other.
- the semiconductor substrate 1N is an N-type (first conductivity type) semiconductor substrate made of Si.
- Each photodiode array PDA includes a plurality of avalanche photodiodes APD formed on the semiconductor substrate 1N. As shown in FIG. 5, a quenching resistor R1 is connected in series to each avalanche photodiode APD. One avalanche photodiode APD constitutes one pixel in each photodiode array PDA. The avalanche photodiodes APD are all connected in parallel with being connected in series with the quenching resistor R1, and a reverse bias voltage is applied from the power supply. The output current from the avalanche photodiode APD is detected by a signal processing unit SP described later.
- Each avalanche photodiode APD has a P-type (second conductivity type) first semiconductor region 1PA and a P-type (second conductivity type) second semiconductor region 1PB.
- the first semiconductor region 1PA is formed on the main surface 1Na side of the semiconductor substrate 1N.
- the second semiconductor region 1PB is formed in the first semiconductor region 1PA and has a higher impurity concentration than the first semiconductor region 1PA.
- the planar shape of the second semiconductor region 1PB is, for example, a polygon (in this embodiment, a quadrangle).
- the depth of the first semiconductor region 1PA is deeper than that of the second semiconductor region 1PB.
- the semiconductor substrate 1N has an N-type (first conductivity type) semiconductor region 1PC.
- the semiconductor region 1PC is formed on the main surface 1Na side of the semiconductor substrate 1N.
- the semiconductor region 1PC prevents a PN junction formed between the N-type semiconductor substrate 1N and the P-type first semiconductor region 1PA from being exposed to a through-hole TH in which a later-described through-electrode TE is disposed.
- the semiconductor region 1PC is formed at a position corresponding to the through hole TH (through electrode TE).
- Each avalanche photodiode APD has an electrode E1 as shown in FIG. Each electrode E1 is arranged on the main surface 1Na side of the semiconductor substrate 1N. The electrode E1 is electrically connected to the second semiconductor region 1PB. Each avalanche photodiode APD has an electrode (not shown) electrically connected to the semiconductor substrate 1N. The electrodes are respectively arranged on the main surface 1Nb side of the semiconductor substrate 1N. The first semiconductor region 1PA is electrically connected to the electrode E1 through the second semiconductor region 1PB.
- the photodiode array PDA has a signal line TL and an electrode E3 arranged on the semiconductor substrate 1N outside the second semiconductor region 1PB via the insulating layer L1.
- the signal line TL and the electrode E3 are disposed on the main surface 1Na side of the semiconductor substrate 1N.
- the electrode E3 is located in the central region of each channel (photodiode array PDA).
- the signal line TL includes a plurality of signal lines TL1 and a plurality of signal lines TL2.
- Each signal line TL1 extends in the Y-axis direction between adjacent avalanche photodiodes APD in plan view.
- Each signal line TL2 extends in the X-axis direction between adjacent avalanche photodiodes APD to electrically connect the plurality of signal lines TL1.
- the signal line TL2 is connected to the electrode E3.
- the signal line TL1 is electrically connected to the electrode E3 via the signal line TL2, except for the signal line TL1, which is not directly connected to the electrode E3.
- the photodiode array PDA has a quenching resistor R1 for each individual avalanche photodiode APD.
- Each quenching resistor R1 is disposed on the semiconductor substrate 1N outside the second semiconductor region 1PB via an insulating layer L1.
- Quenching resistor R1 is arranged on the main surface 1Na side of semiconductor substrate 1N.
- the quenching resistor R1 has one end connected to the electrode E1 and the other end connected to the signal line TL1. 3 and 5, the description of the insulating layers L1 and L3 shown in FIG. 2 is omitted for clarity of the structure.
- Each avalanche photodiode APD (region immediately below the first semiconductor region 1PA) is connected to the signal line TL1 via the quenching resistor R1.
- a plurality of avalanche photodiodes APD are connected to one signal line TL1 via quenching resistors R1, respectively.
- An insulating layer L3 is disposed on the main surface 1Na side of the semiconductor substrate 1N.
- the insulating layer L3 is formed so as to cover the electrodes E1 and E3, the quenching resistor R1, and the signal line TL.
- Each photodiode array PDA includes a through electrode TE.
- the through electrode TE is provided for each individual photodiode array PDA, that is, for each individual channel.
- the through electrode TE is formed so as to penetrate the semiconductor substrate 1N from the main surface 1Na side to the main surface 1Nb side.
- the through electrode TE is disposed in the through hole TH that penetrates the semiconductor substrate 1N.
- the insulating layer L2 is also formed in the through hole TH. Therefore, the through electrode TE is disposed in the through hole TH via the insulating layer L2.
- the through electrode TE has one end connected to the electrode E3.
- the electrode E3 connects the signal line TL and the through electrode TE.
- the quenching resistor R1 is electrically connected to the through electrode TE through the signal line TL and the electrode E3.
- the quenching resistor R1 has a higher resistivity than the electrode E1 to which the quenching resistor R1 is connected.
- Quenching resistor R1 is made of polysilicon, for example.
- a CVD (Chemical Vapor Deposition) method can be used as a method of forming the quenching resistor R1.
- the electrodes E1, E3 and the through electrode TE are made of a metal such as aluminum.
- the semiconductor substrate is made of Si, AuGe / Ni or the like is often used as the electrode material in addition to aluminum.
- a sputtering method can be used as a method for forming the electrodes E1, E3 and the through electrode TE.
- a Group 3 element such as B is used as the P-type impurity, and similarly, a Group 5 element such as N, P, or As is used as the N-type impurity. Even if N-type and P-type, which are semiconductor conductivity types, are replaced with each other to form an element, the element can function.
- a diffusion method or an ion implantation method can be used as a method for adding these impurities.
- SiO 2 or SiN can be used as a material of the insulating layers L1, L2, and L3, SiO 2 or SiN.
- a method for forming the insulating layer L1, L2, L3, when the insulating layer L1, L2, L3 is made of SiO 2 may be used a thermal oxidation method or a sputtering method.
- an avalanche photodiode APD is formed by forming a PN junction between the N-type semiconductor substrate 1N and the P-type first semiconductor region 1PA.
- the semiconductor substrate 1N is electrically connected to an electrode (not shown) formed on the back surface of the substrate 1N, and the first semiconductor region 1PA is connected to the electrode E1 through the second semiconductor region 1PB.
- the quenching resistor R1 is connected in series with the avalanche photodiode APD (see FIG. 6).
- each avalanche photodiode APD is operated in the Geiger mode.
- a reverse voltage (reverse bias voltage) larger than the breakdown voltage of the avalanche photodiode APD is applied between the anode and the cathode of the avalanche photodiode APD.
- a ( ⁇ ) potential V1 is applied to the anode, and a (+) potential V2 is applied to the cathode.
- the polarities of these potentials are relative, and one of the potentials can be a ground potential.
- the anode is a P-type first semiconductor region 1PA
- the cathode is an N-type semiconductor substrate 1N.
- photoelectric conversion is performed inside the substrate to generate photoelectrons.
- Avalanche multiplication is performed in a region near the PN junction interface of the first semiconductor region 1PA, and the amplified electron group flows toward an electrode formed on the back surface of the semiconductor substrate 1N. That is, when light (photon) is incident on any pixel (avalanche photodiode APD) of the photodiode array PDA, it is multiplied and extracted as a signal from the electrode E3 (through electrode TE).
- the other end of the quenching resistor R1 connected to each avalanche photodiode APD is electrically connected to a common signal line TL along the surface of the semiconductor substrate 1N.
- the plurality of avalanche photodiodes APD operate in Geiger mode, and each avalanche photodiode APD is connected to a common signal line TL. For this reason, when photons simultaneously enter a plurality of avalanche photodiodes APD, the outputs of the plurality of avalanche photodiodes APD are all input to a common signal line TL, and as a whole, a high-intensity signal corresponding to the number of incident photons. It is measured. In the semiconductor photodetecting element 10, a signal is output for each channel (photodiode array PDA) through the corresponding through electrode TE.
- the mounting substrate 20 has a main surface 20a and a main surface 20b facing each other as shown in FIG.
- the mounting substrate 20 has a rectangular shape in plan view.
- Main surface 20a is opposed to main surface 1Nb of semiconductor substrate 1N.
- the mounting substrate 20 includes a plurality of electrodes E9 arranged on the main surface 20a side.
- the electrode E9 is disposed corresponding to the through electrode TE. That is, the electrode E9 is disposed on each region facing the through electrode TE on the main surface 20a.
- the electrode E9 is provided for each channel (photodiode array PDA).
- illustration of the bump electrodes described on the main surface 20 b side of the mounting substrate 20 is omitted.
- the through electrode TE and the electrode E9 are connected by a bump electrode BE.
- the electrode E3 is electrically connected to the electrode E9 via the penetration electrode TE and the bump electrode BE.
- the quenching resistor R1 is electrically connected to the electrode E9 via the signal line TL, the electrode E3, the through electrode TE, and the bump electrode BE.
- the electrode E9 is also made of a metal such as aluminum like the electrodes E1 and E3 and the through electrode TE. As an electrode material, AuGe / Ni or the like may be used in addition to aluminum.
- the bump electrode BE is made of, for example, solder.
- the bump electrode BE is formed on the through electrode TE through a UBM (Under Bump Metal) 40.
- the mounting substrate 20 has a signal processing unit SP.
- the signal processing unit SP is disposed on the main surface 20b side of the mounting substrate 20.
- the signal processing unit SP constitutes an ASIC (Application Specific Integrated Circuit).
- Each electrode E9 is electrically connected to the signal processing unit SP via a wiring (not shown) formed in the mounting substrate 20 and a bonding wire.
- the signal processing unit SP receives an output signal from each channel (photodiode array PDA), and the signal processing unit SP processes the output signal from each channel.
- the signal processing unit SP includes a CMOS circuit that converts an output signal from each channel into a digital pulse.
- a passivation film PF having openings formed at positions corresponding to the bump electrodes BE is disposed on the main surface 1Nb side of the semiconductor substrate 1N and the main surface 20a side of the mounting substrate 20.
- the passivation film PF is made of SiN, for example.
- a CVD method can be used as a method for forming the passivation film PF.
- the glass substrate 30 has a main surface 30a and a main surface 30b facing each other.
- the glass substrate 30 has a rectangular shape in plan view.
- Main surface 30a faces main surface 1Nb of semiconductor substrate 1N.
- the main surface 30b is flat. In the present embodiment, the main surface 30a is also flat.
- the glass substrate 30 and the semiconductor photodetecting element 10 are optically connected by an optical adhesive (not shown).
- the glass substrate 30 may be formed directly on the semiconductor photodetecting element 10.
- a scintillator is optically connected to the main surface 30b of the glass substrate 30 by an optical adhesive.
- the scintillation light from the scintillator passes through the glass substrate 30 and enters the semiconductor light detection element 10.
- the side surface 1Nc of the semiconductor substrate 1N and the side surface 30c of the glass substrate 30 are flush with each other as shown in FIG. In plan view, the outer edge of the semiconductor substrate 1N and the outer edge of the glass substrate 30 coincide.
- 8 to 17 are diagrams for explaining a manufacturing process of the photodetecting device according to the present embodiment.
- a portion corresponding to the semiconductor photodetecting element 10 that is, a portion corresponding to each channel (photodiode array PDA) (first semiconductor region 1PA, second semiconductor region 1PB, insulating layer L1, quenching resistor R1, electrode E1, A semiconductor substrate 1N on which E3 and a signal line TL) are formed is prepared (see FIG. 8).
- the semiconductor substrate 1N is prepared in the form of a semiconductor wafer in which a plurality of portions corresponding to the semiconductor photodetector 10 are formed.
- the insulating layer L3 is formed on the main surface 1Na side of the prepared semiconductor substrate 1N, and then the semiconductor substrate 1N is thinned from the main surface 1Nb side (see FIG. 9).
- Insulating layer L3 is made of SiO 2.
- the insulating layer L3 can be formed by a CVD method. As a method for thinning the semiconductor substrate 1N, a mechanical polishing method or a chemical polishing method can be used.
- Insulating layer L2 is formed on the main surface 1Nb side of the prepared semiconductor substrate 1N (see FIG. 10).
- Insulating layer L2 is made of SiO 2.
- a CVD method can be used as a method of forming the insulating layer L2.
- the region where the through hole TH is formed in the insulating layer L2 is removed (see FIG. 11).
- a dry etching method can be used as a method for removing the insulating layer L2.
- a through hole TH for arranging the through electrode TE is formed in the semiconductor substrate 1N (see FIG. 12).
- a method for forming the through hole TH a dry etching method and a wet etching method can be appropriately selected and applied.
- the alkali etching method is used as the wet etching method
- the insulating layer L1 functions as an etching stop layer.
- a part of the insulating layer L1 and the insulating layer L2 is removed to expose the electrode E3 (see FIG. 13).
- a dry etching method can be used as a method for removing the insulating layer L1 and the insulating layer L2.
- the through electrode TE is formed (see FIG. 14).
- the through electrode TE can be formed by sputtering.
- a passivation film PF having an opening formed at a position corresponding to the bump electrode BE is formed on the main surface 1Nb side of the semiconductor substrate 1N, and then the bump electrode BE is formed (see FIG. 15). Thereby, the semiconductor photodetection element 10 is obtained.
- the UBM 40 Prior to the formation of the bump electrode BE, the UBM 40 is formed in a region exposed from the passivation film PF in the through electrode TE.
- the UBM 40 is made of a material that is electrically and physically connected to the bump electrode BE.
- an electroless plating method can be used.
- a method for forming the bump electrode BE a method of mounting a solder ball or a printing method can be used.
- the glass substrate 30 is bonded to the semiconductor photodetector 10 through an optical adhesive (see FIG. 16). Thereby, the glass substrate 30 and the semiconductor light detection element 10 are optically connected.
- the glass substrate 30 is also prepared in the form of a glass substrate base material including a plurality of glass substrates 30. The step of bonding the glass substrate 30 and the semiconductor photodetecting element 10 may be performed after forming the insulating layer L3 on the semiconductor substrate 1N.
- the laminated body composed of the glass substrate 30 (glass substrate base material) and the semiconductor photodetector 10 (semiconductor wafer) is cut by dicing. Thereby, the side surface 1Nc of the semiconductor substrate 1N and the side surface 30c of the glass substrate 30 are flush with each other.
- the semiconductor photodetecting element 10 with the glass substrate 30 disposed opposite to the mounting substrate 20 separately prepared is bump-connected (see FIG. 17). Through these processes, the photodetection device 1 is obtained.
- a bump electrode BE is formed on the mounting substrate 20 on the main surface 20a side at a position corresponding to the electrode E9.
- the semiconductor photodetector 10 since the semiconductor photodetector 10 has a plurality of channels with the photodiode array PDA as one channel, the photodetector 1 with a large area is realized. can do.
- a through electrode TE that is electrically connected to the signal line TL and penetrates from the main surface 1Na side to the main surface 1Nb side is formed on the semiconductor substrate 1N of the semiconductor photodetection element 10 for each channel.
- the through electrode TE of the light detection element 10 and the electrode E9 of the mounting substrate 20 are electrically connected via the bump electrode BE.
- the photodetecting device 1 includes a glass substrate 30 disposed on the main surface 1Na side of the semiconductor substrate 1N. Thereby, the mechanical strength of the semiconductor substrate 1 ⁇ / b> N can be increased by the glass substrate 30.
- the side surface 1Nc of the semiconductor substrate 1N and the side surface 30c of the glass substrate 30 are flush with each other. Thereby, dead space can be reduced.
- the main surface 30b of the glass substrate 30 is flat. Thereby, installation of the scintillator to the glass substrate 30 can be performed very easily.
- the through electrode TE is located in the central region of each channel. Thereby, in each channel, the wiring distance from each avalanche photodiode APD to the penetration electrode TE can be shortened.
- the semiconductor photodetecting element 10 is disposed on the main surface 1Na side of the semiconductor substrate 1N and includes an electrode E3 that connects the signal line TL and the through electrode TE. Thereby, the signal line TL and the through electrode TE can be reliably electrically connected.
- the through electrode TE may be located in a region between each channel (photodiode array PDA) as shown in FIGS. In this case, it is possible to prevent a decrease in the aperture ratio in each channel. 18 and 19, the insulating layer L1 shown in FIG. 2 is omitted for clarity of the structure.
- the bump electrode BE may be arranged outside the through hole TH as shown in FIGS.
- a plurality of bump electrodes (four bump electrodes in this example) BE are formed for one through electrode TE.
- the bump electrode BE is disposed on an electrode portion that is continuous with the through electrode TE and is disposed on the main surface 1Nb side of the semiconductor substrate 1N.
- the description of the passivation film PF shown in FIG. 2 is omitted for clarity of the structure.
- the shapes of the first and second semiconductor regions 1PB and 1PB are not limited to the shapes described above, but may be other shapes (for example, a circular shape).
- the number (number of rows and number of columns) and arrangement of the avalanche photodiode APD (second semiconductor region 1PB) are not limited to those described above. Further, the number and arrangement of the channels (photodiode arrays PDA) are not limited to those described above.
- the present invention can be used for a light detection device that detects weak light.
- SYMBOLS 1 Photodetection apparatus, 1N ... Semiconductor substrate, 1Na, 1Nb ... Main surface, 1Nc ... Side surface, 1PA ... First semiconductor region, 1PB ... Second semiconductor region, 10 ... Semiconductor photodetection element, 20 ... Mounting substrate, 20a, 20b ... main surface, 30 ... glass substrate, 30a, 30b ... main surface, 30c ... side surface, APD ... avalanche photodiode, BE ... bump electrode, E1, E3, E9 ... electrode, PDA ... photodiode array, R1 ... quenching Resistance, SP ... signal processing unit, TE ... through electrode, TL ... signal line.
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Abstract
Description
Claims (6)
- 光検出装置であって、
互いに対向する第一及び第二主面を含む半導体基板を有する半導体光検出素子と、
前記半導体光検出素子に対向配置されると共に、前記半導体基板の前記第二主面と対向する第三主面と該第三主面と対向する第四主面とを有する搭載基板と、を備え、
前記半導体光検出素子は、ガイガーモードで動作すると共に前記半導体基板内に形成された複数のアバランシェフォトダイオードと、それぞれの前記アバランシェフォトダイオードに対して直列に接続されると共に前記半導体基板の第一主面側に配置されたクエンチング抵抗と、前記クエンチング抵抗が並列に接続されると共に前記半導体基板の前記第一主面側に配置された信号線と、を含むフォトダイオードアレイを一つのチャンネルとして、複数の前記チャンネルを有し、
前記搭載基板は、前記チャンネル毎に対応した複数の第一電極が前記第三主面側に配置されると共に、前記複数の第一電極と電気的に接続され且つ各前記チャンネルからの出力信号を処理する信号処理部が前記第四主面側に配置されており、
前記半導体基板には、前記チャンネル毎に、前記信号線と電気的に接続され且つ前記第一主面側から前記第二主面側まで貫通した貫通電極が形成され、
前記貫通電極と、該貫通電極に対応する前記第一電極と、がバンプ電極を介して電気的に接続されている。 - 請求項1に記載の光検出装置であって、
前記半導体基板の前記第一主面側に配置され、前記半導体基板の前記第一主面と対向する第五主面と該第五主面と対向する第六主面とを有するガラス基板を更に備え、
前記半導体基板の側面と前記ガラス基板の側面とが面一とされている。 - 請求項2に記載の光検出装置であって、
前記ガラス基板の前記第六主面が平坦である。 - 請求項1~3のいずれか一項に記載の光検出装置であって、
前記貫通電極が、前記チャンネルの中央領域に位置している。 - 請求項1~3のいずれか一項に記載の光検出装置であって、
前記貫通電極が、各前記チャンネル間の領域に位置している。 - 請求項1~5のいずれか一項に記載の光検出装置であって、
前記半導体光検出素子は、前記半導体基板の前記第一主面側に配置され、前記信号線と前記貫通電極とを接続する第二電極を更に含んでいる。
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US14/352,398 US8969990B2 (en) | 2011-10-21 | 2012-08-02 | Light detection device |
DE112012004383.9T DE112012004383T5 (de) | 2011-10-21 | 2012-08-02 | Lichterfassungsvorrichtung |
CN201280051795.8A CN103907206B (zh) | 2011-10-21 | 2012-08-02 | 光检测装置 |
US14/605,120 US9425224B2 (en) | 2011-10-21 | 2015-01-26 | Light detection device |
US15/207,569 US9825071B2 (en) | 2011-10-21 | 2016-07-12 | Light detection device |
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US14/352,398 A-371-Of-International US8969990B2 (en) | 2011-10-21 | 2012-08-02 | Light detection device |
US14/605,120 Continuation US9425224B2 (en) | 2011-10-21 | 2015-01-26 | Light detection device |
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JP (1) | JP5791461B2 (ja) |
CN (3) | CN103907206B (ja) |
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US9825071B2 (en) | 2017-11-21 |
DE112012004383T5 (de) | 2014-07-10 |
CN105679777A (zh) | 2016-06-15 |
US9425224B2 (en) | 2016-08-23 |
TWI569431B (zh) | 2017-02-01 |
TW201635504A (zh) | 2016-10-01 |
TW201717369A (zh) | 2017-05-16 |
JP5791461B2 (ja) | 2015-10-07 |
US20150137298A1 (en) | 2015-05-21 |
US20140327100A1 (en) | 2014-11-06 |
CN103907206B (zh) | 2016-02-24 |
DE202012013199U1 (de) | 2015-05-15 |
US8969990B2 (en) | 2015-03-03 |
CN103907206A (zh) | 2014-07-02 |
US20160322405A1 (en) | 2016-11-03 |
JP2013089917A (ja) | 2013-05-13 |
CN105679841A (zh) | 2016-06-15 |
CN105679777B (zh) | 2018-11-27 |
TWI549270B (zh) | 2016-09-11 |
CN105679841B (zh) | 2017-12-08 |
TWI607553B (zh) | 2017-12-01 |
TW201318153A (zh) | 2013-05-01 |
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