WO2012157287A1 - 半導体チップの製造方法 - Google Patents
半導体チップの製造方法 Download PDFInfo
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- WO2012157287A1 WO2012157287A1 PCT/JP2012/003277 JP2012003277W WO2012157287A1 WO 2012157287 A1 WO2012157287 A1 WO 2012157287A1 JP 2012003277 W JP2012003277 W JP 2012003277W WO 2012157287 A1 WO2012157287 A1 WO 2012157287A1
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
- H01J37/32082—Radio frequency generated discharge
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
- H01L21/31138—Etching organic layers by chemical means by dry-etching
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- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
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- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
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- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
- H01L2221/68386—Separation by peeling
Definitions
- the present invention relates to a semiconductor chip manufacturing method for dividing a semiconductor wafer into individual pieces.
- Patent Document 1 discloses mechanical dicing by a DBG (Dicing Before Grinding) method.
- a groove is formed by a blade from an element formation surface (front surface) of a semiconductor wafer, and then a protective tape is attached to the surface.
- the surface (back surface) opposite to the front surface of the semiconductor wafer is ground until reaching the groove, and is divided into individual semiconductor chips.
- the DGB method using a dicer has the following problems.
- the thickness of the blade at least about 40 to 50 ⁇ m
- Patent Document 2 discloses that a resist pattern is formed on the back surface of a semiconductor wafer after grinding for thinning, and the semiconductor wafer is divided into individual pieces by performing plasma etching from the back surface side.
- Patent Document 3 discloses that both a step of forming a resist pattern on the front surface side and performing plasma etching and a step of forming a resist pattern on the back surface side and performing plasma etching are performed. It is disclosed that a semiconductor wafer is divided into pieces by performing plasma etching.
- Patent Document 4 discloses that a resist pattern is formed on the front surface so as to cover an element formation region, a protective tape is attached to the back surface, a semiconductor wafer is divided from the front surface side with a dicer, and is separated into pieces. It is disclosed that the cut surface is modified by plasma treatment from the surface side.
- JP 2002-100588 A (FIG. 3) JP 2004-172364 A (FIG. 5) Japanese Patent Laying-Open No. 2004-95952 (FIGS. 3 to 6) JP-A-7-201784 (FIGS. 1 and 2)
- the semiconductor chip manufacturing method for dividing the semiconductor wafer into individual pieces in addition to the chip yield per chip, reduction of chipping, and handling properties, the number of times of attaching the protective tape is small.
- the number of times of attaching the protective tape is small.
- There are various demands such as a small number of photolithography processes for forming a resist pattern.
- the above-described known DBG method and various semiconductor dicing methods using plasma dicing cannot satisfy all of these requirements.
- An object of the present invention is to provide a method of manufacturing a semiconductor chip having various characteristics including chip yield per semiconductor wafer, reduction of chipping, and handling properties.
- the present invention provides a semiconductor wafer comprising a first surface on which a plurality of semiconductor element portions defined by divided regions are formed on an insulating film, and a second surface opposite to the first surface.
- a method of manufacturing a semiconductor chip wherein a semiconductor chip is manufactured by dividing each semiconductor element portion, wherein a mask that covers the semiconductor element portion but exposes the divided region is formed on the first surface;
- a first plasma dicing step of removing the insulating film in the divided regions exposed from the mask by plasma irradiation from the first surface; and a protective tape on the first surface after the first plasma dicing step Pasting the protective tape, grinding the second surface to thin the semiconductor wafer, and pasting the holding tape with a frame on the second surface after the grinding Process Removing the protective tape from the first surface after applying the holding tape; and removing the protective tape from the mask on the semiconductor wafer by plasma irradiation from the first surface after removing the protective tape.
- a portion of the exposed divided region is removed, and the semiconductor wafer is
- the semiconductor wafer is divided into a plurality of semiconductor chips by the first and second plasma dicing processes, and mechanical dicing using a dicer is not performed. Chip yield can be improved. Moreover, since it is separated into individual semiconductor chips in a state of being attached to a holding tape with a frame, chipping due to interference between adjacent semiconductor chips can be prevented. Further, in the state where the second surface is affixed to the protective tape after grinding, only the insulating film in the part of the divided region is removed and not separated into pieces, so that the handling property is excellent.
- a process can be simplified in the point that the process of sticking and peeling of a protective tape is only once. Moreover, the process can be simplified in that the mask formed on the first surface is used for both the first and second plasma dicing, and the mask formation and removal processes are performed only once. Furthermore, since the insulating film (for example, SiO 2 ) formed on the first surface is removed from the same first surface by plasma irradiation (first plasma dicing process), the insulating film can be removed reliably and at high speed. .
- the insulating film for example, SiO 2
- a step of removing the altered layer generated on the surface of the mask by the first plasma dicing step is performed by plasma irradiation from the first surface.
- the surface of the mask formed on the first surface is roughened and an altered layer is generated. By removing this altered layer, it is possible to prevent an excessive increase in the adhesive strength of the protective tape to the mask. As a result, when the protective tape is peeled off from the first surface after the holding film is applied to the second surface, damage to the mask such as peeling off of the mask from the first surface can be prevented.
- a step of removing the altered layer generated on the second surface by the grinding by plasma irradiation from the first surface is performed.
- the step of removing the mask removes the mask by plasma irradiation from the first surface.
- FIG. 1 A) to (E) are schematic cross-sectional views for explaining a method for manufacturing a semiconductor chip according to an embodiment of the present invention.
- FIG. 1 A) to (E) are schematic cross-sectional views for explaining a method for manufacturing a semiconductor chip according to an embodiment of the present invention.
- (A) And (B) is typical sectional drawing for demonstrating the manufacturing method of the semiconductor chip which concerns on embodiment of this invention. The typical sectional view of the semiconductor chip manufactured with the manufacturing method concerning the embodiment of the present invention.
- FIG. 1 to 3 are schematic sectional views showing a method for manufacturing a semiconductor chip according to an embodiment of the present invention.
- FIG. 4 shows a semiconductor chip 1 manufactured by this manufacturing method.
- the semiconductor chip 1 includes a die 2, an insulating film 3 formed on the die 2, and an IC part (semiconductor element part) 4 formed on the insulating film 3.
- the die 2 is made of Si or a Si-based material
- the insulating film 3 is made of SiO 2 .
- the material of the die 2 and the insulating film 3 is not limited to this.
- the insulating film 3 may be SiN, SiOC, Low-k, or the like.
- an insulating film 3 is formed on a surface (first surface) 5a of a semiconductor wafer 5, and a plurality of IC portions 4 are formed thereon. There is a gap (divided region 6) between adjacent IC portions 4 around each IC portion 4. Since the IC part 4 is not formed in the divided region 6, the insulating film 3 is exposed. In other words, the individual IC parts 4 are defined by the divided regions 6. On the other hand, no IC part is formed on the back surface (second surface) 5b opposite to the front surface 5a of the semiconductor wafer 5.
- a resist mask 7 is formed on the surface 5a of the semiconductor wafer 5 by photolithography so as to cover the individual IC portions 4 but expose the insulating film 3 in the divided regions 6 without covering them.
- FIG. 5 shows an example of a dry etching apparatus 11A used in an insulating film etching process and a resist surface treatment process described later.
- An antenna 13 as an upper electrode is disposed above the top of the chamber (vacuum vessel) 12 of the dry etching apparatus 11A.
- the antenna 13 is electrically connected to the first high frequency power supply unit 14A.
- a stage 16 on which the semiconductor wafer 5 is arranged is arranged on the bottom side of the processing chamber 15 in the chamber 12.
- the stage 16 also functions as a lower electrode and is electrically connected to the second high frequency power supply unit 14B.
- the gas introduction port 12a of the chamber 12 is connected to a CF 4 / Ar mixed gas source 17A and an oxygen gas source 17B, and the exhaust port 12b is connected to a vacuum exhaust unit 18 including a vacuum pump for evacuating the inside of the chamber 12. Has been.
- the insulating film etching step first placing the semiconductor wafer 5 on the stage 16, and CF 4 in the processing chamber 15 from the CF 4 / Ar mixed gas source 17A while evacuating by a vacuum exhaust unit 18 into the processing chamber 15 A mixed gas of Ar is supplied and maintained at a predetermined pressure. Thereafter, high frequency power is supplied from the first high frequency power supply unit 14 ⁇ / b> A to the antenna 13 to generate plasma 19 in the processing chamber 15 and irradiate the semiconductor wafer 5. At this time, a bias voltage is applied to the stage 16 from the second high frequency power supply unit 14B. The insulating film 3 in the divided region 6 exposed from the resist mask 7 is removed by the physicochemical action of radicals and ions in the plasma 19, and the Si or Si-based material that is the material of the semiconductor wafer 5 is exposed.
- a resist surface treatment step shown in FIG. the processing chamber 15 is evacuated by the evacuation unit 18 and oxygen gas is supplied from the oxygen gas source 17B into the processing chamber 15 to maintain a predetermined pressure.
- high frequency power is supplied from the first high frequency power supply unit 14 ⁇ / b> A to the antenna 13 to generate oxygen plasma 20 in the processing chamber 15 and irradiate the semiconductor wafer 5.
- the surface of the resist mask 7 is roughened due to the irradiation of the plasma 19 in the insulating film etching process (FIG. 1C), and an altered layer is generated.
- the oxygen plasma 20 is irradiated in the resist surface treatment process (FIG. 1D)
- the altered layer (roughness) on the surface of the resist mask 7 is removed by a physical action by the physicochemical action of radicals and ions in the oxygen plasma 20.
- BG tape (protective tape) 25 is affixed on the resist mask 7 in a step subsequent to the insulating film etching step (BG tape affixing step in FIG. 1E). Is removed from the resist mask 7 before the main etching step (FIG. 3A) for etching (BG tape peeling step in FIG. 2E). If the BG tape 25 is attached to the resist mask 7 with the altered layer existing on the surface of the resist mask 7, that is, with the surface roughness of the resist mask 7 being high, the BG with respect to the resist mask 7 is increased. The adhesive strength of the tape 25 becomes excessively high.
- a BG tape (protective tape) 25 for protection at the time of back surface grinding (Back Grind) is attached to the front side of the semiconductor wafer 5 (BG tape application) Process). That is, the BG tape 25 is attached to the surface of the resist mask 7 on the semiconductor wafer 5. Since the BG tape 25 is cut according to the outer shape of the semiconductor wafer 5 after being attached to the semiconductor wafer 5 or before being attached, the handling property of the semiconductor wafer 5 is not impaired.
- the back surface 5b of the semiconductor wafer 5 is ground by the grinding device 26 (back surface grinding step).
- the semiconductor wafer 5 is thinned to a predetermined thickness.
- FIG. 6 shows an example of a dry etching apparatus 11B used in the plasma stress relief process.
- This dry etching apparatus 11B has the above-described insulating film etching process (FIG. 1C) and resist surface treatment process (except for the point that only the SF 6 gas source 17C is connected to the gas inlet 12a of the chamber 12).
- This is the same as the dry etching apparatus 11A used in FIG. Therefore, among the elements shown in FIG. 6, the same or similar elements as those in FIG.
- the semiconductor wafer 5 is placed on the stage 16, and SF 6 gas is supplied into the processing chamber 15 from the SF 6 gas source 17 C while the processing chamber 15 is evacuated by the vacuum exhaust section 18. , Maintain at a predetermined pressure. Thereafter, high-frequency power is supplied from the first high-frequency power supply unit 14 ⁇ / b> A to the antenna 13 to generate SF 6 plasma 21 in the processing chamber 15 and irradiate the semiconductor wafer 5.
- the altered layer 5 c is removed from the back surface 5 b of the semiconductor wafer 5 by the physicochemical action of radicals and ions in the SF 6 plasma 21.
- the back surface 5b of the semiconductor wafer 5 is bonded to the holding tape 28 with the dicing ring (frame) 27 (holding tape applying process).
- the BG tape 25 is peeled from the semiconductor wafer 5, and the BG tape 25 is removed as shown in FIG. 2E (BG tape peeling step). That is, in this BG tape peeling step, the BG tape 25 is peeled off from the surface of the resist mask 7 and removed. As described above, the altered layer (roughness) generated on the surface of the resist mask 7 by the insulating film etching process (FIG. 1C) is removed by irradiation with the oxygen plasma 20 in the resist surface treatment process (FIG. 1D). Has been. And the excessive increase in the pasting strength of the BG tape 25 with respect to the resist mask 7 is suppressed by removing the deteriorated layer.
- FIG. 7 shows an example of a dry etching apparatus 11C used in a main etching process and an ashing process described later.
- this dry etching apparatus 11C an SF 6 gas source 17C and an oxygen gas source 17B are connected to the gas inlet 12a of the chamber 12.
- the dry etching apparatus 11C includes an annular cover 29 for protecting the portion of the holding tape 28 that protrudes from the semiconductor wafer 5 and the dicing ring 27 from plasma.
- the cover 29 is driven up and down by a drive mechanism (not shown).
- the cover 29 is in the lowered position (located in the vicinity of the upper side of the holding tape 28 and the dicing ring 27 and protects from the plasma) shown in FIG.
- the stage 16 can be moved to an ascending position (not shown) that enables loading and unloading.
- Other configurations of the dry etching apparatus 11C are the same as those of the dry etching apparatus 11A used in the above-described insulating film etching process (FIG. 1C) and resist surface treatment process (FIG. 1D). Therefore, among the elements shown in FIG. 7, the same or similar elements as those in FIG.
- the holding tape 28 semiconductor wafer 5
- the dicing ring 27 is placed on the stage 16 with the cover 29 in the raised position.
- the cover 29 moves to the lowered position.
- SF 6 gas is supplied into the processing chamber 15 from the SF 6 gas source 17C while the inside of the processing chamber 15 is evacuated by the evacuation unit 18, and maintained at a predetermined pressure.
- high-frequency power is supplied from the first high-frequency power supply unit 14 ⁇ / b> A to the antenna 13 to generate SF 6 plasma 21 in the processing chamber 15 and irradiate the semiconductor wafer 5.
- the semiconductor wafer 5 exposed in the divided region 6 is removed by the physicochemical action of radicals and ions in the SF 6 plasma 21.
- the main etching process is continued until the material constituting the semiconductor wafer 5 in the divided region 6 is removed from the front surface 5 a to the back surface 5 b and the semiconductor wafer 5 is divided into individual semiconductor chips 1.
- a portion of the holding tape 28 that protrudes from the semiconductor wafer 5 and the dicing ring 27 are covered with a cover 29 and protected from the SF 6 plasma 21.
- the ashing process shown in FIG. oxygen gas is supplied from the oxygen gas source 17B into the processing chamber 15 while the processing chamber 15 is evacuated to maintain a predetermined pressure.
- high frequency power is supplied from the first high frequency power supply unit 14 ⁇ / b> A to the antenna 13 to generate oxygen plasma 20 in the processing chamber 15 and irradiate the semiconductor wafer 5.
- the resist mask 7 is completely removed from the surface 5 a of the semiconductor wafer 5 by irradiation with the oxygen plasma 20.
- a portion of the holding tape 28 that protrudes from the semiconductor wafer 5 and the dicing ring 27 are covered with a cover 29 and protected from the oxygen plasma 20.
- the semiconductor chip 1 manufactured while being held on the holding tape 28 in the above process is taken out from the dry etching apparatus 11C and sent to a subsequent process.
- the semiconductor wafer 5 in a divided state (the semiconductor chip 1) Since the assembly) is held by the holding tape 28 with the dicing ring 27, handling in the subsequent process is easy.
- the semiconductor manufacturing method of this embodiment is particularly characterized in the following points.
- the semiconductor wafer 5 is divided into a plurality of semiconductor chips 1 by two plasma dicing processes, that is, an insulating film etching process (FIG. 1C) and a main etching process (FIG. 3A). That is, mechanical dicing using a dicer is not performed. Therefore, the chip yield per one semiconductor wafer 5 can be improved.
- ⁇ Chipping can be effectively suppressed. Since the semiconductor wafer 5 is separated into the semiconductor chips 1 in the insulating film etching process (FIG. 1C) and the main etching process (FIG. 3A), which are non-contact processing using plasma, chipping occurs. It can be greatly reduced. Further, since the semiconductor wafer 5 is separated into individual semiconductor chips 1 in a state of being attached to the holding tape 28 with the dicing ring 27 in the main etching step (FIG. 3A), the adjacent semiconductor chips 1 are separated. Chipping due to interference can be prevented.
- the semiconductor wafer 5 includes an automatic transfer mechanism and manual handling. A good handling property of 5 is ensured. Further, the division of the semiconductor wafer (the main etching process in FIG. 3A) is performed on the holding tape 28 with the dicing ring 27, and the handling after the division is performed through the holding tape 28 with the dicing ring 27. Good handling is ensured even after division.
- the semiconductor manufacturing method of this embodiment also has the following characteristics.
- the process for pasting the BG tape 25 (BG tape pasting process in FIG. 1 (E)) and the stripping process (BG tape stripping process in FIG. 2 (E)) are each performed only once. Can simplify the process.
- the resist mask 7 formed on the surface 5a is used in both the insulating film etching step (FIG. 1C) and the main etching step (FIG. 3A) to form the resist mask 7 (FIG. 1B).
- the resist mask forming step) and the removal of the resist mask 7 (the ashing step in FIG. 3B) are each performed only once, and the process can be simplified.
- the mask formation step (FIG. 1B) for providing the resist mask 7 on the semiconductor wafer 5 is performed before the semiconductor wafer 5 is thinned, that is, in a state where the semiconductor wafer 5 has sufficient rigidity. Since the semiconductor wafer 5 thinned by the back grinding process has low rigidity and deforms like paper, it is difficult to form a resist mask. On the other hand, if the mask forming step is executed before the semiconductor wafer 5 is thinned as in this embodiment, the resist mask 7 can be easily formed by photolithography, and a special apparatus is used for mask formation. There is no need to do.
- the BG tape peeling step (FIG. 2E) for peeling off the BG tape 25 from the semiconductor wafer 5 is performed before the semiconductor wafer 5 is divided into individual pieces, the operation is easy. It is not easy to remove the BG tape after dividing the semiconductor wafer 5 into individual pieces. In particular, when the size of the semiconductor chip 1 is reduced, the difficulty of this operation increases. Therefore, when the size of the semiconductor chip 1 is small, the advantage of performing the BG tape peeling step before the semiconductor wafer 5 is singulated as in this embodiment is particularly remarkable.
- the insulating film 3 formed on the surface 5a of the semiconductor wafer 5 is removed by plasma irradiation from the same surface 5a in the insulating film etching step (FIG. 1C), the insulating film 3 can be removed reliably and at high speed. .
- the insulating film etching step (FIG. 1C) is easy to handle with a sufficient thickness before the back grinding step (FIG. 2A), that is, before the semiconductor wafer 5 is thinned. Because there is no need to use special equipment.
- the BG tape 25 is peeled off and removed from the surface 5a of the semiconductor wafer 5 by removing the altered layer (roughness) on the surface of the resist mask 7 in the resist surface treatment step (FIG. 1C). It is possible to prevent the resist mask 7 from being damaged (peeling off from the surface 5a).
- Table 1 shows a comparison between the semiconductor chip manufacturing method according to the present embodiment and other manufacturing methods capable of manufacturing the same semiconductor chip 1 from the semiconductor wafer 5 of FIG.
- Table 1 compares the manufacturing method of the embodiment with the other four types of manufacturing methods listed below.
- DCG Downward Grinding
- a semiconductor wafer is mechanically divided by a dicer blade before grinding for thinning the semiconductor wafer 5.
- Backside plasma dicing is a manufacturing method in which the semiconductor wafer 5 is divided into individual semiconductor chips 1 by plasma irradiation only from the backside 5b where the IC portion 4 is not formed.
- Double-sided plasma dicing is a manufacturing method in which the semiconductor wafer 5 is divided into individual semiconductor chips 1 by sequentially irradiating plasma from both the front surface 5 a where the IC portion 4 is formed and the back surface 5 b where the IC portion 4 is not formed. Is the method.
- “Surface plasma dicing” is a manufacturing method in which the semiconductor wafer 5 is divided into individual semiconductor chips 1 by plasma irradiation only from the surface 5a on which the IC portion 4 is formed.
- Chip yield is an evaluation from the viewpoint of chip yield per one semiconductor wafer 5. When it is preferable in terms of chip yield, a “ ⁇ ” mark is shown, and when it is not preferable, a “X” mark is shown.
- Chip reduction is an evaluation from the viewpoint of effectively preventing or reducing chipping of the corners (edges) of the semiconductor chip 1.
- a “ ⁇ ” mark is indicated, and when the chipping cannot be effectively reduced, an “X” mark is indicated.
- “Handling property” is an evaluation of the ease of handling of the semiconductor wafer 5 being manufactured from the viewpoint of whether or not the handling (conveyance) is easy when the semiconductor wafer 5 is completely cut.
- “ ⁇ ” when not completely attached to a holding tape with a dicing ring, a completely divided semiconductor When it is necessary to handle the wafer 1, “x” is shown.
- “Tape application” requires a process of attaching a protective tape (BG tape 25 in the present embodiment) or a tape such as an adhesive tape used to hold a divided semiconductor wafer to the semiconductor wafer 5 at least twice. (In other words, whether the process of peeling the tape from the semiconductor wafer 5 is required twice or more) was evaluated. If the tape is applied once, a “ ⁇ ” mark is shown, and if more than two times are required, a “X” mark is shown. In addition, when the work of peeling the tape from the semiconductor wafer after being divided into semiconductor chips is included, “x” is also indicated when the difficulty of the work of peeling the tape from the semiconductor wafer is high.
- the “mask forming process” it is necessary to execute photolithography for forming the resist mask 7 on the semiconductor wafer whose thickness is reduced in the thinning process (in this embodiment, the back surface polishing process in FIG. 2A). Or, it is evaluated from the viewpoint of whether photolithography for forming the resist mask 7 needs to be executed twice or more (in other words, it is necessary to remove the resist mask 7 twice or more). If the photolithography for forming the resist mask 7 is not necessary after the thinning process and the photolithography for forming the resist mask 7 is performed once, “ ⁇ ” is shown, and the photolithography process is performed after the thinning process. If it needs to be performed or photolithography is required more than once, an “x” mark is shown.
- Insulating film etching is generally able to etch the insulating film 3 (SiO 2 in this embodiment) which is more difficult to etch than the semiconductor wafer 5 (Si or Si-based material in this embodiment) efficiently or at high speed. It is evaluated from the viewpoint of whether or not.
- the insulating film 3 can be etched at a high speed (in other words, when the insulating film is removed by etching from the surface side of the semiconductor wafer), a “ ⁇ ” mark is shown;
- Evaluation of each manufacturing method for each evaluation item is as follows.
- the number of times of applying the protective tape is “1” in “DBG”, but the evaluation is “ ⁇ ” because it is necessary to remove the protective tape from the semiconductor wafer divided into semiconductor chips. It is.
- the tape is attached and peeled twice or more, and thus the evaluation is “x”.
- the BG tape attaching step (FIG. 1E) and the BG tape peeling step (FIG. 2E) are each performed once.
- the BG tape 25 is peeled off from the semiconductor wafer 5 before being divided into semiconductor chips 1. Therefore, the evaluation of “the number of times of applying the protective tape” in the manufacturing method of this embodiment is “ ⁇ ”.
- the “mask formation process” photolithography is not performed in “DBG” in the first place.
- backside plasma dicing and “frontside plasma dicing”
- the number of times of photolithography for forming a mask is one, but since it is necessary to perform it on a semiconductor wafer thinned in the thinning process, the evaluation is “ ⁇ ”.
- “Double-sided plasma dicing” is evaluated as “x” because photolithography for mask formation is required twice on both the front and back sides.
- the photolithography for forming the resist mask 7 is performed only once (the mask formation process in FIG. 1B), and the semiconductor wafer 5 before being thinned in the thinning process is applied. Done. Therefore, the “mask formation process” in the manufacturing method of this embodiment is evaluated as “ ⁇ ”.
- etchability of insulating film “DBG” is not etched in the first place.
- double-sided plasma dicing” and “surface plasma dicing” the evaluation is “ ⁇ ” because the insulating film 3 can be etched at a high speed from the surface 5a on which the insulating film 3 is formed.
- backside plasma dicing since the insulating film 3 needs to be etched from the back surface 5b opposite to the surface 5a on which the insulating film 3 is formed, the etching efficiency is low and the evaluation is “x”.
- the insulating film 3 is etched from the surface 5a on which the insulating film 3 is formed (insulating film etching step in FIG. 1C), so that the insulating film 3 can be etched at a high speed. Therefore, the evaluation of “etching property of the insulating film” in the manufacturing method of this embodiment is “ ⁇ ”.
- the present invention can be variously modified as enumerated below.
- the resist surface treatment step (FIG. 1D) is not limited to the plasma treatment, but other than the plasma treatment as long as the roughness generated on the surface of the resist mask 7 in the insulating film etching step (FIG. 1E) can be removed.
- a dry or wet process can be employed.
- the resist surface treatment step may be omitted.
- the insulating film etching step (FIG. 1 (C)) and the subsequent resist surface treatment step (1 (D)) may be executed by another dry etching apparatus.
- the main etching step (FIG. 3A) and the subsequent ashing step (FIG. 3B) may be performed by another dry etching apparatus.
- any two or more of the ashing steps (FIG. 3B) may be executed by the same dry etching apparatus.
Abstract
Description
2 ダイ
3 絶縁膜
4 IC部
5 半導体ウエハ
5a 表面
5b 裏面
5c 変質層
6 分割領域
7 レジストマスク
11A,11B,11C ドライエッチング装置
12 チャンバ
12a ガス導入口
12b 排気口
13 アンテナ
14A,14B 高周波電源部
15 処理室
16 ステージ
17A CF4/Ar混合ガス源
17B 酸素ガス源
17C SF6ガス源
18 真空排気部
19 プラズマ
20 酸素プラズマ
21 SF6プラズマ
25 BGテープ
26 研削装置
27 ダイシングリング
28 保持テープ
29 カバー
Claims (4)
- 絶縁膜上に分割領域で画定された複数の半導体素子部が形成された第1の面と、この第1の面とは反対側の第2の面とを備える半導体ウエハを、前記半導体素子部毎に分割して半導体チップを製造する半導体チップの製造方法であって、
前記半導体素子部を覆うが前記分割領域は露出させるマスクを前記第1の面に形成する工程と、
前記第1の面からのプラズマ照射で前記マスクから露出している前記分割領域の前記絶縁膜を除去する第1のプラズマダイシング工程と、
前記第1のプラズマダイシング工程後に前記第1の面に保護テープを貼り付ける工程と、
前記保護テープの貼付後に、前記第2の面を研削して前記半導体ウエハを薄厚化する工程と、
前記研削後に、前記第2の面にフレーム付きの保持テープを貼り付ける工程と、
前記保持テープの貼付後に、前記第1の面から前記保護テープを剥離して除去する工程と、
前記保護テープの剥離後に、前記第1の面からのプラズマ照射で前記半導体ウエハにおいて前記マスクから露出している前記分割領域の部分を除去し、前記半導体ウエハを前記半導体素子部毎の複数の半導体チップに分割する第2のプラズマダイシング工程と、
前記第2のプラズマダイシング工程後に、前記マスクを除去する工程と
を備える半導体チップの製造方法。 - 前記保護テープの貼付前に、前記第1のプラズマダイシング工程により前記マスクの表面に生じた変質層を前記第1の面からのプラズマ照射で除去する工程をさらに備える、請求項1に記載の半導体チップの製造方法。
- 前記保持テープの貼付前に、前記研削により前記第2の面に生じた変質層を前記第1の面からのプラズマ照射で除去する工程をさらに備える、請求項1又は請求項2に記載の半導体チップの製造方法。
- 前記マスクを除去する工程は、前記第1の面からのプラズマ照射で前記マスクを除去するものである、請求項1から請求項3のいずれか1項に記載の半導体チップの製造方法。
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US9041198B2 (en) * | 2013-10-22 | 2015-05-26 | Applied Materials, Inc. | Maskless hybrid laser scribing and plasma etching wafer dicing process |
JP6318046B2 (ja) * | 2014-08-12 | 2018-04-25 | 株式会社ディスコ | ウエーハの分割方法 |
JP6296299B2 (ja) * | 2014-09-02 | 2018-03-20 | パナソニックIpマネジメント株式会社 | プラズマ処理装置およびプラズマ処理方法 |
JP2016051876A (ja) * | 2014-09-02 | 2016-04-11 | パナソニックIpマネジメント株式会社 | プラズマ処理装置およびプラズマ処理方法 |
JP2016058578A (ja) * | 2014-09-10 | 2016-04-21 | 株式会社ディスコ | 分割方法 |
JP6522998B2 (ja) * | 2015-03-13 | 2019-05-29 | 古河電気工業株式会社 | 半導体ウェハの処理方法、半導体チップおよび半導体ウェハ処理用表面保護テープ。 |
JP6738591B2 (ja) * | 2015-03-13 | 2020-08-12 | 古河電気工業株式会社 | 半導体ウェハの処理方法、半導体チップおよび表面保護テープ |
JP6500230B2 (ja) | 2015-09-03 | 2019-04-17 | パナソニックIpマネジメント株式会社 | マスクパターンの形成方法および基板の加工方法ならびに素子チップの製造方法 |
JP6492286B2 (ja) * | 2015-09-25 | 2019-04-03 | パナソニックIpマネジメント株式会社 | 素子チップの製造方法 |
JP6492288B2 (ja) * | 2015-10-01 | 2019-04-03 | パナソニックIpマネジメント株式会社 | 素子チップの製造方法 |
JP6564670B2 (ja) * | 2015-10-06 | 2019-08-21 | 株式会社ディスコ | デバイスの製造方法 |
CN113675131A (zh) * | 2015-11-09 | 2021-11-19 | 古河电气工业株式会社 | 半导体芯片的制造方法和用于该制造方法的掩模一体型表面保护带 |
JP6575874B2 (ja) * | 2016-03-09 | 2019-09-18 | パナソニックIpマネジメント株式会社 | 素子チップの製造方法 |
JP6524535B2 (ja) * | 2016-03-11 | 2019-06-05 | パナソニックIpマネジメント株式会社 | 素子チップおよびその製造方法 |
JP2017163070A (ja) * | 2016-03-11 | 2017-09-14 | パナソニックIpマネジメント株式会社 | 素子チップおよびその製造方法 |
JP6524553B2 (ja) * | 2016-05-30 | 2019-06-05 | パナソニックIpマネジメント株式会社 | 素子チップの製造方法 |
JP6512454B2 (ja) * | 2016-12-06 | 2019-05-15 | パナソニックIpマネジメント株式会社 | 素子チップの製造方法 |
JP2018110156A (ja) | 2016-12-28 | 2018-07-12 | キヤノン株式会社 | 半導体装置、その製造方法およびカメラ |
CN109536067B (zh) * | 2018-10-31 | 2021-04-13 | 中航锂电技术研究院有限公司 | 一种防止辊压溢胶的耐高温胶带 |
JP6646820B2 (ja) * | 2019-02-20 | 2020-02-14 | パナソニックIpマネジメント株式会社 | 素子チップの製造方法 |
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CN113539956A (zh) * | 2021-06-11 | 2021-10-22 | 深圳米飞泰克科技有限公司 | 一种晶片的加工方法 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03185750A (ja) * | 1989-12-14 | 1991-08-13 | Victor Co Of Japan Ltd | 半導体装置 |
JPH03205846A (ja) * | 1990-01-08 | 1991-09-09 | Sumitomo Electric Ind Ltd | 半導体装置の製造方法 |
JPH0864828A (ja) * | 1994-08-24 | 1996-03-08 | Oki Electric Ind Co Ltd | 薄膜トランジスタの製造方法 |
JP2003282490A (ja) * | 2002-03-27 | 2003-10-03 | Hitachi Ltd | 半導体装置及びその製造方法 |
JP2006114825A (ja) * | 2004-10-18 | 2006-04-27 | Disco Abrasive Syst Ltd | ウェーハの分割方法 |
JP2010165963A (ja) * | 2009-01-19 | 2010-07-29 | Furukawa Electric Co Ltd:The | 半導体ウェハの処理方法 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3205846B2 (ja) * | 1993-06-01 | 2001-09-04 | 日本無線株式会社 | 自動衝突予防援助装置 |
JPH07201784A (ja) | 1994-01-07 | 1995-08-04 | Fujitsu Ltd | 半導体装置の製造方法 |
JP2002100588A (ja) | 2000-09-22 | 2002-04-05 | Shinkawa Ltd | 半導体装置の製造方法 |
JP4579489B2 (ja) | 2002-09-02 | 2010-11-10 | 新光電気工業株式会社 | 半導体チップ製造方法及び半導体チップ |
US6897128B2 (en) | 2002-11-20 | 2005-05-24 | Matsushita Electric Industrial Co., Ltd. | Method of manufacturing semiconductor device, plasma processing apparatus and plasma processing method |
JP4013745B2 (ja) | 2002-11-20 | 2007-11-28 | 松下電器産業株式会社 | プラズマ処理方法 |
JP4840174B2 (ja) * | 2007-02-08 | 2011-12-21 | パナソニック株式会社 | 半導体チップの製造方法 |
US7655539B2 (en) * | 2008-04-16 | 2010-02-02 | Fairchild Semiconductor Corporation | Dice by grind for back surface metallized dies |
US8188924B2 (en) * | 2008-05-22 | 2012-05-29 | Philtech Inc. | RF powder and method for manufacturing the same |
-
2011
- 2011-05-19 JP JP2011112434A patent/JP5591181B2/ja active Active
-
2012
- 2012-05-18 WO PCT/JP2012/003277 patent/WO2012157287A1/ja active Application Filing
- 2012-05-18 CN CN201280024239.1A patent/CN103563053B/zh active Active
- 2012-05-18 US US14/117,463 patent/US9076859B2/en active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03185750A (ja) * | 1989-12-14 | 1991-08-13 | Victor Co Of Japan Ltd | 半導体装置 |
JPH03205846A (ja) * | 1990-01-08 | 1991-09-09 | Sumitomo Electric Ind Ltd | 半導体装置の製造方法 |
JPH0864828A (ja) * | 1994-08-24 | 1996-03-08 | Oki Electric Ind Co Ltd | 薄膜トランジスタの製造方法 |
JP2003282490A (ja) * | 2002-03-27 | 2003-10-03 | Hitachi Ltd | 半導体装置及びその製造方法 |
JP2006114825A (ja) * | 2004-10-18 | 2006-04-27 | Disco Abrasive Syst Ltd | ウェーハの分割方法 |
JP2010165963A (ja) * | 2009-01-19 | 2010-07-29 | Furukawa Electric Co Ltd:The | 半導体ウェハの処理方法 |
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