JP2017163070A - 素子チップおよびその製造方法 - Google Patents
素子チップおよびその製造方法 Download PDFInfo
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Abstract
【解決手段】第1層と第2層とを備える基板の分割領域に、第2層側からレーザ光を照射して、分割領域に第1層が露出する露出部を備える開口を形成するとともに、露出部を含む第1層の表層部に第1ダメージ領域を形成し、第1ダメージ領域の近傍であって、第2層に覆われる第1層の表層部に第2ダメージ領域を形成するレーザスクライブ工程と、レーザスクライブ工程の後、基板を第1プラズマに晒すことにより第1層を等方的にエッチングして、第1ダメージ領域と第2ダメージ領域とを除去する等方エッチング工程と、等方エッチング工程の後、第2主面を支持部材で支持した状態で基板を第2プラズマに晒すことにより、第1層を異方的にエッチングして、基板を、素子領域を備える複数の素子チップに分割するプラズマダイシング工程と、を備える素子チップの製造方法。
【選択図】図1
Description
(1)準備工程
まず、ダイシングの対象となる基板10を準備する(図1(a))。基板10は、第1主面10Xおよび第2主面10Yを備えており、半導体層である第1層11と、第1層11の第1主面10X側に形成された絶縁膜を含む第2層12と、を備える。また、基板10は、分割領域R1と、分割領域R1によって画定される複数の素子領域R2とに区画されている。したがって、第1層11は、分割領域R1に対応する第1分割領域111と、素子領域R2に対応する複数の第1素子領域112とを備える。第2層12は、分割領域R1に対応する第2分割領域121と、素子領域R2に対応する複数の第2素子領域122とを備える。基板10の素子領域R2(第1素子領域112と第2素子領域122)には、半導体回路、電子部品素子、MEMS等の回路層(いずれも図示せず)が形成されていてもよい。
レーザスクライブ工程では、第2分割領域121に第1主面10X側からレーザ光Lを照射して、第2分割領域121の一部を除去し、第1分割領域111が一部露出した開口10Aを形成する(図1(b))。言い換えれば、レーザスクライブ工程では、第1分割領域111の一部を露出させて、露出部111aを形成する。レーザ光Lの中心波長は特に限定されず、例えば350〜600nmである。
レーザスクライブ工程の後、プラズマダイシング工程の前に、開口10Aを第1プラズマP1に晒す(図1(c))。このとき、第2素子領域122は、マスクとして機能する。しかし、等方的に進行するエッチング条件でエッチングすることにより、開口10Aから露出する第1ダメージ領域DR1に加えて、第2層12に覆われる第2ダメージ領域DR2もエッチングされる。このとき、開口10A付近の第2素子領域122の下方には、ラウンド形状の窪み112gが形成される。
次に、第2主面10Yを支持部材22で支持した状態で、基板10をプラズマP2に晒す(図1(d))。プラズマP2は、第1分割領域111が異方的にエッチングされる条件で発生させる。例えば、六フッ化硫黄(SF6)等のフッ素を含むプロセスガスを用いるとともに、高周波電極部220に高周波電力を印加して、バイアス電圧をかける。これにより、基材10の厚みに平行な方向に、異方的にエッチングが行われる。上記のエッチング条件は、第1層11の材質に応じて適宜選択することができる。第1層11がSiの場合、第1分割領域111のエッチングには、いわゆるボッシュプロセスを用いることができる。ボッシュプロセスでは、堆積膜堆積ステップと、堆積膜エッチングステップと、Siエッチングステップとを順次繰り返すことにより、第1分割領域111を深さ方向に掘り進む。
10A:開口
10X:第1主面
10Y:第2主面
11:第1層
111:第1分割領域
111a:露出部
112:第1素子領域
112X:積層面
112Y:積層面とは反対側の面
112g:窪み
12:第2層
121:第2分割領域
122:第2素子領域
110:素子チップ
20:搬送キャリア
21:フレーム
21a:ノッチ
21b:コーナーカット
22:支持部材
22a:粘着面
22b:非粘着面
200:プラズマ処理装置
203:真空チャンバ
203a:ガス導入口
203b:排気口
208:誘電体部材
209:アンテナ
210A:第1高周波電源
210B:第2高周波電源
211:ステージ
212:プロセスガス源
213:アッシングガス源
214:減圧機構
215:電極層
216:金属層
217:基台
218:外周部
219:ESC電極
220:高周波電極部
221:昇降ロッド
222:支持部
223A、223B:昇降機構
224:カバー
224W:窓部
225:冷媒循環装置
226:直流電源
227:冷媒流路
228:制御装置
229:外周リング
30:基板
31:第1層
32:第2層
130:素子チップ
Claims (3)
- 第1主面および第2主面を備え、半導体層である第1層と、前記第1層の前記第1主面側に形成された絶縁膜を含む第2層と、を備える基板であって、複数の素子領域と、前記素子領域を画定する分割領域を備える基板を準備する工程と、
前記分割領域に前記第1主面側からレーザ光を照射して、前記分割領域に前記第1層が露出する露出部を備える開口を形成するとともに、前記露出部を含む前記第1層の表層部に第1ダメージ領域を形成し、前記第1ダメージ領域の近傍であって、前記第2層に覆われる前記第1層の表層部に第2ダメージ領域を形成するレーザスクライブ工程と、
前記レーザスクライブ工程の後、前記基板を第1プラズマに晒すことにより前記第1層を等方的にエッチングして、前記第1ダメージ領域と前記第2ダメージ領域とを除去する等方エッチング工程と、
前記等方エッチング工程の後、前記第2主面を支持部材で支持した状態で前記基板を第2プラズマに晒すことにより、前記第1層を異方的にエッチングして、前記基板を、前記素子領域を備える複数の素子チップに分割するプラズマダイシング工程と、を備える、素子チップの製造方法。 - 前記等方エッチング工程では、六フッ化硫黄を含むプロセスガスを原料として前記第1プラズマを発生させる、請求項1に記載の素子チップの製造方法。
- 積層面とその反対側の面とを備える半導体層である第1層と、前記積層面上に積層された絶縁膜を含む第2層と、を備える素子チップであって、
前記第1層の前記積層面側の周縁部に形成された窪みを備える、素子チップ。
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