JP4827567B2 - プラズマエッチング方法およびコンピュータ読み取り可能な記憶媒体 - Google Patents
プラズマエッチング方法およびコンピュータ読み取り可能な記憶媒体 Download PDFInfo
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- 238000001020 plasma etching Methods 0.000 title claims description 39
- 238000000034 method Methods 0.000 title claims description 32
- 238000003860 storage Methods 0.000 title claims description 11
- 238000005530 etching Methods 0.000 claims description 125
- 238000012545 processing Methods 0.000 claims description 42
- 239000000463 material Substances 0.000 claims description 18
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- 239000004065 semiconductor Substances 0.000 description 20
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- 230000008021 deposition Effects 0.000 description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 7
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- 239000010949 copper Substances 0.000 description 7
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- 229910052751 metal Inorganic materials 0.000 description 5
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Inorganic materials [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
- H01L21/31138—Etching organic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/7681—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving one or more buried masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Drying Of Semiconductors (AREA)
Description
また、このようなプラズマエッチング方法を実行させるプログラムを記憶したコンピュータ読み取り可能な記憶媒体を提供することを目的とする。
図1は、本発明の実施に用いられるプラズマエッチング装置の一例を示す概略断面図である。
ここでは、被処理体である半導体ウエハWとして、図3に示すように、Si基板101の上に、銅配線層102、エッチングストップ膜103、層間絶縁膜として機能するLow−k膜104、メタルハードマスク層105からなり、図示しないフォトレジスト膜等のエッチングマスクを用いてLow−k膜104にビア106を形成し、エッチングマスクをアッシングにより除去した後、メタルハードマスク層105をエッチングマスクとして用いてレンチ107を形成したものを用いる。
上部電極34には、従前のエッチングプロセス、特に上部電極34への高周波電力が小さいエッチングプロセスによってポリマーが付着している。そして、エッチング処理を行う際に上部電極34に適切な直流電圧を印加すると、図5に示すように、上部電極の自己バイアス電圧Vdcを深くすること、つまり上部電極34表面でのVdcの絶対値を大きくすることができる。このため、上部電極34に付着しているポリマーが印加された直流電圧によってスパッタされて半導体ウエハWに供給され、エッチング対象膜であるエッチングストップ膜103の側壁にも付着する。これによりエッチングストップ膜103の側壁が保護され、エッチングされ難くなる。
RFパワー(上部60MHz/下部2MHz)
:30/250W
直流電圧 :−400V
処理ガス
CF4ガス :112mL/min(sccm)
Arガス :150mL/min(sccm)
O2ガス : 6mL/min(sccm)
C4F8ガス:13mL/min(sccm)
時間 :110sec
温度 サセプタ:40℃
ウエハ :60℃
RFパワー(上部60MHz/下部2MHz)
:400/1000W
直流電圧 : 0V
処理ガス
NF3ガス: 12mL/min(sccm)
Arガス :200mL/min(sccm)
Heガス :240mL/min(sccm)
時間 :15sec
温度 サセプタ:40℃
ウエハ :60℃
16…サセプタ(下部電極)
34…上部電極
44…給電棒
46,88…整合器
48…第1の高周波電源
50…可変直流電源
51…コントローラ
52…オン・オフスイッチ
66…処理ガス供給源
84…排気装置
90…第2の高周波電源
91…GNDブロック
101…Si基板
102…銅配線層
103…エッチングストップ膜
104…Low−k膜
105…メタルハードマスク層
W…半導体ウエハ(被処理基板)
Claims (8)
- 上部電極および下部電極が上下に対向して設けられた処理容器内で、基板上に、配線層、SiC系材料からなるエッチングストップ膜、低誘電率(Low−k)膜およびエッチングマスクを順次形成した構造体の前記エッチングストップ膜をプラズマエッチングするプラズマエッチング方法であって、
前記低誘電率(Low−k)膜をプラズマエッチングした後の前記構造体が配置された前記処理容器内にNF3を含む処理ガスを導入する工程と、
前記上部電極および前記下部電極のいずれかに高周波電力を印加して前記NF3を含む処理ガスのプラズマを生成する工程と、
前記上部電極と前記下部電極のいずれかに直流電圧を印加する工程と
を有し、
前記直流電圧の印加により、前記プラズマエッチングのエッチング側壁へデポを形成して前記エッチング側壁を保護するとともに、プラズマが形成される際に生成した電子を前記上部電極から前記下部電極に向けて鉛直方向に加速し、
前記エッチングストップ膜を、前記低誘電率(Low−k)膜に対して高選択比で、かつ、前記低誘電率(Low−k)膜の直下でエッチングが横方向に進行することを抑制しつつエッチングすることを特徴とするプラズマエッチング方法。 - 前記直流電圧の絶対値が400V以上であることを特徴とする請求項1に記載のプラズマエッチング方法。
- 前記低誘電率(Low−k)膜は、SiOC系膜であることを特徴とする請求項1または請求項2に記載のプラズマエッチング方法。
- テスト用の被処理体について、予め、所望のエッチング形状が得られるような直流電圧値を求めておき、その際の直流電圧値を前記いずれかの電極に印加して前記所定の直流電圧を印加する工程を実施することを特徴とする請求項1から請求項3のいずれか1項に記載のプラズマエッチング方法。
- 前記上部電極および前記下部電極に高周波電力を供給し、前記上部電極に直流電圧を印加することを特徴とする請求項1から請求項4のいずれか1項に記載のプラズマエッチング方法。
- 前記下部電極に第1の周波数の第1の高周波電力および前記第1の周波数よりも小さい第2の周波数の第2の高周波電力を供給し、前記上部電極に直流電圧を印加することを特徴とする請求項1から請求項4のいずれか1項に記載のプラズマエッチング方法。
- 前記下部電極に第1の周波数の第1の高周波電力および前記第1の周波数よりも小さい第2の周波数の第2の高周波電力を供給し、前記下部電極に直流電圧を印加することを特徴とする請求項1から請求項4のいずれか1項に記載のプラズマエッチング方法。
- コンピュータ上で動作し、プラズマ処理装置を制御するための制御プログラムが記憶されたコンピュータ記憶媒体であって、
前記制御プログラムは、実行時に、請求項1から請求項7のいずれか1項に記載のプラズマエッチング方法が行われるように、コンピュータに前記プラズマ処理装置を制御させることを特徴とするコンピュータ読み取り可能な記憶媒体。
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JP2006072825A JP4827567B2 (ja) | 2006-03-16 | 2006-03-16 | プラズマエッチング方法およびコンピュータ読み取り可能な記憶媒体 |
KR1020070024760A KR100886274B1 (ko) | 2006-03-16 | 2007-03-14 | 플라즈마 에칭 방법 및 컴퓨터 판독 가능한 기억 매체 |
US11/686,686 US20070218699A1 (en) | 2006-03-16 | 2007-03-15 | Plasma etching method and computer-readable storage medium |
CNB2007100883796A CN100474524C (zh) | 2006-03-16 | 2007-03-16 | 等离子体蚀刻方法及计算机可读取的存储介质 |
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JP6400425B2 (ja) * | 2014-10-15 | 2018-10-03 | 東京エレクトロン株式会社 | 多層膜をエッチングする方法 |
JP2017163070A (ja) * | 2016-03-11 | 2017-09-14 | パナソニックIpマネジメント株式会社 | 素子チップおよびその製造方法 |
CN108287982B (zh) * | 2018-01-16 | 2021-04-13 | 温州大学 | 一种多孔硅碳氧陶瓷的建模方法 |
KR102024568B1 (ko) * | 2018-02-13 | 2019-09-24 | 한국기초과학지원연구원 | 환형 면방전 플라즈마 장치를 이용한 점상 식각 모듈 및 점상 식각 모듈의 식각 프로파일을 제어하는 방법 |
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