WO2014057799A1 - プラズマエッチング方法 - Google Patents
プラズマエッチング方法 Download PDFInfo
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- WO2014057799A1 WO2014057799A1 PCT/JP2013/075708 JP2013075708W WO2014057799A1 WO 2014057799 A1 WO2014057799 A1 WO 2014057799A1 JP 2013075708 W JP2013075708 W JP 2013075708W WO 2014057799 A1 WO2014057799 A1 WO 2014057799A1
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- gas
- etching
- plasma
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- 238000001020 plasma etching Methods 0.000 title claims abstract description 59
- 238000000034 method Methods 0.000 title claims abstract description 45
- 238000005530 etching Methods 0.000 claims abstract description 82
- 238000012545 processing Methods 0.000 claims abstract description 61
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 48
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 48
- 239000010703 silicon Substances 0.000 claims abstract description 48
- 230000008021 deposition Effects 0.000 claims abstract description 45
- 239000000758 substrate Substances 0.000 claims abstract description 21
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 16
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 10
- 229920005591 polysilicon Polymers 0.000 claims abstract description 10
- 238000000151 deposition Methods 0.000 claims description 61
- 239000000463 material Substances 0.000 abstract description 4
- 239000007789 gas Substances 0.000 description 87
- 239000004065 semiconductor Substances 0.000 description 13
- 230000000052 comparative effect Effects 0.000 description 12
- 238000010586 diagram Methods 0.000 description 12
- 150000002500 ions Chemical class 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- 239000004020 conductor Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000003507 refrigerant Substances 0.000 description 4
- 230000003749 cleanliness Effects 0.000 description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 238000012937 correction Methods 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- -1 for example Substances 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 230000003746 surface roughness Effects 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- XKRFYHLGVUSROY-UHFFFAOYSA-N argon Substances [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 1
- 238000000691 measurement method Methods 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000011144 upstream manufacturing Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
- H01J2237/32—Processing objects by plasma generation
- H01J2237/33—Processing objects by plasma generation characterised by the type of processing
- H01J2237/334—Etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
- H01J37/32082—Radio frequency generated discharge
- H01J37/32091—Radio frequency generated discharge the radio frequency energy being capacitively coupled to the plasma
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67098—Apparatus for thermal treatment
- H01L21/67109—Apparatus for thermal treatment mainly by convection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6831—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using electrostatic chucks
Definitions
- Various aspects and embodiments of the present invention relate to a plasma etching method.
- a plasma processing apparatus performs etching using, for example, a photoresist as a mask.
- the plasma processing apparatus modifies the composition of a photoresist used as a mask.
- the above-described conventional technique has a problem that the mask selection ratio is lowered when a polysilicon mask is used as a mask.
- the disclosed plasma etching method is based on silicon with respect to a processing substrate in which an underlayer, a silicon oxide film, and an etching mask made of polysilicon on which an etching pattern is formed are sequentially stacked.
- the disclosed plasma etching method includes an etching step of etching the silicon oxide film with plasma using a first CF-based gas using the etching mask on which the silicon-containing deposit is deposited as a mask.
- the mask selection ratio can be improved when a polysilicon mask is used as a mask.
- FIG. 1 is a cross-sectional view schematically showing a plasma etching apparatus applied to the plasma etching method according to the first embodiment.
- FIG. 2 is a schematic cross-sectional view showing a plasma etching apparatus applied to the plasma etching method according to the first embodiment.
- FIG. 3 is a flowchart showing an example of the flow of plasma etching processing by the plasma etching apparatus in the first embodiment.
- FIG. 4 is a diagram showing the deposition step in the first embodiment.
- FIG. 5 is a diagram illustrating an example of the structure of the processing substrate in Example 1 and Comparative Example 1.
- FIG. 6 is a diagram illustrating a processing result in the first comparative example.
- FIG. 7 is a diagram illustrating a processing result in the second embodiment.
- FIG. 8 is a diagram illustrating a processing result in the third embodiment.
- FIG. 9 is a diagram illustrating a processing result in the fourth embodiment.
- the plasma etching method according to the first embodiment is applied to a processing substrate in which an underlayer, a silicon oxide film, and an etching mask made of polysilicon on which an etching pattern is formed are sequentially stacked. And a deposition step of depositing a silicon-containing deposit on the etching mask surface by plasma with a processing gas while applying a negative DC voltage to the upper electrode made of silicon.
- the plasma etching method according to the first embodiment includes an etching step of etching the silicon oxide film with plasma using a first CF-based gas, using the etching mask on which the silicon-containing deposit is deposited as a mask in one embodiment. .
- the processing gas is selected from H2 / Ar gas, CF4 / H2 / Ar gas, and CF4 / COS / Ar gas.
- the plasma etching method according to the first embodiment is a deposition in which a CF-based deposit is deposited by plasma with a second CF-based processing gas after the deposition step and before the etching step.
- the method further includes a step.
- the first CF-based gas is C4F6 / C4F8 / Ar / O2 gas.
- the second CF-based gas is C4F6 / Ar / O2 gas.
- FIG. 1 is a cross-sectional view schematically showing a plasma etching apparatus applied to the plasma etching method according to the first embodiment.
- the plasma etching apparatus applies, for example, 40 MHz high frequency (RF) power for plasma generation from a first high frequency power supply 89 to a susceptor 16 that is a lower electrode, and from a second high frequency power supply 90.
- RF high frequency
- a plasma etching apparatus of a lower RF 2 frequency application type that applies a high frequency (RF) power of, for example, 2 MHz for ion attraction, and a predetermined direct current (DC) is connected by connecting a variable DC power supply 50 to the upper electrode 34 as shown A plasma etching apparatus to which a voltage is applied.
- RF high frequency
- DC direct current
- FIG. 2 is a schematic cross-sectional view showing a plasma etching apparatus applied to the plasma etching method according to the first embodiment.
- the plasma etching apparatus is configured as a capacitively coupled parallel plate plasma etching apparatus, and has a substantially cylindrical chamber (processing vessel) 10 made of aluminum whose surface is anodized, for example.
- the chamber 10 is grounded.
- a cylindrical susceptor support 14 is disposed at the bottom of the chamber 10 via an insulating plate 12 made of ceramics or the like. On the susceptor support 14, a susceptor 16 made of, for example, aluminum is provided. The susceptor 16 forms a lower electrode, and a semiconductor wafer W that is a substrate to be processed is placed on the susceptor 16.
- an electrostatic chuck 18 for attracting and holding the semiconductor wafer W with an electrostatic force is provided.
- the electrostatic chuck 18 has a structure in which an electrode 20 made of a conductive film is sandwiched between a pair of insulating layers or insulating sheets, and a DC power source 22 is electrically connected to the electrode 20.
- the semiconductor wafer W is attracted and held by an electrostatic force such as a Coulomb force generated by a DC voltage from the DC power supply 22.
- a conductive focus ring (correction ring) 24 that improves the uniformity of etching is disposed on the upper surface of the susceptor 16 around the electrostatic chuck 18 (semiconductor wafer W).
- the focus ring (correction ring) 24 is made of, for example, silicon.
- a cylindrical inner wall member 26 made of, for example, quartz is provided on the side surfaces of the susceptor 16 and the susceptor support 14.
- a refrigerant chamber 28 is provided on the circumference.
- a refrigerant having a predetermined temperature is circulated and supplied to the refrigerant chamber 28 via pipes 30a and 30b from a chiller unit (not shown) provided outside.
- the processing temperature of the semiconductor wafer W on the susceptor 16 is controlled by the temperature of the refrigerant.
- a heat transfer gas for example, He gas
- a heat transfer gas supply mechanism (not shown) is supplied between the upper surface of the electrostatic chuck 18 and the back surface of the semiconductor wafer W via the gas supply line 32.
- an upper electrode 34 is provided in parallel to face the susceptor 16.
- a space between the upper and lower electrodes 34 and 16 becomes a plasma generation space.
- the upper electrode 34 faces the semiconductor wafer W on the susceptor 16 that is the lower electrode, and forms a surface that is in contact with the plasma generation space, that is, a facing surface.
- the upper electrode 34 is supported on the upper part of the chamber 10 through the insulating shielding member 42.
- the upper electrode 34 constitutes a surface facing the susceptor 16 and has a number of gas discharge holes 37, and an electrode support 38 having a water cooling structure made of a conductive material by detachably supporting the electrode plate 36. And is composed of.
- the conductive material forming the electrode support 38 is, for example, aluminum whose surface is anodized.
- the electrode plate 36 is made of a silicon-containing material, for example, silicon.
- a gas diffusion chamber 40 is provided inside the electrode support 38.
- a large number of gas flow holes 41 communicating with the gas discharge holes 37 extend downward from the gas diffusion chamber 40.
- a gas inlet 62 for introducing the processing gas to the gas diffusion chamber 40 is formed.
- a gas supply pipe 64 is connected to the gas introduction port 62, and a processing gas supply source 66 is connected to the gas supply pipe 64.
- the gas supply pipe 64 is provided with a mass flow controller (MFC) 68 and an opening / closing valve 70 in order from the upstream side.
- MFC mass flow controller
- a fluorocarbon gas (CxFy) such as C4F8 gas reaches the gas diffusion chamber 40 from the gas supply pipe 64, the gas flow hole 41 and the gas discharge hole 37. And is discharged into the plasma generation space in the form of a shower. That is, the upper electrode 34 functions as a shower head for supplying the processing gas.
- a processing gas, a first CF-based gas, a second CF-based gas, and the like used for depositing the silicon-containing deposit are supplied from the processing gas supply source 66. Details of the gas supplied from the processing gas supply source 66 will be described later.
- a variable DC power supply 50 is electrically connected to the upper electrode 34 via a low pass filter (LPF) 46a.
- the variable DC power supply 50 may be a bipolar power supply.
- the variable DC power supply 50 can be turned on / off by an on / off switch 52.
- the polarity and current / voltage of the variable DC power supply 50 and the on / off of the on / off switch 52 are controlled by a controller (control device) 51.
- the low pass filter (LPF) 46a is for trapping a high frequency from first and second high frequency power sources described later, and is preferably composed of an LR filter or an LC filter.
- a cylindrical ground conductor 10 a is provided so as to extend from the side wall of the chamber 10 to a position higher than the height position of the upper electrode 34.
- the cylindrical ground conductor 10a has a top wall at the top thereof.
- a first high frequency power supply 89 is electrically connected to the susceptor 16 which is a lower electrode through a matching unit 87.
- the susceptor 16 is electrically connected to a second high frequency power supply 90 via a matching unit 88.
- the first high frequency power supply 89 outputs a high frequency power of 27 MHz or higher, for example, 40 MHz.
- the second high frequency power supply 90 outputs a high frequency power of 13.56 MHz or less, for example, 2 MHz.
- Matching devices 87 and 88 are used to match the load impedance to the internal (or output) impedances of the first and second high-frequency power sources 89 and 90, respectively, and are used when the plasma is generated in the chamber 10. It functions so that the internal impedance of the first and second high frequency power supplies 89 and 90 and the load impedance seem to coincide with each other.
- An exhaust port 80 is provided at the bottom of the chamber 10, and an exhaust device 84 is connected to the exhaust port 80 via an exhaust pipe 82.
- the exhaust device 84 includes a vacuum pump such as a turbo molecular pump, and can reduce the pressure in the chamber 10 to a desired degree of vacuum.
- a loading / unloading port 85 for the semiconductor wafer W is provided on the side wall of the chamber 10.
- the loading / unloading port 85 can be opened and closed by a gate valve 86.
- a deposition shield 11 is detachably provided along the inner wall of the chamber 10 for preventing the etching byproduct (depot) from adhering to the chamber 10. That is, the deposition shield 11 forms a chamber wall.
- the deposition shield 11 is also provided on the outer periphery of the inner wall member 26.
- An exhaust plate 83 is provided between the deposition shield 11 on the chamber wall side at the bottom of the chamber 10 and the deposition shield 11 on the inner wall member 26 side.
- an aluminum material coated with ceramics such as Y2O3 can be suitably used.
- a conductive member (GND block) 91 connected to the ground in a DC manner is provided at a portion substantially the same height as the wafer W constituting the inner wall of the chamber 10 of the deposition shield 11, which will be described later. Exhibits the effect of preventing abnormal discharge.
- control unit 95 Each component of the plasma etching apparatus is connected to and controlled by a control unit (overall control device) 95.
- control unit 95 includes a user interface 96 including a keyboard on which a process manager inputs commands to manage the plasma etching apparatus, a display that visualizes and displays the operating status of the plasma processing apparatus, and the like. It is connected.
- the control unit 95 has a control program for realizing various processes executed in the plasma etching apparatus under the control of the control unit 95, and causes each component of the plasma etching apparatus to execute processes according to processing conditions.
- the recipe may be stored in a hard disk or semiconductor memory, or set in a predetermined position in the storage unit 97 while being stored in a portable computer-readable storage medium such as a CDROM or DVD. Also good.
- an arbitrary recipe is called from the storage unit 97 by an instruction from the user interface 96 and executed by the control unit 95, so that the control unit 95 controls the plasma etching apparatus.
- the desired processing is performed.
- the gate valve 86 is opened, and the semiconductor wafer W to be etched is loaded into the chamber 10 via the loading / unloading port 85, and the susceptor is loaded. 16 is mounted. Then, a processing gas for etching is supplied from the processing gas supply source 66 to the gas diffusion chamber 40 at a predetermined flow rate, and is supplied into the chamber 10 through the gas flow holes 41 and the gas discharge holes 37, and the exhaust device
- the chamber 10 is evacuated by 84, and the pressure therein is set to a set value within a range of 0.1 to 150 Pa, for example.
- the high frequency power for plasma generation is applied from the first high frequency power supply 89 to the susceptor 16 as the lower electrode at a predetermined power, and the second high frequency power supply is applied. From 90, high-frequency power for ion attraction is applied at a predetermined power. Then, a predetermined DC voltage is applied to the upper electrode 34 from the variable DC power supply 50. Further, a DC voltage is applied from the DC power source 22 for the electrostatic chuck 18 to the electrode 20 of the electrostatic chuck 18 to fix the semiconductor wafer W to the susceptor 16.
- the processing gas discharged from the gas discharge holes 37 formed in the electrode plate 36 of the upper electrode 34 is converted into plasma in a glow discharge between the upper electrode 34 and the lower electrode susceptor 16 generated by high frequency power, and is generated by plasma.
- the surface to be processed of the semiconductor wafer W is etched by the radicals and ions.
- high-frequency power in a high frequency region (for example, 10 MHz or more) is supplied from the first high-frequency power supply 89 to the susceptor 16 as the lower electrode, so that the plasma can be densified in a preferable state.
- High density plasma can be formed even under lower pressure conditions.
- FIG. 3 is a flowchart showing an example of the flow of plasma etching processing by the plasma etching apparatus in the first embodiment.
- the plasma etching apparatus performs a series of processes on a processing substrate in which an underlayer, a silicon oxide film, and an etching mask made of polysilicon on which an etching pattern is formed are sequentially stacked. Execute the process.
- the underlayer is polysilicon, SiC, SiN, or the like.
- the silicon oxide film is, for example, SiO2, TEOS (Tetraethoxysilane).
- the plasma etching apparatus applies a negative DC voltage to the upper electrode made of silicon, and plasma containing a silicon-containing deposit is formed on the etching mask surface by plasma with a processing gas.
- a deposition step for depositing is performed (step S102).
- the plasma etching apparatus deposits silicon-containing deposits using, for example, H2 / Ar gas, CF4 / H2 / Ar gas, and CF4 / COS / Ar gas as process gases.
- FIG. 4 is a diagram showing the deposition step in the first embodiment.
- the plasma etching apparatus applies high frequency power from the first high frequency power supply 89 and connects the variable DC power supply 50 to the upper electrode 34 to apply a predetermined direct current (DC) voltage.
- the high frequency power for ion attraction is not applied from the second high frequency power supply 90. That is, as shown in FIG. 4A, the plasma etching apparatus applies a negative DC voltage having a predetermined polarity and magnitude from the variable DC power source 50 to the upper electrode 34 when plasma is formed.
- the self-bias voltage Vdc on the surface of the electrode plate 36 is such that a predetermined (moderate) sputtering effect is obtained with respect to the surface of the electrode plate 36 that is the surface of the upper electrode 34 that is the application electrode.
- the applied voltage from the variable DC power supply 50 is applied so as to be deep, that is, to increase the absolute value of Vdc on the surface of the upper electrode 34.
- the plasma etching apparatus supplies, for example, H2 / Ar gas, CF4 / H2 / Ar gas, and CF4 / COS / Ar gas as processing gases into the chamber 10.
- the collision of ions with the surface of the electrode plate 36 is accelerated, and the amount of descent of the silicon forming the upper electrode 34 and the amount of descent of the electron beam are increased.
- argon ions collide with the surface of the electrode plate 36, and silicon forming the electrode plate 36 falls to the etching mask 203.
- a silicon-containing deposit 204 is deposited on the surface of the etching mask 203 made of polysilicon.
- the angle of the source select line can be made more vertical, or the line after etching can be made more beautifully.
- the plasma etching apparatus performs a deposition step of depositing a CF-based deposit by plasma with the second CF-based processing gas (Step S103).
- the plasma etching apparatus deposits a CF-based deposit on the upper portion of the etching mask using C4F6 / Ar / O2 gas. That is, the CF-based deposit is deposited on the line that has been cleaned by the deposition of the silicon-containing deposit.
- the plasma etching apparatus applies high frequency power from the first high frequency power supply 89 and connects the variable DC power supply 50 to the upper electrode 34 to apply a predetermined direct current (DC) voltage. At this time, the high frequency power for ion attraction is not applied from the second high frequency power supply 90.
- the plasma etching apparatus supplies the gas into the C4F6 / Ar / O2 gas chamber 10, for example. As a result, a CF diameter deposit is deposited on the etching mask.
- the plasma etching apparatus performs an etching step of etching the silicon oxide film with the plasma of the first CF-based gas using the etching mask on which the silicon-containing deposit is deposited as a mask (step S104).
- the plasma etching apparatus performs etching by using, for example, C4F6 / C4F8 / Ar / O2 gas as the first CF-based gas.
- the processing procedure shown in FIG. 3 is not limited to the above-described order, and may be appropriately changed within a range that does not contradict the processing contents.
- the deposition step of depositing the CF-based deposit by the plasma with the second CF-based processing gas is performed after the deposition step and before the etching step is described as an example.
- the present invention is not limited to this, and the deposition step for depositing the CF-based deposit may not be performed.
- the silicon-containing deposit is deposited on the etching mask surface by plasma with the processing gas while applying a negative DC voltage to the upper electrode made of silicon with respect to the processing substrate.
- the silicon oxide film is etched by plasma using the first CF-based gas.
- the angle of the source select line can be made more vertical, or the line after etching can be made more beautifully. That is, it is possible to perform etching with a high selectivity while maintaining the plasma resistance of the etching mask high.
- the mask selection ratio while maintaining the omission.
- the mask becomes thicker, the lines can be etched thicker, and the resistance to wiggling can be improved.
- a DC voltage having a predetermined polarity and magnitude is applied to the upper electrode 34 from the variable DC power supply 50.
- the self-bias voltage Vdc of the surface becomes deep enough to obtain a predetermined (moderate) sputtering effect on the surface of the upper electrode 34 that is the application electrode, that is, the surface of the electrode plate 36, that is, the surface of the upper electrode 34.
- the processing gas is selected from H2 / Ar gas, CF4 / H2 / Ar gas, and CF4 / COS / Ar gas. As a result, it is possible to reliably deposit a silicon-containing deposit on the etching mask.
- the CF-based deposit is deposited by plasma with the second CF-based processing gas after the deposition step and before the etching step.
- the mask selectivity can be further improved as compared with the case where no CF-based deposit is deposited.
- the first CF-based gas is C4F6 / C4F8 / Ar / O2 gas.
- the second CF-based gas is C4F6 / Ar / O2 gas.
- the CF-based deposit can be reliably deposited.
- Comparative Example 1 In Comparative Example 1, an etching step was performed on the processed substrate under the following conditions. (Etching step) Process gas: C4F6 / C4F8 / Ar / Os (13/24/600/27 sccm) Pressure: 2.7 Pa (20 mTorr) High frequency power from the first high frequency power source: 750 W High frequency power from the second high frequency power source: 500 W DC voltage to upper electrode: -150V Time: 16.5 seconds
- Example 1 In Example 1, an etching step was performed after sequentially performing a deposition step for depositing a silicon-containing deposit and a deposition step for depositing a CF-based deposit on the processing substrate. The etching step in Example 1 was performed in the same manner as in Comparative Example 1.
- Process gas H2 / CF4 / Ar (100/40/800 sccm) Pressure: 6.6 Pa (50 mTorr) High frequency power from the first high frequency power supply: 300 W High frequency power from the second high frequency power supply: 0 W DC voltage to the upper electrode: -900V Time: 10 seconds (Deposition step for depositing CF deposits) Process gas: C4F6 / Ar / O2 (40/800/30 sccm) Pressure: 3.3 Pa (25 mTorr) High frequency power from the first high frequency power source: 1250W High frequency power from the second high frequency power supply: 0 W DC voltage to upper electrode: -300V Time: 13.7 seconds
- FIG. 5 is a diagram showing an example of the structure of the processing substrate in Example 1 and Comparative Example 1.
- the processing substrate before processing, the processing substrate after etching in Comparative Example 1, the processing substrate after depositing the silicon-containing deposit in Example 1, and the processing substrate after etching in Example 1, It is the trace figure of the photograph which expanded the cross section (Cell), the cross section (SSL, a source selection line), and the upper surface 350,000 times.
- “initial” indicates a processing substrate before processing.
- “No deposition” indicates a processed substrate in a comparative example.
- “With deposition, after deposition” indicates the treated substrate after depositing the silicon-containing deposit in Example 1.
- After deposition and after etching” indicates the processed substrate after etching in Example 1.
- a cross section (Cell) shows the center part of a process board
- a cross section (SSL, a source select line) shows the edge part of a process board
- the remaining amount of the etching mask after etching is “19.8 nm”, the angle in SSL is “83.7 degrees”, and LWR and LER are “1.3 nm”. It was “2.5 nm”.
- the remaining amount of the etching mask after etching is “24.4 nm”, the angle in SSL is “84.2 degrees”, and the LWR and LER are “1.2 nm”. And “2.4 nm”.
- LWR (line width heightness) and LER (line edge heightness) are values representing the size of irregularities formed on the wall surface of a fine pattern such as a gate electrode or a line in the semiconductor field.
- LWR indicates a variation in pattern width caused by irregularities on the surface of the line.
- the line width dimension including the unevenness is measured at a plurality of locations at different locations, and the standard deviation is calculated.
- a value that is three times the standard deviation is used as the value of variation.
- LER determines a reference line at the end of the line, and measures a plurality of dimensions from the reference line to the unevenness of the end of the line at different locations, and the subsequent calculation is the same as LWR. It is the value of the degree of variation.
- Example 1 an etching mask is formed by depositing a silicon-containing deposit as compared with a case where no silicon-containing deposit is deposited. More can be left, and the mask selection ratio can be improved. Moreover, in the case shown in Example 1, it was possible to make the angle in SSL closer to the vertical compared to Comparative Example 1.
- Example 2 to Example 4 In Examples 2 to 4, the following process gas and process gas flow rates were used in the silicon deposition step. The other points are the same as in the first embodiment.
- Example 2 H2 / Ar (100/800 sccm)
- Example 3 H2 / CF4 / Ar (100/40/800 sccm)
- Example 4 COS / CF4 / Ar (20/40/800 sccm)
- FIG. 6 is a diagram showing a processing result in Comparative Example 1.
- FIG. 7 is a diagram illustrating a processing result in the second embodiment.
- FIG. 8 is a diagram illustrating a processing result in the third embodiment.
- FIG. 9 is a diagram illustrating a processing result in the fourth embodiment. 6 to 9, the height of the etching mask remaining after the etching is shown together with a cross-sectional view (Cell), a cross-section (SSL) after the etching, and a trace view of the photograph in which the upper surface is enlarged 350,000 times. , LWR, SWR, LER, and LWR, SWR and LER are shown together.
- SWR space width heightness
- SWR space width heightness
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Abstract
Description
第1の実施形態におけるプラズマエッチング方法は、1つの実施形態において、下地層と、シリコン酸化膜と、エッチングパターンが形成されているポリシリコンからなるエッチングマスクとが順に積層されている処理基板に対して、シリコンからなる上部電極に負の直流電圧を印加しながら処理ガスによるプラズマによりエッチングマスク表面にシリコン含有堆積物を堆積させる堆積ステップを含む。また、第1の実施形態におけるプラズマエッチング方法は、1つの実施形態において、シリコン含有堆積物が堆積したエッチングマスクをマスクとして第1のCF系ガスによるプラズマでシリコン酸化膜をエッチングするエッチングステップを含む。
図1は、第1の実施形態に係るプラズマエッチング方法に適用されるプラズマエッチング装置を単純化して模式的に示す断面図である。図1に示すように、プラズマエッチング装置は、下部電極であるサセプタ16に第1の高周波電源89からプラズマ生成用の例えば40MHzの高周波(RF)電力を印加するとともに、第2の高周波電源90からイオン引き込み用の例えば2MHzの高周波(RF)電力を印加する下部RF2周波印加タイプのプラズマエッチング装置であって、図示のように上部電極34に可変直流電源50を接続して所定の直流(DC)電圧が印加されるプラズマエッチング装置である。
図3は、第1の実施形態におけるプラズマエッチング装置によるプラズマエッチング処理の流れの一例を示すフローチャートである。以下に詳細に説明するように、プラズマエッチング装置は、下地層と、シリコン酸化膜と、エッチングパターンが形成されているポリシリコンからなるエッチングマスクとが順に積層されている処理基板に対して、一連の処理を実行する。
このように、第1の実施形態によれば、処理基板に対して、シリコンからなる上部電極に負の直流電圧を印加しながら処理ガスによるプラズマによりエッチングマスク表面にシリコン含有堆積物を堆積させ、シリコン含有堆積物が堆積したエッチングマスクをマスクとして第1のCF系ガスによるプラズマでシリコン酸化膜をエッチングする。この結果、ポリシリコンマスクをマスクとして用いる場合にマスク選択比を向上可能となる。すなわち、この結果、エッチングマスクの表面荒れを解消され、エッチングマスクの選択比が向上可能となる。更に、堆積ステップを行った後にエッチングを行うことで、ソースセレクトラインの角度をより垂直にすることが可能になったり、エッチング後のラインをより綺麗に作成可能になったりする。すなわち、エッチングマスクの耐プラズマ性を高く維持して高選択比でエッチングすることが可能となる。
以下に、開示のプラズマエッチング方法について、実施例をあげて更に詳細に説明する。ただし、開示のプラズマエッチング方法は、下記の実施例に限定されるものではない。
比較例1では、処理基板に対して、下記の条件でエッチングステップを行った。
(エッチングステップ)
処理ガス:C4F6/C4F8/Ar/Os(13/24/600/27sccm)
圧力:2.7Pa(20mTorr)
第1の高周波電源からの高周波電力:750W
第2の高周波電源からの高周波電力:500W
上部電極への直流電圧:-150V
時間:16.5秒
実施例1では、処理基板に対して、シリコン含有堆積物を堆積させる堆積ステップと、CF系堆積物を堆積させる堆積ステップとを順に行った上で、エッチングステップを行った。なお、実施例1におけるエッチングステップは、比較例1と同様に行った。
(シリコン含有堆積物を堆積させる堆積ステップ)
処理ガス:H2/CF4/Ar(100/40/800sccm)
圧力:6.6Pa(50mTorr)
第1の高周波電源からの高周波電力:300W
第2の高周波電源からの高周波電力:0W
上部電極への直流電圧:-900V
時間:10秒
(CF系堆積物を堆積させる堆積ステップ)
処理ガス:C4F6/Ar/O2(40/800/30sccm)
圧力:3.3Pa(25mTorr)
第1の高周波電源からの高周波電力:1250W
第2の高周波電源からの高周波電力:0W
上部電極への直流電圧:-300V
時間:13.7秒
実施例2~実施例4では、シリコン堆積ステップにおいて、以下に示す処理ガス及び処理ガスの流量を用いた。その他の点については、実施例1と同様である。
実施例2:H2/Ar(100/800sccm)
実施例3:H2/CF4/Ar(100/40/800sccm)
実施例4:COS/CF4/Ar(20/40/800sccm)
32 ガス供給ライン
34 上部電極
36 電極板
50 可変直流電源
51 コントローラ
87 整合器
88 整合器
89 高周波電源
90 高周波電源
95 制御部
96 ユーザーインターフェース
97 記憶部
203 エッチングマスク
204 シリコン含有堆積物
Claims (5)
- 下地層と、シリコン酸化膜と、エッチングパターンが形成されているポリシリコンからなるエッチングマスクとが順に積層されている処理基板に対して、シリコンからなる上部電極に負の直流電圧を印加しながら処理ガスによるプラズマによりエッチングマスク表面にシリコン含有堆積物を堆積させる堆積ステップと、
前記シリコン含有堆積物が堆積したエッチングマスクをマスクとして第1のCF系ガスによるプラズマで前記シリコン酸化膜をエッチングするエッチングステップと
を含むプラズマエッチング方法。 - 前記処理ガスは、H2/Arガス、CF4/H2/Arガス及びCF4/COS/Arガスから選択されることを特徴とする請求項1に記載のプラズマエッチング方法。
- 前記堆積ステップの後であって前記エッチングステップの前に、第2のCF系処理ガスによるプラズマによりCF系堆積物を堆積させる堆積ステップを更に含むことを特徴とする請求項1に記載のプラズマエッチング方法。
- 前記第1のCF系ガスがC4F6/C4F8/Ar/O2ガスであることを特徴とする請求項1に記載のプラズマエッチング方法。
- 前記第2のCF系ガスがC4F6/Ar/O2ガスであることを特徴とする請求項3に記載のプラズマエッチング方法。
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Citations (3)
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JP2011199243A (ja) * | 2010-02-24 | 2011-10-06 | Tokyo Electron Ltd | エッチング処理方法 |
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JP2012195576A (ja) * | 2011-02-28 | 2012-10-11 | Tokyo Electron Ltd | プラズマエッチング方法及び半導体装置の製造方法並びにコンピュータ記憶媒体 |
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US7988816B2 (en) | 2004-06-21 | 2011-08-02 | Tokyo Electron Limited | Plasma processing apparatus and method |
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