JP6604476B2 - 素子チップの製造方法 - Google Patents
素子チップの製造方法Info
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- JP6604476B2 JP6604476B2 JP2016048006A JP2016048006A JP6604476B2 JP 6604476 B2 JP6604476 B2 JP 6604476B2 JP 2016048006 A JP2016048006 A JP 2016048006A JP 2016048006 A JP2016048006 A JP 2016048006A JP 6604476 B2 JP6604476 B2 JP 6604476B2
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Description
本発明に係る一実施形態を、図1Aおよび図1Bを参照しながら説明する。図1Aおよび図1Bは、本実施形態に係る製造方法の各工程を示す断面図である(図1A(a)〜図1B(f))。
(1)準備工程
まず、ダイシングの対象となる基板10を準備する(図1A(a))。基板10は、第1主面10Xおよび第2主面10Yを備えており、半導体層である第1層11と、第1層11の第1主面10X側に形成された絶縁膜を含む第2層12と、を備える。また、基板10は、分割領域R1と、分割領域R1によって画定される複数の素子領域R2とに区画されている。したがって、第1層11は、分割領域R1に対応する第1分割領域111と、素子領域R2に対応する複数の第1素子領域112とを備える。第2層12は、分割領域R1に対応する第2分割領域121と、素子領域R2に対応する複数の第2素子領域122とを備える。基板10の素子領域R2(第1素子領域112および第2素子領域122)には、電子部品素子、MEMS等の回路層(いずれも図示せず)が形成されていてもよい。
レーザスクライブ工程では、第2分割領域121に第1主面10X側からレーザ光Lを照射して、第2分割領域121の一部を除去し、第1分割領域111が一部露出した開口10Aを形成する(図1A(b))。言い換えれば、レーザスクライブ工程では、第1分割領域111の一部を露出させて、露出部111aを形成する。レーザ光Lの中心波長は特に限定されず、例えば350〜600nmである。
レーザスクライブ工程の後、第2素子領域122の表面と露出部111aと第2素子領域122の端面とに、保護膜13を堆積させる(図1A(c))。保護膜13の堆積は、例えば、基板10を第4プラズマP4に晒すことにより行うことができる。この方法は、プラズマCVDといわれ、比較的低温かつ速いスピードで薄膜を形成できる点で優れている。
保護膜堆積工程の後、基板10を第1プラズマP1に晒すことにより、保護膜13を異方的にエッチングする(図1B(d))。異方性エッチングにより、露出部111aに堆積した保護膜13の一部および第2素子領域122の表面に堆積した保護膜13が除去される。一方、第2素子領域122の端面は、保護膜13に被覆されたままである。
保護膜エッチング工程の後、プラズマダイシング工程の前に、基板10を第2プラズマP2に晒す(図1B(e))。このとき、第2素子領域122および保護膜13は、マスクとして機能する。しかし、等方的に進行するエッチング条件でエッチングすることにより、第1分割領域111の保護膜13で覆われていない部分に加えて、保護膜13に覆われる部分もエッチングされる。図1B(e)では、第1分割領域111の保護膜13で覆われていた部分の全面が、下方にエッチングされている。等方エッチング工程の条件は特に限定されないが、第1分割領域111がエッチングされ、かつ、エッチングが等方的に進行し易い点で、六フッ化硫黄(SF6)等を含むプロセスガスが好ましく用いられる。
次に、基板10を第3プラズマP3に晒す(図1B(f))。第3プラズマP3は、第1分割領域111が異方的にエッチングされる条件で発生させる。例えば、六フッ化硫黄(SF6)等を含むプロセスガスを用いるとともに、高周波電極部220に高周波電力を印加して、バイアス電圧をかける。これにより、基材10の厚みに平行な方向に、異方的にエッチングが行われる。上記エッチング条件は、第1層11の材質に応じて適宜選択することができる。第1層11がSiの場合、第1分割領域111のエッチングには、いわゆるボッシュプロセスを用いることができる。ボッシュプロセスでは、堆積膜堆積ステップと、堆積膜エッチングステップと、Siエッチングステップとを順次繰り返すことにより、第1分割領域111を深さ方向に掘り進む。
本発明に係る他の実施形態を、図3Aおよび図3Bを参照しながら説明する。図3Aおよび図3Bは、本実施形態に係る製造方法の各工程を示す断面図である(図3A(a)〜図3B(f))。
本実施形態は、レーザスクライブ工程(図3A(b))において、第1分割領域111の表面よりも深い位置までレーザスクライブすること、および、等方エッチング工程(図3B(e))において、第1分割領域111の保護膜13で覆われていた部分の一部が、エッチングされること以外、第1実施形態と同様である。つまり、本実施形態の等方エッチング工程における保護膜13の厚み方向のエッチング量は、保護膜13の厚みよりも少ない。
10A:開口
10X:第1主面
10Y:第2主面
11:第1層
111:第1分割領域
111a:露出部
112:第1素子領域
112X:積層面
112Y:積層面とは反対側の面
12:第2層
121:第2分割領域
122:第2素子領域
13:保護膜
110:素子チップ
20:搬送キャリア
21:フレーム
21a:ノッチ
21b:コーナーカット
22:支持部材
22a:粘着面
22b:非粘着面
200:プラズマ処理装置
203:真空チャンバ
203a:ガス導入口
203b:排気口
208:誘電体部材
209:アンテナ
210A:第1高周波電源
210B:第2高周波電源
211:ステージ
212:プロセスガス源
213:アッシングガス源
214:減圧機構
215:電極層
216:金属層
217:基台
218:外周部
219:ESC電極
220:高周波電極部
221:昇降ロッド
222:支持部
223A、223B:昇降機構
224:カバー
224W:窓部
225:冷媒循環装置
226:直流電源
227:冷媒流路
228:制御装置
229:外周リング
30:基板
31:第1層
32:第2層
130:素子チップ
Claims (3)
- 第1主面および第2主面を備え、半導体層である第1層と、前記第1層の前記第1主面側に形成された絶縁膜を含む第2層と、を備える基板であって、複数の素子領域と、前記素子領域を画定する分割領域を備える基板を準備する工程と、
前記分割領域に前記第1主面側からレーザ光を照射して、前記分割領域に前記第1層が露出する露出部を備える開口を形成するレーザスクライブ工程と、
前記レーザスクライブ工程の後、前記素子領域および前記分割領域に保護膜を堆積させる保護膜堆積工程と、
前記保護膜堆積工程の後、前記基板を第1プラズマに晒すことにより前記保護膜を異方的にエッチングして、前記分割領域に堆積した前記保護膜の一部および前記素子領域に堆積した前記保護膜を除去するとともに、前記素子領域の端面を覆う前記保護膜を残存させる、保護膜エッチング工程と、
前記保護膜エッチング工程の後、前記基板を第2プラズマに晒すことにより前記分割領域を等方的にエッチングする等方エッチング工程と、
前記等方エッチング工程の後、前記第2主面を支持部材で支持した状態で前記基板を第3プラズマに晒すことにより、前記分割領域を異方的にエッチングして、前記基板を、前記素子領域を備える複数の素子チップに分割するプラズマダイシング工程と、を備える、素子チップの製造方法。 - 前記保護膜堆積工程では、フッ化炭素を含むプロセスガスを原料として第4プラズマを発生させる、請求項1に記載の素子チップの製造方法。
- 前記等方エッチング工程では、六フッ化硫黄を含むプロセスガスを原料として前記第2プラズマを発生させる、請求項1または2に記載の素子チップの製造方法。
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