WO2012101957A1 - シリコン単結晶ウェーハの製造方法及びアニールウェーハ - Google Patents
シリコン単結晶ウェーハの製造方法及びアニールウェーハ Download PDFInfo
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- WO2012101957A1 WO2012101957A1 PCT/JP2012/000053 JP2012000053W WO2012101957A1 WO 2012101957 A1 WO2012101957 A1 WO 2012101957A1 JP 2012000053 W JP2012000053 W JP 2012000053W WO 2012101957 A1 WO2012101957 A1 WO 2012101957A1
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- 239000013078 crystal Substances 0.000 title claims abstract description 67
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 55
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 55
- 239000010703 silicon Substances 0.000 title claims abstract description 55
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 230000007547 defect Effects 0.000 claims abstract description 55
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 50
- 238000010438 heat treatment Methods 0.000 claims abstract description 31
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 28
- 239000001301 oxygen Substances 0.000 claims abstract description 28
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 27
- 238000000034 method Methods 0.000 claims abstract description 26
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 25
- 235000012431 wafers Nutrition 0.000 claims description 103
- 230000007935 neutral effect Effects 0.000 claims description 2
- 238000005121 nitriding Methods 0.000 abstract description 6
- 238000009826 distribution Methods 0.000 abstract description 5
- 230000000052 comparative effect Effects 0.000 description 7
- 239000002019 doping agent Substances 0.000 description 6
- 238000011156 evaluation Methods 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 4
- 239000002344 surface layer Substances 0.000 description 4
- 230000008034 disappearance Effects 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000002244 precipitate Substances 0.000 description 2
- 229910052787 antimony Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 230000008685 targeting Effects 0.000 description 1
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- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
- C30B33/02—Heat treatment
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/02—Elements
- C30B29/06—Silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/30—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface
- H01L29/32—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface the imperfections being within the semiconductor body
Definitions
- the present invention relates to a method for manufacturing a silicon single crystal wafer for IGBT, for example.
- a wafer for a vertical silicon device such as IGBT (Insulated Gate Bipolar Transistor)
- a wafer of N type conductivity type manufactured by FZ method Floating Zone Method
- An IGBT is a device that uses a wafer in the vertical direction, and is therefore affected by the quality of the wafer bulk. For this reason, the FZ method in which a wafer with few defects is easily obtained is used.
- Patent Document 1 wafers manufactured by the CZ method (Czochralski Method) with a defect region of N region, nitrogen-doped, low oxygen concentration (Patent Document 1), and wafers subjected to RTA treatment with N region, low oxygen concentration (Patent Document 1) Patent Document 2) has been proposed.
- the defect region of the wafer in the CZ method changes greatly depending on the pulling speed of the silicon single crystal ingot.
- the glow-in defects considered as voids which are point defects called vacancy
- the region where these defects exist is the V region.
- the OSF ring generated in the periphery of the crystal contracts toward the inside of the crystal and eventually disappears.
- an N (Neutral) region in which excess or deficiency of vacancy or interstitial silicon (interstitial silicon) is small appears.
- the width of the pulling speed for obtaining the silicon single crystal in the N region is narrow and the yield is poor, so that the wafer is high-cost.
- the above-mentioned wafer is such that a defect in the bulk is made defect-free by performing nitrogen doping, RTA treatment, and neutron irradiation on the N region, low oxygen concentration wafer, and the in-plane resistivity distribution is improved.
- the premise was the use of wafers in the N region. Therefore, the cost is high and the yield is poor.
- the present invention has been made in view of the above-described problems, and uses a V-region wafer manufactured by a CZ method capable of handling a large diameter to make defects in the bulk defect-free and further perform neutron irradiation. Even if it is not, it aims at providing the method of manufacturing the low-cost silicon single crystal wafer applicable for IGBT by setting it as the in-plane resistivity distribution comparable to the case where neutron irradiation is performed.
- the present invention provides an oxygen concentration of less than 7 ppma obtained from a V-region silicon single crystal ingot grown by the Czochralski method (JEIDA: using a conversion factor by the Japan Electronics Industry Promotion Association), A silicon single-crystal wafer having a nitrogen concentration of 1 ⁇ 10 13 to 1 ⁇ 10 14 atoms / cm 3 is heat-treated at 1150 to 1300 ° C. for 1 to 120 minutes in a non-nitriding atmosphere. A method for producing a single crystal wafer is provided.
- the silicon single crystal wafer described above not only the surface layer but also the bulk can be obtained by performing a heat treatment at 1150 to 1300 ° C. for 1 to 120 minutes in a non-nitriding atmosphere even if a silicon single crystal in the V region is used. It is possible to effectively reduce the crystal defects therein, and to improve the in-plane variation of the resistivity of the wafer. For this reason, in the manufacturing method of the present invention, a silicon single crystal wafer in the V region with good productivity is used, and further, in-plane variation of resistivity is improved without performing neutron irradiation, and a wafer suitable for IGBT is manufactured. Therefore, the productivity of manufacturing the wafer for IGBT can be improved and the cost can be reduced.
- the density of crystal defects having a defect size of 15 nm or more in the bulk of the silicon single crystal wafer is 2 ⁇ 10 6 / cm 3 or less by performing the heat treatment.
- the in-plane variation in resistivity of the silicon single crystal wafer is 5% or less by performing the heat treatment.
- the in-plane variation of resistivity can be improved by heat treatment without performing neutron irradiation, and a high-quality wafer can be obtained at low cost.
- the silicon single crystal wafer has an N conductivity type and is used for an IGBT device. If it is the manufacturing method of this invention, the wafer used for such a device for IGBT can be manufactured at low cost with high productivity.
- the present invention also provides a silicon single crystal wafer having an oxygen concentration of less than 7 ppma and a nitrogen concentration of 1 ⁇ 10 13 to 1 ⁇ 10 14 atoms / cm 3 obtained from a V region silicon single crystal ingot grown by the Czochralski method.
- Such an annealed wafer is suitable as an IGBT wafer because it is obtained from a V-region silicon single crystal ingot that can be grown with a high yield and is low in cost and has very few crystal defects in the bulk.
- the in-plane variation in resistivity of the annealed wafer is preferably 5% or less.
- the annealed wafer has an N conductivity type and is used for an IGBT device.
- the annealed wafer of the present invention is suitable for use in a device for IGBT.
- an annealed wafer for IGBT can be manufactured with high productivity and low cost using a V-region silicon single crystal wafer.
- FIG. (A) The graph which shows the size of the defect in a wafer surface
- (b) The figure which shows the defect area
- the annealed wafer of the present invention is silicon having an oxygen concentration of less than 7 ppma and a nitrogen concentration of 1 ⁇ 10 13 to 1 ⁇ 10 14 atoms / cm 3 obtained from a V-region silicon single crystal ingot grown by the Czochralski method.
- An annealed wafer manufactured by heat-treating a single crystal wafer, and the density of crystal defects having a defect size of 15 nm or more in the bulk of the annealed wafer is 2 ⁇ 10 6 / cm 3 or less.
- the in-plane variation in resistivity of the annealed wafer of the present invention is preferably 5% or less. As long as the uniformity of resistivity is improved to the above range by heat treatment without using such neutron irradiation, a high-quality and inexpensive IGBT wafer can be obtained.
- Such an annealed wafer of the present invention is suitable as a wafer used for an IGBT device if the conductivity type is N-type.
- an oxygen concentration of less than 7 ppma and a nitrogen concentration of 1 ⁇ 10 13 to 1 ⁇ 10 14 atoms / cm obtained from a V region silicon single crystal ingot grown by the Czochralski method.
- the silicon single crystal wafer 3 is heat-treated at 1150 to 1300 ° C. for 1 to 120 minutes in a non-nitriding atmosphere.
- a silicon single crystal ingot is grown by the MCZ method so that the oxygen concentration is less than 7 ppma while controlling the pulling rate so that the defect region becomes the V region.
- nitrogen is doped so that the nitrogen concentration is 1 ⁇ 10 13 to 1 ⁇ 10 14 atoms / cm 3 .
- the conductivity type is N-type, P, As, Sb, or the like can be doped as a dopant.
- the silicon concentration is less than 7 ppma
- the nitrogen concentration is 1 ⁇ 10 13 to 1 ⁇ 10 14 atoms / cm 3
- the entire surface is V region silicon.
- a single crystal wafer can be produced.
- the N region wafer is conventionally used for the IGBT.
- the V region wafer can be used in the present invention, the margin of the pulling speed at the time of growing the ingot can be increased, and the productivity of the wafer manufacturing can be increased. Will improve.
- the CZ method since the CZ method is used, it is easy to obtain a large-diameter wafer.
- the nitrogen concentration is less than 1 ⁇ 10 13 atoms / cm 3 , the size of oxygen precipitates on the wafer becomes large, and it becomes difficult to eliminate defects inside the bulk by a heat treatment in a later step.
- the nitrogen concentration is higher than 1 ⁇ 10 14 atoms / cm 3 , an OSF region is formed on the outer periphery of the wafer.
- the oxygen concentration of the silicon single crystal wafer of the present invention is less than 7 ppma, preferably 5 ppma or less. With such an extremely low oxygen concentration, defects in the wafer can be sufficiently eliminated by heat treatment, When the oxygen concentration is 7 ppma or more, defects are difficult to disappear by heat treatment, and many defects in the bulk remain in particular. As described above, in the present invention, when the oxygen concentration and the nitrogen concentration are within the above ranges, the size of the oxygen precipitate in the wafer is 250a. u. It becomes smaller as follows, and the defects are easily eliminated by the subsequent heat treatment.
- such a silicon single crystal wafer is heat-treated at 1150 to 1300 ° C. for 1 to 120 minutes in a non-nitriding atmosphere such as Ar, H 2 , Ar + O 2 or the like in a vertical heat treatment furnace, for example.
- a non-nitriding atmosphere such as Ar, H 2 , Ar + O 2 or the like
- oxygen in the surface layer diffuses outward, the oxide film on the inner wall of the glow-in defect in the bulk dissolves, the cavity is reduced, and the cavity is filled, so that a crystal having a defect size of 15 nm or more in the bulk is obtained.
- the density of defects can be 2 ⁇ 10 6 / cm 3 or less.
- a nitride film is formed on the wafer surface, preventing oxygen from diffusing outwardly, and defects cannot be sufficiently eliminated.
- the heat treatment temperature is less than 1150 ° C., the disappearance of defects is insufficient, and when it exceeds 1300 ° C., slip dislocation may occur.
- the heat treatment temperature is preferably 1200 ° C. or lower because slip dislocation can be reliably prevented. If the heat treatment time is 1 minute or longer, the disappearance of defects can be effectively achieved, and if it is 120 minutes or shorter, it is sufficient, and the occurrence of slip dislocation can be suppressed.
- the in-plane variation of the resistivity of the wafer can be reduced to 5% or less.
- neutron irradiation is required, and this processing has increased the cost.
- the present inventors have found a method of uniforming resistivity by heat treatment from the following knowledge.
- Diffusion of a dopant such as P is not performed by a single dopant, but by a pair of dopant and I (Si) (interstitial silicon).
- I dopant and I (Si) (interstitial silicon).
- vacancy when vacancy is present, it facilitates diffusion of dopant + I (Si). Therefore, when the above-described high-temperature heat treatment is performed on the nitrogen-doped + low-oxygen wafer according to the present invention, out-diffusion of nitrogen occurs, and more oxygen is generated due to less oxygen. It has been found that the generation of this large amount of vacancy promotes the diffusion of dopant + I (Si) and the resistivity changes in a uniform direction.
- Such a heat treatment according to the present invention makes it possible to equalize the resistivity equal to or higher than that of neutron irradiation, and effectively reduce the manufacturing cost of the IGBT wafer.
- a wafer suitable for use in a device for IGBT can be manufactured with low cost and high productivity by making the conductivity type N type.
- the wafer manufactured by the manufacturing method of the annealed wafer and the silicon single crystal wafer of the present invention can be used for devices other than IGBTs.
- Example 1 Comparative Example 1
- Example 2 Three types of silicon single crystal wafers obtained by the Czochralski method and having a nitrogen concentration of 5 ⁇ 10 13 atoms / cm 3 and a V region with oxygen concentrations of 4 ppma, 6 ppma, and 8 ppma (JEIDA) are prepared in an Ar atmosphere. Heat treatment was performed at 1170 ° C. for 1 hour.
- MO601 made by Mitsui Metals.
- MO601 can evaluate defects near the surface layer of 5 ⁇ m.
- defects in the bulk were evaluated by MO 601 after polishing in the depth direction (targeting 50 ⁇ m and 100 ⁇ m). This evaluation method can evaluate the entire polished surface. The evaluation results are shown in FIG.
- the oxygen concentration is 8 ppma, defects remain particularly in the bulk even when heat treatment is performed, and the defect density in the bulk is set to 2 ⁇ 10 6 / cm 3 or less. I could't.
- the defect density is 2 ⁇ 10 6 / cm 3 or less, and in particular in the case of 5 ppma or less, no defect was detected in the bulk. Therefore, it can be seen that the oxygen concentration is preferably less than 7 ppma, particularly 5 ppma or less.
- Example 2 comparative example 2 (Proof of critical significance of nitrogen concentration)
- a silicon single crystal wafer in the V region having an oxygen concentration of 4 ppma (JEIDA) obtained by the Czochralski method has a nitrogen concentration of less than 1 ⁇ 10 13 atoms / cm 3 , 2 ⁇ 10 13 atoms / cm 3 , 5 ⁇
- 10 13 atoms / cm 3 and 2 ⁇ 10 14 atoms / cm 3 were prepared, and heat treatment was performed at 1170 ° C. for 1 hour in an Ar atmosphere.
- Table 2 shows the results of defect evaluation performed in the same manner as in Example 1 and Comparative Example 1.
- FIG. 2A shows a graph showing the size of defects in the silicon single crystal before the heat treatment
- FIG. 2B shows the result of measuring the defect region on the surface by MO601.
- the defect size in the central portion decreases as the nitrogen concentration increases.
- FIG. 2 (b) this also applies to a wafer obtained from a single crystal pulled up under the same conditions.
- the nitrogen concentration is 2 ⁇ 10 14 atoms / cm 3
- the nitrogen concentration is excessive, and the OSF region is formed on the outer periphery of the V region.
- the nitrogen concentration exceeded 1 ⁇ 10 14 atoms / cm 3
- an OSF region was formed on the outer periphery.
- Example 3 A V-region silicon single crystal wafer having a nitrogen concentration of 5 ⁇ 10 13 atoms / cm 3 and an oxygen concentration of 4 ppma (JEIDA) obtained by the Czochralski method is prepared and heat-treated for 1 hour in an Ar atmosphere. went.
- the heat treatment temperatures were higher than 1130, 1150, 1170, 1200 and 1300 ° C. (> 1300 ° C.), respectively.
- Defect evaluation was performed in the same manner as in Example 1 and Comparative Example 1. Further, the in-plane resistivity distribution was measured on the plane SR. The results are shown in Table 3.
- the present invention is not limited to the above embodiment.
- the above-described embodiment is an exemplification, and the present invention has substantially the same configuration as the technical idea described in the claims of the present invention, and any device that exhibits the same function and effect is the present invention. It is included in the technical scope of the invention.
Abstract
Description
このN領域のシリコン単結晶を得るための引き上げ速度の幅は狭く、歩留まりが悪いため、高コストのウェーハとなるが、結晶中に欠陥がほとんど無いためIGBT用のウェーハとして用いられていた。
このため、IGBT用のウェーハとして、面内抵抗率分布が5%以下のウェーハも提案されている(特許文献3、特許文献4)。
このような結晶欠陥の密度とすることで、IGBT等に適した高品質のウェーハとすることができる。
このように、本発明の方法であれば、中性子照射を行うことなく、熱処理で抵抗率の面内ばらつきを改善することができ、低コストで高品質のウェーハにすることができる。
本発明の製造方法であれば、このようなIGBT向けデバイスに用いるウェーハを低コストで生産性良く製造することができる。
このようなウェーハであれば、デバイスを作製した場合、故障の発生を防止でき、歩留まりが向上するウェーハとなる。
このように、本発明のアニールウェーハは、IGBT向けデバイスに用いるのに好適である。
このような中性子照射を用いることなく熱処理により抵抗率の均一性が上記範囲にまで向上されたウェーハであれば、高品質で安価なIGBT用ウェーハとすることができる。
そして、このように育成したシリコン単結晶インゴットをスライスし、研磨等を行うことで、酸素濃度7ppma未満、窒素濃度1×1013~1×1014atoms/cm3で、全面がV領域のシリコン単結晶ウェーハを作製することができる。
このように、本発明において、酸素濃度と窒素濃度を上記範囲とすることで、ウェーハ中の酸素析出物サイズが、MO601(三井金属製)により、赤外線の散乱強度で評価すると250a.u.以下と小さくなり、その後の熱処理により欠陥を消滅しやすくなる。
この熱処理において、表層の酸素が外方拡散し、さらに、バルク中のグローイン欠陥の内壁の酸化膜が溶解し、空洞の縮小、さらには空洞が埋まることによって、バルク中の欠陥サイズ15nm以上の結晶欠陥の密度を2×106/cm3以下とすることができる。
また、熱処理温度は、1150℃未満では欠陥の消滅が不十分で、1300℃を超えると、スリップ転位が発生することがある。さらに、この熱処理温度は1200℃以下がスリップ転位発生を確実に防止できるため、好ましい。熱処理時間は、1分以上であれば欠陥の消滅を効果的に達成でき、120分以下であれば十分であり、またスリップ転位の発生を抑制できる。
従来では、このような面内均一な抵抗率を得るためには、中性子照射が必要で、この処理によりコストが高くなっていた。しかし、本発明者らは、以下のような知見から熱処理による抵抗率均一化の方法を見出した。
従って、本発明の窒素ドープ+低酸素ウェーハに対して上記の高温熱処理を行うと、窒素の外方拡散が起こり、さらに、酸素が少ないため、過剰なVacancyが発生する。この大量のVacancyの発生により、ドーパント+I(Si)の拡散が促進され、抵抗率が均一方向に変化することを見出した。
このような本発明の熱処理により中性子照射と同等以上の抵抗率均一化が可能で、IGBT用ウェーハの製造コストを効果的に低減することができる。
ただし、本発明のアニールウェーハ及びシリコン単結晶ウェーハの製造方法で製造したウェーハは、IGBT以外のデバイスにも用いることができる。
(実施例1、比較例1)
(酸素濃度の臨界的意義の証明)
チョクラルスキー法により得られた、窒素濃度5×1013atoms/cm3でV領域のシリコン単結晶ウェーハを、酸素濃度が4ppma,6ppma,8ppma(JEIDA)の三種類用意して、Ar雰囲気下、1170℃、1時間の熱処理を行った。
評価の際、バルク中の欠陥評価は、深さ方向研磨(50μm、100μm狙い)し、MO601で評価を行った。この評価方法は研磨面の全面評価が可能である。
評価結果を図1,表1に示す。
(窒素濃度の臨界的意義の証明)
チョクラルスキー法により得られた、酸素濃度が4ppma(JEIDA)でV領域のシリコン単結晶ウェーハを、窒素濃度が1×1013atoms/cm3未満、2×1013atoms/cm3、5×1013atoms/cm3、2×1014atoms/cm3の4種類用意して、Ar雰囲気下、1170℃、1時間の熱処理を行った。
実施例1、比較例1と同様の方法で欠陥評価を行った結果を表2に示す。
図2(a)に熱処理前のシリコン単結晶中の欠陥のサイズを示すグラフと、(b)その表面の欠陥領域をMO601で測定した結果を示す。図2(a)に示すように、窒素濃度が高くなると中心部分の欠陥サイズが小さくなるが、図2(b)に示すように、同じ条件で引き上げた単結晶から得られたウェーハにもかかわらず、窒素濃度が2×1014atoms/cm3の方は、窒素濃度が過剰で、V領域の外周にOSF領域が形成されてしまっている。このように、窒素濃度が1×1014atoms/cm3を超えると、外周にOSF領域が形成された。
チョクラルスキー法により得られた、窒素濃度が5×1013atoms/cm3、酸素濃度が4ppma(JEIDA)でV領域のシリコン単結晶ウェーハを用意して、Ar雰囲気下、1時間の熱処理を行った。熱処理温度は1130、1150、1170、1200、1300℃より高い温度(>1300℃)でそれぞれ行った。
実施例1、比較例1と同様の方法で欠陥評価を行った。また、面内抵抗率分布を平面SRで測定した。結果を表3に示す。
Claims (7)
- チョクラルスキー法により育成されたV領域のシリコン単結晶インゴットから得られた酸素濃度7ppma未満、窒素濃度1×1013~1×1014atoms/cm3のシリコン単結晶ウェーハに対して、非窒化性雰囲気下、1150~1300℃で、1~120分の熱処理を行うことを特徴とするシリコン単結晶ウェーハの製造方法。
- 前記熱処理を行うことにより、前記シリコン単結晶ウェーハのバルク中の欠陥サイズ15nm以上の結晶欠陥の密度を2×106/cm3以下とすることを特徴とする請求項1に記載のシリコン単結晶ウェーハの製造方法。
- 前記熱処理を行うことにより、前記シリコン単結晶ウェーハの抵抗率の面内ばらつきを5%以下とすることを特徴とする請求項1又は請求項2に記載のシリコン単結晶ウェーハの製造方法。
- 前記シリコン単結晶ウェーハを、導電型がN型で、IGBT向けデバイスに用いるものとすることを特徴とする請求項1乃至請求項3のいずれか一項に記載のシリコン単結晶ウェーハの製造方法。
- チョクラルスキー法により育成されたV領域のシリコン単結晶インゴットから得られた酸素濃度7ppma未満、窒素濃度1×1013~1×1014atoms/cm3のシリコン単結晶ウェーハを熱処理して製造されたアニールウェーハであって、該アニールウェーハのバルク中の欠陥サイズ15nm以上の結晶欠陥の密度が2×106/cm3以下であることを特徴とするアニールウェーハ。
- 前記アニールウェーハの抵抗率の面内ばらつきが、5%以下であることを特徴とする請求項5に記載のアニールウェーハ。
- 前記アニールウェーハは、導電型がN型で、IGBT向けデバイスに用いるものであることを特徴とする請求項5又は請求項6に記載のアニールウェーハ。
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