WO2011072042A2 - Low damage photoresist strip method for low-k dielectrics - Google Patents

Low damage photoresist strip method for low-k dielectrics Download PDF

Info

Publication number
WO2011072042A2
WO2011072042A2 PCT/US2010/059517 US2010059517W WO2011072042A2 WO 2011072042 A2 WO2011072042 A2 WO 2011072042A2 US 2010059517 W US2010059517 W US 2010059517W WO 2011072042 A2 WO2011072042 A2 WO 2011072042A2
Authority
WO
WIPO (PCT)
Prior art keywords
plasma
work piece
temperature
gas
fluorine
Prior art date
Application number
PCT/US2010/059517
Other languages
English (en)
French (fr)
Other versions
WO2011072042A3 (en
Inventor
David Cheung
Ted Li
Anirban Guha
Kirk Ostrowski
Original Assignee
Novellus Systems, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Novellus Systems, Inc. filed Critical Novellus Systems, Inc.
Priority to KR1020127015129A priority Critical patent/KR101908737B1/ko
Priority to JP2012543254A priority patent/JP5911068B2/ja
Priority to CN201080056102.5A priority patent/CN102792423B/zh
Priority to SG2012040929A priority patent/SG181165A1/en
Publication of WO2011072042A2 publication Critical patent/WO2011072042A2/en
Publication of WO2011072042A3 publication Critical patent/WO2011072042A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31058—After-treatment of organic layers
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • G03F7/42—Stripping or agents therefor
    • G03F7/427—Stripping or agents therefor using plasma means only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02043—Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H01L21/02046—Dry cleaning only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H01L21/02312—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a gas or vapour
    • H01L21/02315—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67207—Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures

Definitions

  • the present invention pertains to methods for stripping photo-resist material and removing etch-related residues from the surface of a partially fabricated integrated circuit in preparation for further processing.
  • Damascene processing techniques are often preferred methods in many modern integrated circuit manufacturing schemes because it requires fewer processing steps and offers a higher yield than other methods. Damascene processing involves forming metal conductors on integrated circuits by forming inlaid metal lines in trenches and vias in a dielectric layer (inter-metal dielectric). As part of the Damascene process, a layer of photoresist is deposited on a dielectric layer. The photoresist is a light-sensitive organic polymer which can be "spun on” in liquid form and dries to a solid thin film.
  • the photosensitive photoresist is then patterned using light through the mask and wet solvent.
  • a plasma etching process (dry etch) is then used to etch exposed portions of dielectric and transfer the pattern into the dielectric, forming vias and trenches in the dielectric layer.
  • the photoresist must be stripped and any etch-related residues must be thoroughly removed before subsequent processing to avoid embedding impurities in the device.
  • Conventional processes for stripping photoresist employ a plasma formed from a mixture of gases with the presence of oxygen in the plasma. The highly reactive oxygen based plasma reacts with and oxidizes the organic photoresist to form volatile components that are carried away from the wafer surface.
  • Low-k materials have been used as inter-metal and/or inter-layer dielectrics between conductive interconnects in many modern devices to reduce the delay in signal propagation due to capacitive effects.
  • low-k dielectrics are silicon-oxide based materials with some amount of incorporated carbon, commonly referred to as carbon doped oxide (CDO). It is believed, although not necessarily proven, that the oxygen scavenges or removes carbon from the low-k materials.
  • the present invention addresses the aforementioned need by providing improved methods for stripping photoresist and removing etch-related residues from dielectric materials.
  • methods involve removing material from a dielectric layer using a hydrogen-based etch process employing a weak oxidizing agent and fluorine-containing compound.
  • Substrate temperature is maintained at a level of about 160 °C or less, e.g., less than about 90 °C.
  • the methods involve introducing gas comprising a weak oxidizing agent, fluorine-containing compound and hydrogen into the reaction chamber, and applying RF power to form a plasma within the reaction chamber to convert at least a portion of the material to gaseous form, thereby removing at least a portion of the material from the partially fabricated integrated circuit.
  • methods may be used to remove photoresist and/or residues from the etch process. Methods may be effectively implemented on Damascene devices, including single and dual Damascene devices.
  • the weak oxidizing agent comprises at least one of carbon dioxide, carbon monoxide, nitrous oxide, nitric oxide and nitrogen dioxide and water.
  • the weak oxidizing agent comprises carbon dioxide.
  • the gas comprises between about 0.1 % to about 10.0 % carbon dioxide by volume.
  • the gas further comprises at least one inert carrier gas such as helium, argon or nitrogen.
  • the gas does not comprise molecular oxygen.
  • the fluorine-containing compound comprises at least one of nitrogen trifluoride (NF 3 ), sulfur hexafluoride (SF 6 ), hexafluoroethane (C 2 F 6 ), tetrafluoromethane (CF 4 ), trifluoromethane (CHF 3 ), difluoromethane (CH 2 F 2 ), octofluoropropane (C 3 F 8 ), octofluorocyclobutane (C 4 F 8 ), octofluoro[l-]butane (C 4 F 8 ), octofluoro[2-]butane (C 4 F 8 ), octofluoroisobutylene (C 4 F 8 ), fluorine (F 2 ), and the like.
  • the weak oxidizing agent comprises nitrogen trifluoride.
  • the gas comprises between about 5ppm to about 10% nitrogen trifluoride by volume.
  • Methods of the invention may be implemented on any size wafer. Most modern wafer fabrication facilities use either 200 mm or 300 mm wafers. Process conditions may vary depending upon the wafer size. If a 300 mm wafer is used, the total flow rate of gas may range between about 1,000 seem and about 40,000 seem. If carbon dioxide is used as the weak oxidizing agent, the flow rate of carbon dioxide may range between about 10 seem and about 2000 seem, e.g., 800 seem. If nitrogen trifluoride is used as the fluorine-containing gas, the flow rate of nitrogen trifluoride may range between about 1 and 20 seem, e.g., 5 seem. Typically, the RF plasma power for a 300 mm wafer ranges between about 300 Watts to about 3 Kilowatts for a plasma. Methods may be implemented using a direct or remote plasma.
  • substrate temperatures can range between about 50°C degrees and about 160°C. In certain embodiments, work piece temperatures are maintained at about 90°C or less.
  • Example chamber pressures can range between about 300 mTorr and about 2 Torr. In some embodiments, the wafer is held at a bias.
  • methods of the invention may be used with low-k dielectric materials, including carbon-doped low-k dielectric materials such as carbon- doped oxides (CDOs).
  • CDOs carbon- doped oxides
  • Methods of the invention can be implemented on both non- porous and porous dielectric materials, including CDOs and other compositions.
  • Methods of the invention may be implemented in any suitable reaction chamber.
  • the reaction chamber may be one chamber of a multi-chambered apparatus or it may be part of a single chamber apparatus.
  • a multi-stage removal process is used, with the fluoride-containing compound used only a subset of the stages.
  • the fluoride-containing compound is used only in a first set of stages, e.g., a first stage.
  • the fluoride-containing compound may be used as part of process gas used to generate a plasma in the first station, for example.
  • FIG. 1 is a process flow diagram illustrating aspects of some embodiments of the invention employed for stripping photoresist and removing etch-related residue from a partially fabricated integrated circuit.
  • FIGs. 2A-2C show cross sectional depictions of a low-k Damascene device during dry etch and photoresist strip processes in accordance with the invention.
  • FIGS. 3A and 3B show cross sectional depictions of a low-k device during dry after photoresist strip and HF-test processes in accordance with the invention.
  • FIG. 4A is a schematic illustration showing an apparatus suitable for practicing the present invention.
  • FIG. 4B is a simple block diagram showing a multi-station stripping tool suitable for practicing the present invention.
  • semiconductor wafer semiconductor wafer
  • wafer wafer
  • partially fabricated integrated circuit can refer to a silicon wafer during any of many stages of integrated circuit fabrication thereon.
  • the following detailed description assumes the invention is implemented on a wafer. However, the invention is not so limited.
  • the work piece may be of various shapes, sizes, and materials.
  • other work pieces that may take advantage of this invention include various articles such as printed circuit boards and the like.
  • methods of the invention may be used to efficiently and effectively to remove photoresist and etch-related materials from a low-k dielectric materials.
  • Methods of the invention are not limited to low-k dielectrics. Methods are also not limited to any particular category of low-k dielectrics. For instance, described methods may be effectively used on dielectrics with k values less than 4.0, dielectrics with k values less than about 2.8 and dielectrics with k values less than about 2.0 (“ultra-low-k” or ULK dielectrics).
  • the low-k dielectric may be porous or non-porous (sometimes referred to as a "dense" low-k dielectric).
  • low-k dense dielectrics are those having k values no greater than 2.8 and low-k porous dielectrics are those having k values no greater than 2.2.
  • Low-k dielectrics of any suitable composition may be used, including silicon oxide based dielectrics doped with fluorine and/or carbon. Non-silicon oxide based dielectrics, such as polymeric materials, may also be used. Any suitable process may be used to deposit the low-k dielectric, including as spin-on deposit and CVD deposit techniques. In the case of forming porous dielectrics, any suitable method may be used. A typical method involves co-depositing a silicon-based backbone and an organic porogen and subsequently removing the porogen component, leaving a porous dielectric film. Other methods include sol-gel techniques. Specific examples of suitable low-k films are carbon based spin-on type films such as SILK TM and CVD deposited porous films such as Coral TM .
  • Methods of the invention use plasmas that are produced from gases that contain hydrogen and a weak oxidizing agent, and in certain processing operations, a fluorine-containing compound.
  • the actual species present in the plasma may be a mixture of different ions and molecules derived from the hydrogen, weak oxidizing agent and/or fluorine-containing compound. It is noted that other species may be present in the reaction chamber, such as small hydrocarbons, carbon dioxide, water vapor and other volatile components as the plasma reacts with and breaks down the organic photoresist and other residues.
  • reference to the initial gas/gases introduced into the plasma is/are different from other gas/gases that may exist after the plasma is formed.
  • Figure 1 is a flow chart depicting one general high-level process flow in accordance with some embodiments of the present invention. Note that some typical operations related to the methods of the invention involved in integrated circuit (IC) fabrication are also included in Figure 1 to provide a context for how the invention may be used. To provide a visual context of some embodiments of the invention, Figures 2A through 2C show cross-sectional depictions of a portion of a low-k Damascene device during various pertinent fabrication processes. [0026] Referring to Figure 1 , a wafer with exposed regions of a low-k dielectric layer are etched leaving a patterned photoresist layer thereon is provided (block 101).
  • Figures 2A and 2B depict the forming of a patterned low-k dielectric in the context of processing a Damascene device 200.
  • Figure 2 A shows device 200 before and
  • Figure 2B shows device 200 after a dry etch process.
  • Figure 2B corresponds to the state of the device provided in block 101 of Figure 1.
  • layer 201 has a low-k dielectric layer 203 deposited thereon, which has portions of photoresist 205 deposited thereon.
  • underlying layer 201 may be a metal layer such as copper, an etch stop layer such as silicon carbide or silicon nitride, or another type of layer.
  • Photoresist 205 was previously patterned using UV light lithography (or other suitable process) to leave exposed portions of low-k dielectric layer 203.
  • Device 200 is then subjected to a dry etch process, typically one of sputter etching, plasma etching or reactive ion etching.
  • the resulting device 200 has features 210 etched within an ultra low-k dielectric layer 203.
  • Photoresist portions 205 must be stripped before further wafer processing. Note that the tops and sides of the exposed photoresist portions 205 have "skins" 207 that are relatively hard portions of the photoresist as a result of some dry etch processes and that can be compositionally different from the bulk photoresist portions 205.
  • the skin is typically composed of dielectric residues re-deposited from low-k dielectric 203 and re-deposited polymer residue from the photoresist 205.
  • a film 209 can also form over exposed sidewalls of low dielectric 203. This film typically is made of polymer residues and damaged portions of the low-k dielectric from ion bombardment during the dry etch process.
  • the photoresist is stripped of a first portion of the photoresist (block 103).
  • this first portion includes skin that was formed from the etch process and is generally tougher to remove.
  • the wafer is exposed to a hydrogen-based plasma with a weak oxidizing agent and a fluorine-containing compound.
  • the wafer is exposed to a H2/C02/NF3 plasma.
  • a relatively small amount of fluorine-containing compound is employed in this operation.
  • H2 flow rate is about 20,000 seem (20 slpm)
  • the individual flow rates may vary depending on the particular embodiment.
  • the H2 flow rate is two orders of magnitude larger than that of the C02 flow rate, and four orders of magnitude larger than the NF3 flow.
  • the C02 flow rate is at least one order of magnitude larger than the NF3 flow.
  • This operation is typically performed in a different reaction chamber from the chamber where the etch took place.
  • a reaction chamber may be referred to as a stand-alone "strip unit.” Any apparatus with a suitable plasma reaction chamber can be used.
  • the system may provide a direct (in situ plasma) or remote plasma.
  • the operation 103 may be used in certain embodiments to replace a conventional oxygen-based strip that is performed in the same reaction chamber in which the etch took place and typically involves exposure to an oxygen- based plasma.
  • This oxidizing partial strip operation can damage some low-k dielectric materials, and may not be performed in certain implementations.
  • the wafer is provided in operation 101 without having previously undergone such a strip process in the etch chamber.
  • the next operation is to expose the wafer to a hydrogen-based plasma with a weak oxidizing agent to strip the bulk photoresist and/or remove etch-related material (block 105).
  • fluorine is not present in this operation, unlike in the previous operation.
  • the bulk of the photoresist and residue is removed in this operation, which may itself include multiple sub-operations.
  • the total flow rate of gas, the relative amount of weak oxidizing agent and fluorine-containing compound and other conditions in the strip chamber can vary depending upon, among other factors, plasma type (downstream versus direct), RF power, chamber pressure, substrate (wafer) size and type of weak oxidizing agent used.
  • the plasma may comprise between about 0.1% to 10%> carbon dioxide by volume and between about 5ppm to 10%> nitrogen trifluoride (if present) by volume.
  • a carrier gas such as helium, argon or nitrogen may be used.
  • the carrier gas is typically an unreactive gas.
  • commercial hydrogen is available in mixtures with noble gases such as helium. These commercially available gas mixtures may be used for the methods of this invention.
  • one or more additional plasma strip or wet clean operations may be performed. It should also be noted that in multi-station apparatuses, operations 103 and 105 may each be performed over one or more than one station.
  • the wafer is typically temperature controlled during exposure to the plasma.
  • the temperature such that it is no more than about 200 °C, no more than about 160°C, no more than about 150°C, no more than about 140°C, no more than about 130°C, no more than about 120°C, no more than about 110°C, no more than about 100°C, no more than about 90°C, no more than about 80°C, or no more than about 60°C.
  • the substrate is maintained at temperature no more than about 90°C. It has been found that these relatively low temperatures are critical in certain embodiments to preventing significant damage to the ULK film.
  • Figure 3A depicts a patterned ultra low-k dielectric layer 303, hard mask layer 315, and silicon carbide layer 301, after photoresist removal as described above.
  • Etched into low-k dielectric layer 303 is recessed feature 310, which may be a via or trench.
  • the feature 310 includes sidewalls 317 and bottom 319. It has been found that if the photoresist removal occurs at too high of a temperature, the low-k material near the sidewalls 317 is damaged.
  • One manner in which this damage is tested is by an HF dip, for example a 100: 1 dilution of HF for 45 seconds.
  • a photoresist removal process as described above in was performed at 90°C and compared to a process using the same chemistry, but performed at 280°C.
  • Figure 3B depicts the results with 317" showing the profile of the feature stripped at 280°C, and 317' showing the profile of the feature stripped at 90°C. While the profile 317' was found to be substantially unchanged from the as-stripped feature profile, profile 317" is bowed inward. The region between these two profiles is the area that is damaged under the high temperature stripping process. The higher temperature process may also remove a certain amount of etch stop material from the bottom of the feature.
  • Stations 1-5 0.9 Torr / 90°C / 3.5 kW RF plasma / 103 seconds per station
  • the temperature is raised for one or more operations after exposure to the fluorine-containing plasma.
  • a temperature of less than 160°C or less than 90°C may be used during exposure to the fluorine-based plasma, and raised prior to or during exposure to the one or more operations that use fluorine-free plasmas.
  • Temperature may be raised in stages in certain embodiments, with later stations using higher temperatures than earlier ones. The higher temperature may be within the range described, or may be higher than that described. For example, in certain embodiments, later stations can use higher temperatures such as 285 °C. However, in many embodiments, temperature is maintained at a low temperature throughout the strip process.
  • the above description provides examples of removing photoresist using low temperature hydrogen-based plasmas, in particular processes that involve exposing photoresist and etch-related residues to a plasma generated from hydrogen gas, wherein the wafer temperature is maintained at a low temperature, e.g., less than about 200 °C, less than about 160°C, less than about 150°C, less than about 140°C, less than about 130°C, less than about 120°C, less than about 110°C, less than about 100°C, less than about 90°C, less than about 80°C, or less than about 60°C.
  • the gas used to generate the plasma consists essentially of hydrogen gas in one or more operations.
  • one or more of a weak oxidizing agent, a fluorine-containing gas and a carrier gas may be added to the hydrogen gas in one or more operations, as described above.
  • process gas chemistries that may be employed to generate a plasma for the low-temperature exposure operations include H2; H2/C02; H2/C02/NF3 and H2/NF3, with other weak oxidizing agents and fluorine-containing agents described above substituted for or added to C02 and NF3, respectively.
  • these may be used at any or all of the removal operations depicted in Figures 2A-2C.
  • the gas used to generate the hydrogen- based plasma may have essentially no C02 or other weak oxidizing agent present.
  • the gas used to generate the hydrogen-based plasma to remove the bulk photoresist may have essentially no C02 or other weak oxidizing agent present.
  • NF3 or other fluorine- containing gas may be present in certain embodiments.
  • any suitable plasma reaction chamber apparatus may be used.
  • Suitable plasma chambers and systems include the Gamma 2100, 2130 I CP (Interlaced Inductively Coupled Plasma), G400, and GxT offered by Novellus Systems, Inc. of San Jose, CA.
  • Other systems include the Fusion line from Axcelis Technologies Inc. of Rockville, Maryland, TERA21 from PSK Tech Inc. in Korea, and the Aspen from Mattson Technology Inc. in Fremont, CA.
  • various strip chambers may be configured onto cluster tools. For example, a strip chamber may be added to a Centura cluster tool available from Applied Materials of Santa Clara, CA.
  • Figure 4A is a schematic illustration showing aspects of a downstream plasma apparatus 400 suitable for practicing the present invention on wafers.
  • Apparatus 400 has a plasma source 411 and an exposure chamber 401 separated by a showerhead assembly 417. Inside exposure chamber 401, a wafer 403 rests on a platen (or stage) 405. Platen 405 is fitted with a heating/cooling element. In some embodiments, platen 405 is also configured for applying a bias to wafer 403. Low pressure is attained in exposure chamber 401 via vacuum pump via conduit 407. Sources of gaseous hydrogen (with or without dilution/carrier gas), carbon dioxide (or other weak oxidizing agent), and if present nitrogen trifluoride (or other fluorine-containing gas) provide a flow of gas via inlet 409 into plasma source 411 of the apparatus.
  • gaseous hydrogen with or without dilution/carrier gas
  • carbon dioxide or other weak oxidizing agent
  • nitrogen trifluoride or other fluorine-containing gas
  • Plasma source 411 is surrounded in part by induction coils 413, which are in turn connected to a power source 415.
  • gas mixtures are introduced into plasma source 411, induction coils 413 are energized and a plasma is generated in plasma source 411.
  • showerhead assembly 417 which has an applied voltage, terminates the flow of some ions and allows the flow of neutral species into exposure chamber 401.
  • wafer 403 may be temperature controlled and/or a RF bias may be applied.
  • Various configurations and geometries of the plasma source 411 and induction coils 413 may be used. For example, induction coils 413 may loop around the plasma source 411 in an interlaced pattern.
  • the plasma source 411 may be shaped as a dome instead of a cylinder.
  • a controller 450 may be connected to components of the process chamber, and control process gas composition, pressure, temperature and wafer indexing of the stripping operations.
  • Machine-readable media may be coupled to the controller and contain instructions for controlling process conditions for these operations.
  • the apparatus of the invention is a strip unit dedicated to stripping photoresist from wafers.
  • a strip unit tool will have multiple wafer process stations so that multiple wafers may be processes simultaneously.
  • Figure 4B is a simple block diagram showing a top-down view of a multi-station wafer strip unit tool 430 that may be used in accordance with the invention.
  • Strip unit tool 430 has five strip stations 433, 435, 437, 439 and 441 and one load station 431.
  • Strip unit tool 430 is configured such that each station is capable of processing one wafer and so all stations may be exposed to a common vacuum.
  • Each of strip stations 433, 435, 437, 439 and 441 has its own RF power supply.
  • Load station 431 is typically configured with a load-lock station attached thereto to allow the input of wafers into strip unit tool 430 without a break in vacuum. Load station 431 may also be configured with a heat lamp to pre-heat wafers before transferring to strip stations and photoresist stripping.
  • Strip station 441 is typically configured with a load-lock station attached thereto to allow the output of wafers from strip unit tool 430 without a break in vacuum.
  • a robotic arm 443 transfers wafers from station to station.
  • wafers are processed in batch mode.
  • Batch mode processing can increase wafer though-put and is therefore commonly used in manufacturing operation.
  • each wafer is transferred to, and processed in, each of stations 431, 433, 435, 437, 439 and 441.
  • a typical batch mode process will proceed as follows: A wafer is first loaded into load station 431 where it is preheated with a heat lamp. Next, robotic arm 443 transfers the wafer to strip station 433 where it is plasma processed using a fluorine -based plasma for a time period sufficient to strip off about 1/5 of the photoresist.
  • Robotic arm 443 then transfers the wafer to strip station 435 where it is plasma processed using a non- fluorine process for a time period sufficient to strip off about another 1/5 of the remaining photoresist. This sequence is continued such that the wafer is processed at strip stations 437, 439 and 441. At strip station 441, the photoresist should be largely removed and the wafer is then unloaded from the strip unit tool.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Drying Of Semiconductors (AREA)
  • Cleaning Or Drying Semiconductors (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
PCT/US2010/059517 2009-12-11 2010-12-08 Low damage photoresist strip method for low-k dielectrics WO2011072042A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1020127015129A KR101908737B1 (ko) 2009-12-11 2010-12-08 작은-ｋ 절연체를 위한 저손상 포토레지스트 스트립 방법
JP2012543254A JP5911068B2 (ja) 2009-12-11 2010-12-08 ワークピース上の誘電体層から材料を除去する方法および装置、並びに、ワークピース上の誘電体層から材料を除去する段階を備える集積回路を製造する方法
CN201080056102.5A CN102792423B (zh) 2009-12-11 2010-12-08 用于低k电介质的低损害光致抗蚀剂剥离方法
SG2012040929A SG181165A1 (en) 2009-12-11 2010-12-08 Low damage photoresist strip method for low-k dielectrics

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/636,601 US8591661B2 (en) 2009-12-11 2009-12-11 Low damage photoresist strip method for low-K dielectrics
US12/636,601 2009-12-11

Publications (2)

Publication Number Publication Date
WO2011072042A2 true WO2011072042A2 (en) 2011-06-16
WO2011072042A3 WO2011072042A3 (en) 2011-09-09

Family

ID=44141528

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2010/059517 WO2011072042A2 (en) 2009-12-11 2010-12-08 Low damage photoresist strip method for low-k dielectrics

Country Status (7)

Country Link
US (2) US8591661B2 (ko)
JP (1) JP5911068B2 (ko)
KR (1) KR101908737B1 (ko)
CN (1) CN102792423B (ko)
SG (1) SG181165A1 (ko)
TW (1) TWI562225B (ko)
WO (1) WO2011072042A2 (ko)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9613825B2 (en) 2011-08-26 2017-04-04 Novellus Systems, Inc. Photoresist strip processes for improved device integrity
US9941108B2 (en) 2004-12-13 2018-04-10 Novellus Systems, Inc. High dose implantation strip (HDIS) in H2 base chemistry

Families Citing this family (59)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8129281B1 (en) 2005-05-12 2012-03-06 Novellus Systems, Inc. Plasma based photoresist removal system for cleaning post ash residue
US7740768B1 (en) 2006-10-12 2010-06-22 Novellus Systems, Inc. Simultaneous front side ash and backside clean
US8435895B2 (en) 2007-04-04 2013-05-07 Novellus Systems, Inc. Methods for stripping photoresist and/or cleaning metal regions
US8229255B2 (en) 2008-09-04 2012-07-24 Zena Technologies, Inc. Optical waveguides in image sensors
US8866065B2 (en) 2010-12-13 2014-10-21 Zena Technologies, Inc. Nanowire arrays comprising fluorescent nanowires
US9515218B2 (en) 2008-09-04 2016-12-06 Zena Technologies, Inc. Vertical pillar structured photovoltaic devices with mirrors and optical claddings
US8274039B2 (en) 2008-11-13 2012-09-25 Zena Technologies, Inc. Vertical waveguides with various functionality on integrated circuits
US8748799B2 (en) 2010-12-14 2014-06-10 Zena Technologies, Inc. Full color single pixel including doublet or quadruplet si nanowires for image sensors
US8507840B2 (en) 2010-12-21 2013-08-13 Zena Technologies, Inc. Vertically structured passive pixel arrays and methods for fabricating the same
US8889455B2 (en) 2009-12-08 2014-11-18 Zena Technologies, Inc. Manufacturing nanowire photo-detector grown on a back-side illuminated image sensor
US9299866B2 (en) 2010-12-30 2016-03-29 Zena Technologies, Inc. Nanowire array based solar energy harvesting device
US8269985B2 (en) 2009-05-26 2012-09-18 Zena Technologies, Inc. Determination of optimal diameters for nanowires
US8735797B2 (en) 2009-12-08 2014-05-27 Zena Technologies, Inc. Nanowire photo-detector grown on a back-side illuminated image sensor
US9000353B2 (en) 2010-06-22 2015-04-07 President And Fellows Of Harvard College Light absorption and filtering properties of vertically oriented semiconductor nano wires
US8890271B2 (en) * 2010-06-30 2014-11-18 Zena Technologies, Inc. Silicon nitride light pipes for image sensors
US9082673B2 (en) 2009-10-05 2015-07-14 Zena Technologies, Inc. Passivated upstanding nanostructures and methods of making the same
US8519379B2 (en) 2009-12-08 2013-08-27 Zena Technologies, Inc. Nanowire structured photodiode with a surrounding epitaxially grown P or N layer
US8546742B2 (en) 2009-06-04 2013-10-01 Zena Technologies, Inc. Array of nanowires in a single cavity with anti-reflective coating on substrate
US8791470B2 (en) 2009-10-05 2014-07-29 Zena Technologies, Inc. Nano structured LEDs
US8299472B2 (en) 2009-12-08 2012-10-30 Young-June Yu Active pixel sensor with nanowire structured photodetectors
US9478685B2 (en) 2014-06-23 2016-10-25 Zena Technologies, Inc. Vertical pillar structured infrared detector and fabrication method for the same
US9406709B2 (en) 2010-06-22 2016-08-02 President And Fellows Of Harvard College Methods for fabricating and using nanowires
US9343490B2 (en) 2013-08-09 2016-05-17 Zena Technologies, Inc. Nanowire structured color filter arrays and fabrication method of the same
US8835831B2 (en) 2010-06-22 2014-09-16 Zena Technologies, Inc. Polarized light detecting device and fabrication methods of the same
US8591661B2 (en) 2009-12-11 2013-11-26 Novellus Systems, Inc. Low damage photoresist strip method for low-K dielectrics
US20110143548A1 (en) 2009-12-11 2011-06-16 David Cheung Ultra low silicon loss high dose implant strip
WO2011072061A2 (en) 2009-12-11 2011-06-16 Novellus Systems, Inc. Enhanced passivation process to protect silicon prior to high dose implant strip
US9997357B2 (en) 2010-04-15 2018-06-12 Lam Research Corporation Capped ALD films for doping fin-shaped channel regions of 3-D IC transistors
US9257274B2 (en) 2010-04-15 2016-02-09 Lam Research Corporation Gapfill of variable aspect ratio features with a composite PEALD and PECVD method
US9390909B2 (en) 2013-11-07 2016-07-12 Novellus Systems, Inc. Soft landing nanolaminates for advanced patterning
US9892917B2 (en) 2010-04-15 2018-02-13 Lam Research Corporation Plasma assisted atomic layer deposition of multi-layer films for patterning applications
US9611544B2 (en) 2010-04-15 2017-04-04 Novellus Systems, Inc. Plasma activated conformal dielectric film deposition
US8637411B2 (en) 2010-04-15 2014-01-28 Novellus Systems, Inc. Plasma activated conformal dielectric film deposition
US9287113B2 (en) 2012-11-08 2016-03-15 Novellus Systems, Inc. Methods for depositing films on sensitive substrates
US9373500B2 (en) 2014-02-21 2016-06-21 Lam Research Corporation Plasma assisted atomic layer deposition titanium oxide for conformal encapsulation and gapfill applications
US9685320B2 (en) 2010-09-23 2017-06-20 Lam Research Corporation Methods for depositing silicon oxide
KR101357785B1 (ko) * 2012-09-11 2014-02-04 피에스케이 주식회사 기판 처리 방법
TWI595112B (zh) 2012-10-23 2017-08-11 蘭姆研究公司 次飽和之原子層沉積及保形膜沉積
KR102230529B1 (ko) * 2013-12-27 2021-03-19 엘지디스플레이 주식회사 유기전계발광표시소자 및 이의 제조방법
US9214334B2 (en) 2014-02-18 2015-12-15 Lam Research Corporation High growth rate process for conformal aluminum nitride
US9514954B2 (en) 2014-06-10 2016-12-06 Lam Research Corporation Peroxide-vapor treatment for enhancing photoresist-strip performance and modifying organic films
US9478411B2 (en) 2014-08-20 2016-10-25 Lam Research Corporation Method to tune TiOx stoichiometry using atomic layer deposited Ti film to minimize contact resistance for TiOx/Ti based MIS contact scheme for CMOS
US9478438B2 (en) 2014-08-20 2016-10-25 Lam Research Corporation Method and apparatus to deposit pure titanium thin film at low temperature using titanium tetraiodide precursor
US9570320B2 (en) * 2014-10-09 2017-02-14 Lam Research Corporation Method to etch copper barrier film
US9564312B2 (en) 2014-11-24 2017-02-07 Lam Research Corporation Selective inhibition in atomic layer deposition of silicon-containing films
US10566187B2 (en) 2015-03-20 2020-02-18 Lam Research Corporation Ultrathin atomic layer deposition film accuracy thickness control
US9502238B2 (en) 2015-04-03 2016-11-22 Lam Research Corporation Deposition of conformal films by atomic layer deposition and atomic layer etch
US10526701B2 (en) 2015-07-09 2020-01-07 Lam Research Corporation Multi-cycle ALD process for film uniformity and thickness profile modulation
US9934984B2 (en) * 2015-09-09 2018-04-03 International Business Machines Corporation Hydrofluorocarbon gas-assisted plasma etch for interconnect fabrication
US9773643B1 (en) 2016-06-30 2017-09-26 Lam Research Corporation Apparatus and method for deposition and etch in gap fill
US10062563B2 (en) 2016-07-01 2018-08-28 Lam Research Corporation Selective atomic layer deposition with post-dose treatment
US10037884B2 (en) 2016-08-31 2018-07-31 Lam Research Corporation Selective atomic layer deposition for gapfill using sacrificial underlayer
US9730494B1 (en) * 2016-09-23 2017-08-15 Feinstein Patents, Llc Self-fitting, self-adjusting, automatically adjusting and/or automatically fitting shoe/sneaker/footwear
CN107015445A (zh) * 2017-03-27 2017-08-04 武汉新芯集成电路制造有限公司 半导体结构表面处理方法
US10269559B2 (en) 2017-09-13 2019-04-23 Lam Research Corporation Dielectric gapfill of high aspect ratio features utilizing a sacrificial etch cap layer
JP7022651B2 (ja) 2018-05-28 2022-02-18 東京エレクトロン株式会社 膜をエッチングする方法及びプラズマ処理装置
SG11202111962QA (en) 2019-05-01 2021-11-29 Lam Res Corp Modulated atomic layer deposition
CN112689803B (zh) 2019-07-18 2022-03-11 玛特森技术公司 使用氢自由基和臭氧气体的工件处理
WO2023069346A1 (en) * 2021-10-22 2023-04-27 Lam Research Corporation Strip with bevel cleaning

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040248414A1 (en) * 2003-02-04 2004-12-09 Taiwan Semiconductor Manufacturing Company, Ltd. Bi-level resist structure and fabrication method for contact holes on semiconductor substrates
US20060102197A1 (en) * 2004-11-16 2006-05-18 Kang-Lie Chiang Post-etch treatment to remove residues
US20060163202A1 (en) * 2005-01-21 2006-07-27 Tokyo Electron Limited Plasma etching method
US20090053901A1 (en) * 2004-12-13 2009-02-26 Novellus Systems Inc. High dose implantation strip (hdis) in h2 base chemistry

Family Cites Families (163)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4216922B2 (ja) * 1998-05-08 2009-01-28 東京エレクトロン株式会社 酸化膜のエッチング方法
US4201579A (en) 1978-06-05 1980-05-06 Motorola, Inc. Method for removing photoresist by hydrogen plasma
US4357203A (en) 1981-12-30 1982-11-02 Rca Corporation Plasma etching of polyimide
US4699689A (en) * 1985-05-17 1987-10-13 Emergent Technologies Corporation Method and apparatus for dry processing of substrates
US5292393A (en) 1986-12-19 1994-03-08 Applied Materials, Inc. Multichamber integrated process system
US5158644A (en) 1986-12-19 1992-10-27 Applied Materials, Inc. Reactor chamber self-cleaning process
JPH01200628A (ja) * 1988-02-05 1989-08-11 Toshiba Corp ドライエッチング方法
US5354386A (en) 1989-03-24 1994-10-11 National Semiconductor Corporation Method for plasma etching tapered and stepped vias
US5122225A (en) 1990-11-21 1992-06-16 Texas Instruments Incorporated Selective etch method
US5716494A (en) 1992-06-22 1998-02-10 Matsushita Electric Industrial Co., Ltd. Dry etching method, chemical vapor deposition method, and apparatus for processing semiconductor substrate
US5522932A (en) 1993-05-14 1996-06-04 Applied Materials, Inc. Corrosion-resistant apparatus
EP0664347A3 (en) 1994-01-25 1997-05-14 Applied Materials Inc Plant for the deposition of a uniform layer of a material on a substrate.
US5744049A (en) * 1994-07-18 1998-04-28 Applied Materials, Inc. Plasma reactor with enhanced plasma uniformity by gas addition, and method of using same
US5900351A (en) * 1995-01-17 1999-05-04 International Business Machines Corporation Method for stripping photoresist
US5817406A (en) 1995-07-14 1998-10-06 Applied Materials, Inc. Ceramic susceptor with embedded metal electrode and brazing material connection
US5633073A (en) 1995-07-14 1997-05-27 Applied Materials, Inc. Ceramic susceptor with embedded metal electrode and eutectic connection
JP3585591B2 (ja) 1995-07-29 2004-11-04 株式会社半導体エネルギー研究所 エッチング装置及びエッチング方法
US6187072B1 (en) 1995-09-25 2001-02-13 Applied Materials, Inc. Method and apparatus for reducing perfluorocompound gases from substrate processing equipment emissions
US6045618A (en) 1995-09-25 2000-04-04 Applied Materials, Inc. Microwave apparatus for in-situ vacuum line cleaning for substrate processing equipment
US6194628B1 (en) 1995-09-25 2001-02-27 Applied Materials, Inc. Method and apparatus for cleaning a vacuum line in a CVD system
US6193802B1 (en) 1995-09-25 2001-02-27 Applied Materials, Inc. Parallel plate apparatus for in-situ vacuum line cleaning for substrate processing equipment
US5792269A (en) 1995-10-31 1998-08-11 Applied Materials, Inc. Gas distribution for CVD systems
US5968324A (en) 1995-12-05 1999-10-19 Applied Materials, Inc. Method and apparatus for depositing antireflective coating
US5707485A (en) 1995-12-20 1998-01-13 Micron Technology, Inc. Method and apparatus for facilitating removal of material from the backside of wafers via a plasma etch
JPH09205130A (ja) 1996-01-17 1997-08-05 Applied Materials Inc ウェハ支持装置
US5660682A (en) 1996-03-14 1997-08-26 Lsi Logic Corporation Plasma clean with hydrogen gas
US5814155A (en) 1996-06-26 1998-09-29 Vlsi Technology, Inc. Plasma ashing enhancement
US6156149A (en) 1997-05-07 2000-12-05 Applied Materials, Inc. In situ deposition of a dielectric oxide layer and anti-reflective coating
US6127262A (en) 1996-06-28 2000-10-03 Applied Materials, Inc. Method and apparatus for depositing an etch stop layer
US6083852A (en) 1997-05-07 2000-07-04 Applied Materials, Inc. Method for applying films using reduced deposition rates
US6129091A (en) 1996-10-04 2000-10-10 Taiwan Semiconductor Manfacturing Company Method for cleaning silicon wafers with deep trenches
US6562544B1 (en) 1996-11-04 2003-05-13 Applied Materials, Inc. Method and apparatus for improving accuracy in photolithographic processing of substrates
US5844195A (en) 1996-11-18 1998-12-01 Applied Materials, Inc. Remote plasma source
US5911834A (en) 1996-11-18 1999-06-15 Applied Materials, Inc. Gas delivery system
US5830775A (en) * 1996-11-26 1998-11-03 Sharp Microelectronics Technology, Inc. Raised silicided source/drain electrode formation with reduced substrate silicon consumption
US5811358A (en) 1997-01-03 1998-09-22 Mosel Vitelic Inc. Low temperature dry process for stripping photoresist after high dose ion implantation
US6039834A (en) 1997-03-05 2000-03-21 Applied Materials, Inc. Apparatus and methods for upgraded substrate processing system with microwave plasma source
US6077764A (en) 1997-04-21 2000-06-20 Applied Materials, Inc. Process for depositing high deposition rate halogen-doped silicon oxide layer
US6306564B1 (en) 1997-05-27 2001-10-23 Tokyo Electron Limited Removal of resist or residue from semiconductors using supercritical carbon dioxide
US6177023B1 (en) 1997-07-11 2001-01-23 Applied Komatsu Technology, Inc. Method and apparatus for electrostatically maintaining substrate flatness
JP3317209B2 (ja) * 1997-08-12 2002-08-26 東京エレクトロンエイ・ティー株式会社 プラズマ処理装置及びプラズマ処理方法
JPH1187307A (ja) * 1997-09-05 1999-03-30 Sony Corp レジストの除去方法及びその除去装置
US5908672A (en) 1997-10-15 1999-06-01 Applied Materials, Inc. Method and apparatus for depositing a planarized passivation layer
US6797188B1 (en) * 1997-11-12 2004-09-28 Meihua Shen Self-cleaning process for etching silicon-containing material
US6379576B2 (en) * 1997-11-17 2002-04-30 Mattson Technology, Inc. Systems and methods for variable mode plasma enhanced processing of semiconductor wafers
US6098568A (en) 1997-12-01 2000-08-08 Applied Materials, Inc. Mixed frequency CVD apparatus
US6660656B2 (en) 1998-02-11 2003-12-09 Applied Materials Inc. Plasma processes for depositing low dielectric constant films
US6287990B1 (en) 1998-02-11 2001-09-11 Applied Materials, Inc. CVD plasma assisted low dielectric constant films
US6593247B1 (en) 1998-02-11 2003-07-15 Applied Materials, Inc. Method of depositing low k films using an oxidizing plasma
US6340435B1 (en) 1998-02-11 2002-01-22 Applied Materials, Inc. Integrated low K dielectrics and etch stops
US6413583B1 (en) 1998-02-11 2002-07-02 Applied Materials, Inc. Formation of a liquid-like silica layer by reaction of an organosilicon compound and a hydroxyl forming compound
US6054379A (en) 1998-02-11 2000-04-25 Applied Materials, Inc. Method of depositing a low k dielectric with organo silane
US6303523B2 (en) 1998-02-11 2001-10-16 Applied Materials, Inc. Plasma processes for depositing low dielectric constant films
US6203657B1 (en) * 1998-03-31 2001-03-20 Lam Research Corporation Inductively coupled plasma downstream strip module
US5980770A (en) 1998-04-16 1999-11-09 Siemens Aktiengesellschaft Removal of post-RIE polymer on Al/Cu metal line
US6086952A (en) 1998-06-15 2000-07-11 Applied Materials, Inc. Chemical vapor deposition of a copolymer of p-xylylene and a multivinyl silicon/oxygen comonomer
US6800571B2 (en) 1998-09-29 2004-10-05 Applied Materials Inc. CVD plasma assisted low dielectric constant films
US6277733B1 (en) 1998-10-05 2001-08-21 Texas Instruments Incorporated Oxygen-free, dry plasma process for polymer removal
US6342446B1 (en) 1998-10-06 2002-01-29 Texas Instruments Incorporated Plasma process for organic residue removal from copper
US6171945B1 (en) 1998-10-22 2001-01-09 Applied Materials, Inc. CVD nanoporous silica low dielectric constant films
US6245690B1 (en) 1998-11-04 2001-06-12 Applied Materials, Inc. Method of improving moisture resistance of low dielectric constant films
US6107184A (en) 1998-12-09 2000-08-22 Applied Materials, Inc. Nano-porous copolymer films having low dielectric constants
US6417080B1 (en) 1999-01-28 2002-07-09 Canon Kabushiki Kaisha Method of processing residue of ion implanted photoresist, and method of producing semiconductor device
US6130166A (en) 1999-02-01 2000-10-10 Vlsi Technology, Inc. Alternative plasma chemistry for enhanced photoresist removal
US6204192B1 (en) 1999-03-29 2001-03-20 Lsi Logic Corporation Plasma cleaning process for openings formed in at least one low dielectric constant insulation layer over copper metallization in integrated circuit structures
US6709715B1 (en) 1999-06-17 2004-03-23 Applied Materials Inc. Plasma enhanced chemical vapor deposition of copolymer of parylene N and comonomers with various double bonds
US6030901A (en) * 1999-06-24 2000-02-29 Advanced Micro Devices, Inc. Photoresist stripping without degrading low dielectric constant materials
US6492186B1 (en) * 1999-08-05 2002-12-10 Eaton Corporation Method for detecting an endpoint for an oxygen free plasma process
US6281135B1 (en) 1999-08-05 2001-08-28 Axcelis Technologies, Inc. Oxygen free plasma stripping process
US6313042B1 (en) 1999-09-03 2001-11-06 Applied Materials, Inc. Cleaning contact with successive fluorine and hydrogen plasmas
US6767698B2 (en) 1999-09-29 2004-07-27 Tokyo Electron Limited High speed stripping for damaged photoresist
JP4221847B2 (ja) 1999-10-25 2009-02-12 パナソニック電工株式会社 プラズマ処理装置及びプラズマ点灯方法
JP3366301B2 (ja) 1999-11-10 2003-01-14 日本電気株式会社 プラズマｃｖｄ装置
US6352938B2 (en) 1999-12-09 2002-03-05 United Microelectronics Corp. Method of removing photoresist and reducing native oxide in dual damascene copper process
US6365516B1 (en) * 2000-01-14 2002-04-02 Advanced Micro Devices, Inc. Advanced cobalt silicidation with in-situ hydrogen plasma clean
US6184134B1 (en) 2000-02-18 2001-02-06 Infineon Technologies North America Corp. Dry process for cleaning residues/polymers after metal etch
JP4470274B2 (ja) 2000-04-26 2010-06-02 東京エレクトロン株式会社 熱処理装置
JP4371543B2 (ja) 2000-06-29 2009-11-25 日本電気株式会社 リモートプラズマｃｖｄ装置及び膜形成方法
US6426304B1 (en) 2000-06-30 2002-07-30 Lam Research Corporation Post etch photoresist strip with hydrogen for organosilicate glass low-κ etch applications
US20020185226A1 (en) * 2000-08-10 2002-12-12 Lea Leslie Michael Plasma processing apparatus
DE10051380C2 (de) 2000-10-17 2002-11-28 Advanced Micro Devices Inc Verfahren zur Herstellung eines Halbleiterbauteils unter Anwendung eines Schrumpfprozesses eines Strukturmerkmals
US6569257B1 (en) * 2000-11-09 2003-05-27 Applied Materials Inc. Method for cleaning a process chamber
US6692903B2 (en) * 2000-12-13 2004-02-17 Applied Materials, Inc Substrate cleaning apparatus and method
US6733594B2 (en) 2000-12-21 2004-05-11 Lam Research Corporation Method and apparatus for reducing He backside faults during wafer processing
US6479391B2 (en) * 2000-12-22 2002-11-12 Intel Corporation Method for making a dual damascene interconnect using a multilayer hard mask
US20020127853A1 (en) 2000-12-29 2002-09-12 Hubacek Jerome S. Electrode for plasma processes and method for manufacture and use thereof
US6319842B1 (en) 2001-01-02 2001-11-20 Novellus Systems Incorporated Method of cleansing vias in semiconductor wafer having metal conductive layer
US6589879B2 (en) 2001-01-18 2003-07-08 Applied Materials, Inc. Nitride open etch process based on trifluoromethane and sulfur hexafluoride
US6777344B2 (en) 2001-02-12 2004-08-17 Lam Research Corporation Post-etch photoresist strip with O2 and NH3 for organosilicate glass low-K dielectric etch applications
JP4133333B2 (ja) 2001-02-15 2008-08-13 東京エレクトロン株式会社 被処理体の処理方法及びその処理装置
US6764940B1 (en) 2001-03-13 2004-07-20 Novellus Systems, Inc. Method for depositing a diffusion barrier for copper interconnect applications
US7186648B1 (en) 2001-03-13 2007-03-06 Novellus Systems, Inc. Barrier first method for single damascene trench applications
US6723654B2 (en) 2001-03-30 2004-04-20 Taiwan Semiconductor Manufacturing Co., Ltd Method and apparatus for in-situ descum/hot bake/dry etch photoresist/polyimide layer
US6951823B2 (en) 2001-05-14 2005-10-04 Axcelis Technologies, Inc. Plasma ashing process
US6834656B2 (en) 2001-05-23 2004-12-28 Axcelis Technology, Inc. Plasma process for removing polymer and residues from substrates
US6875702B2 (en) 2001-06-11 2005-04-05 Lsi Logic Corporation Plasma treatment system
US6632735B2 (en) 2001-08-07 2003-10-14 Applied Materials, Inc. Method of depositing low dielectric constant carbon doped silicon oxide
US6872652B2 (en) 2001-08-28 2005-03-29 Infineon Technologies Ag Method of cleaning an inter-level dielectric interconnect
US20030045098A1 (en) * 2001-08-31 2003-03-06 Applied Materials, Inc. Method and apparatus for processing a wafer
JP5038567B2 (ja) * 2001-09-26 2012-10-03 東京エレクトロン株式会社 エッチング方法
JP4838464B2 (ja) * 2001-09-26 2011-12-14 東京エレクトロン株式会社 処理方法
US6680164B2 (en) 2001-11-30 2004-01-20 Applied Materials Inc. Solvent free photoresist strip and residue removal processing for post etching of low-k films
US6720132B2 (en) 2002-01-08 2004-04-13 Taiwan Semiconductor Manufacturing Co., Ltd. Bi-layer photoresist dry development and reactive ion etch method
US7390755B1 (en) 2002-03-26 2008-06-24 Novellus Systems, Inc. Methods for post etch cleans
US6848455B1 (en) 2002-04-22 2005-02-01 Novellus Systems, Inc. Method and apparatus for removing photoresist and post-etch residue from semiconductor substrates by in-situ generation of oxidizing species
US7074298B2 (en) 2002-05-17 2006-07-11 Applied Materials High density plasma CVD chamber
KR100649418B1 (ko) 2002-08-22 2006-11-27 다이킨 고교 가부시키가이샤 박리액
US6900135B2 (en) 2002-08-27 2005-05-31 Applied Materials, Inc. Buffer station for wafer backside cleaning and inspection
US6693043B1 (en) * 2002-09-20 2004-02-17 Novellus Systems, Inc. Method for removing photoresist from low-k films in a downstream plasma system
US6837967B1 (en) 2002-11-06 2005-01-04 Lsi Logic Corporation Method and apparatus for cleaning deposited films from the edge of a wafer
US6787452B2 (en) 2002-11-08 2004-09-07 Chartered Semiconductor Manufacturing Ltd. Use of amorphous carbon as a removable ARC material for dual damascene fabrication
US20040195208A1 (en) * 2003-02-15 2004-10-07 Pavel Elizabeth G. Method and apparatus for performing hydrogen optical emission endpoint detection for photoresist strip and residue removal
US7205240B2 (en) * 2003-06-04 2007-04-17 Applied Materials, Inc. HDP-CVD multistep gapfill process
US7256134B2 (en) * 2003-08-01 2007-08-14 Applied Materials, Inc. Selective etching of carbon-doped low-k dielectrics
US6924239B2 (en) 2003-10-14 2005-08-02 Texas Instruments Incorporated Method for removal of hydrocarbon contamination on gate oxide prior to non-thermal nitridation using “spike” radical oxidation
US20050106888A1 (en) 2003-11-14 2005-05-19 Taiwan Semiconductor Manufacturing Co. Method of in-situ damage removal - post O2 dry process
WO2005072211A2 (en) 2004-01-20 2005-08-11 Mattson Technology, Inc. System and method for removal of photoresist and residues following contact etch with a stop layer present
US20050158667A1 (en) 2004-01-20 2005-07-21 Applied Materials, Inc. Solvent free photoresist strip and residue removal processing for post etching of low-k films
JP2005268312A (ja) * 2004-03-16 2005-09-29 Semiconductor Leading Edge Technologies Inc レジスト除去方法及びそれを用いて製造した半導体装置
US7628864B2 (en) 2004-04-28 2009-12-08 Tokyo Electron Limited Substrate cleaning apparatus and method
KR100971799B1 (ko) * 2004-06-21 2010-07-22 도쿄엘렉트론가부시키가이샤 플라즈마 처리 장치, 플라즈마 처리 방법 및 컴퓨터 판독가능한 기억 매체
US7288484B1 (en) * 2004-07-13 2007-10-30 Novellus Systems, Inc. Photoresist strip method for low-k dielectrics
US7632756B2 (en) 2004-08-26 2009-12-15 Applied Materials, Inc. Semiconductor processing using energized hydrogen gas and in combination with wet cleaning
JP2006073612A (ja) * 2004-08-31 2006-03-16 Rohm Co Ltd レジスト除去方法
US7597816B2 (en) 2004-09-03 2009-10-06 Lam Research Corporation Wafer bevel polymer removal
US7202176B1 (en) 2004-12-13 2007-04-10 Novellus Systems, Inc. Enhanced stripping of low-k films using downstream gas mixing
KR100607777B1 (ko) * 2004-12-27 2006-08-01 동부일렉트로닉스 주식회사 반도체 소자의 제조 방법
DE102004063036A1 (de) * 2004-12-28 2006-07-06 Advanced Micro Devices, Inc., Sunnyvale Verfahren zum Ausbilden von Kontaktflecken
US7601272B2 (en) 2005-01-08 2009-10-13 Applied Materials, Inc. Method and apparatus for integrating metrology with etch processing
US7344993B2 (en) * 2005-01-11 2008-03-18 Tokyo Electron Limited, Inc. Low-pressure removal of photoresist and etch residue
US7268071B2 (en) 2005-01-12 2007-09-11 Sony Corporation Dual damascene interconnections having low K layer with reduced damage arising from photoresist stripping
JP2006203035A (ja) * 2005-01-21 2006-08-03 Tokyo Electron Ltd プラズマエッチング方法
US7198677B2 (en) 2005-03-09 2007-04-03 Wafermasters, Inc. Low temperature wafer backside cleaning
US8129281B1 (en) * 2005-05-12 2012-03-06 Novellus Systems, Inc. Plasma based photoresist removal system for cleaning post ash residue
JP2007019367A (ja) 2005-07-11 2007-01-25 Ricoh Co Ltd 半導体装置の製造方法
US7411298B2 (en) * 2005-08-17 2008-08-12 Kabushiki Kaisha Kobe Seiko Sho (Kobe Steel, Ltd.) Source/drain electrodes, thin-film transistor substrates, manufacture methods thereof, and display devices
US7468326B2 (en) 2005-08-24 2008-12-23 United Microelectronics Corp. Method of cleaning a wafer
US7465680B2 (en) 2005-09-07 2008-12-16 Applied Materials, Inc. Post deposition plasma treatment to increase tensile stress of HDP-CVD SIO2
US7909960B2 (en) 2005-09-27 2011-03-22 Lam Research Corporation Apparatus and methods to remove films on bevel edge and backside of wafer
JP2007109744A (ja) * 2005-10-11 2007-04-26 Tokuyama Corp 基板洗浄液
KR100742279B1 (ko) 2005-12-22 2007-07-24 삼성전자주식회사 반도체 소자의 제조 장치 및 방법
KR20070069802A (ko) 2005-12-28 2007-07-03 엘지.필립스 엘시디 주식회사 평판표시소자의 제조장치 및 그를 이용한 기판파손방지방법
US8061459B2 (en) 2006-01-17 2011-11-22 GM Global Technology Operations LLC Traction control method for a tracked vehicle
US7432209B2 (en) * 2006-03-22 2008-10-07 Applied Materials, Inc. Plasma dielectric etch process including in-situ backside polymer removal for low-dielectric constant material
US8034176B2 (en) * 2006-03-28 2011-10-11 Tokyo Electron Limited Gas distribution system for a post-etch treatment system
US7851369B2 (en) 2006-06-05 2010-12-14 Lam Research Corporation Hardmask trim method
US7740768B1 (en) 2006-10-12 2010-06-22 Novellus Systems, Inc. Simultaneous front side ash and backside clean
US7655571B2 (en) * 2006-10-26 2010-02-02 Applied Materials, Inc. Integrated method and apparatus for efficient removal of halogen residues from etched substrates
US7595005B2 (en) 2006-12-11 2009-09-29 Tokyo Electron Limited Method and apparatus for ashing a substrate using carbon dioxide
US8083963B2 (en) * 2007-02-08 2011-12-27 Applied Materials, Inc. Removal of process residues on the backside of a substrate
US8435895B2 (en) * 2007-04-04 2013-05-07 Novellus Systems, Inc. Methods for stripping photoresist and/or cleaning metal regions
KR101440282B1 (ko) * 2007-07-11 2014-09-17 주성엔지니어링(주) 플라즈마 세정 방법
US20090061623A1 (en) * 2007-09-05 2009-03-05 United Microelectronics Corp. Method of forming electrical connection structure
KR101659095B1 (ko) 2008-02-08 2016-09-22 램 리써치 코포레이션 측방향 벨로우 및 비접촉 입자 밀봉을 포함하는 조정가능한 갭이 용량적으로 커플링되는 ｒｆ 플라즈마 반응기
JP5102653B2 (ja) 2008-02-29 2012-12-19 東京エレクトロン株式会社 プラズマエッチング方法、プラズマエッチング装置及びコンピュータ記憶媒体
US20090277871A1 (en) * 2008-03-05 2009-11-12 Axcelis Technologies, Inc. Plasma mediated ashing processes that include formation of a protective layer before and/or during the plasma mediated ashing process
US8791001B2 (en) * 2008-09-08 2014-07-29 Taiwan Semiconductor Manufacturing Company, Ltd. N2 based plasma treatment and ash for HK metal gate protection
US8591661B2 (en) 2009-12-11 2013-11-26 Novellus Systems, Inc. Low damage photoresist strip method for low-K dielectrics
US20120024314A1 (en) 2010-07-27 2012-02-02 Axcelis Technologies, Inc. Plasma mediated ashing processes
WO2011008436A2 (en) * 2009-07-13 2011-01-20 Applied Materials, Inc. Method for removing implanted photo resist from hard disk drive substrates
WO2011072061A2 (en) 2009-12-11 2011-06-16 Novellus Systems, Inc. Enhanced passivation process to protect silicon prior to high dose implant strip
US20110143548A1 (en) 2009-12-11 2011-06-16 David Cheung Ultra low silicon loss high dose implant strip
US9613825B2 (en) * 2011-08-26 2017-04-04 Novellus Systems, Inc. Photoresist strip processes for improved device integrity

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040248414A1 (en) * 2003-02-04 2004-12-09 Taiwan Semiconductor Manufacturing Company, Ltd. Bi-level resist structure and fabrication method for contact holes on semiconductor substrates
US20060102197A1 (en) * 2004-11-16 2006-05-18 Kang-Lie Chiang Post-etch treatment to remove residues
US20090053901A1 (en) * 2004-12-13 2009-02-26 Novellus Systems Inc. High dose implantation strip (hdis) in h2 base chemistry
US20060163202A1 (en) * 2005-01-21 2006-07-27 Tokyo Electron Limited Plasma etching method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9941108B2 (en) 2004-12-13 2018-04-10 Novellus Systems, Inc. High dose implantation strip (HDIS) in H2 base chemistry
US9613825B2 (en) 2011-08-26 2017-04-04 Novellus Systems, Inc. Photoresist strip processes for improved device integrity

Also Published As

Publication number Publication date
KR20120098777A (ko) 2012-09-05
TWI562225B (en) 2016-12-11
WO2011072042A3 (en) 2011-09-09
US20110139176A1 (en) 2011-06-16
SG181165A1 (en) 2012-07-30
TW201137970A (en) 2011-11-01
JP2013513948A (ja) 2013-04-22
KR101908737B1 (ko) 2018-10-16
JP5911068B2 (ja) 2016-04-27
CN102792423A (zh) 2012-11-21
US8591661B2 (en) 2013-11-26
US20140120733A1 (en) 2014-05-01
CN102792423B (zh) 2016-06-22

Similar Documents

Publication Publication Date Title
US8591661B2 (en) Low damage photoresist strip method for low-K dielectrics
US8058178B1 (en) Photoresist strip method for low-k dielectrics
US9564344B2 (en) Ultra low silicon loss high dose implant strip
TWI385728B (zh) 受損介電材料之移除方法
US7202176B1 (en) Enhanced stripping of low-k films using downstream gas mixing
TWI624024B (zh) 用於預清洗導電互連結構之方法
US8664124B2 (en) Method for etching organic hardmasks
KR101019931B1 (ko) 낮은 유전상수 물질에 대한 인-시튜 후면 폴리머 제거를 포함하는 플라즈마 유전체 식각 프로세스
JP5770740B2 (ja) 高ドーズインプラントストリップの前に行われる、シリコンを保護するためのパッシベーションプロセスの改善方法およびそのための装置
KR102083680B1 (ko) 유기 하드마스크들을 에칭하는 방법
JP4825911B2 (ja) 介在チャンバでの脱フッ素化及びウェハ脱フッ素化ステップによるプラズマエッチング及びフォトレジストストリッププロセス
US20050029229A1 (en) Selective etch process of a sacrificial light absorbing material (SLAM) over a dielectric material
US8435419B2 (en) Methods of processing substrates having metal materials
US7288483B1 (en) Method and system for patterning a dielectric film

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 201080056102.5

Country of ref document: CN

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 10836630

Country of ref document: EP

Kind code of ref document: A1

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 10836630

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 2012543254

Country of ref document: JP

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 20127015129

Country of ref document: KR

Kind code of ref document: A

122 Ep: pct application non-entry in european phase

Ref document number: 10836630

Country of ref document: EP

Kind code of ref document: A2