Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
  • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
  • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
  • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
  • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
  • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
  • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
  • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
  • H01L21/0338—Process specially adapted to improve the resolution of the mask
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
  • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
  • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
  • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
  • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
  • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
  • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
  • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
  • H01L21/3088—Process specially adapted to improve the resolution of the mask
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
  • H01L21/3105—After-treatment
  • H01L21/311—Etching the insulating layers by chemical or physical means
  • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
  • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
  • H01L21/321—After treatment
  • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
  • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
  • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
  • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
  • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
  • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
  • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B99/00—Subject matter not provided for in other groups of this subclass

Definitions

• This invention relates generally to integrated circuit fabrication and. more particularly, to masking techniques.
• DRAM dynamic random access memories
• SRAM static random access memories
• FE ferroelectric
• DRAM typically comprises millions of identical circuit elements, known as memory cells.
• a capacitor-based memory cell such as in conventional DRAM, typically consists of two electrical devices: a storage capacitor and an access field effect transistor. Each memory cell is an addressable location that can store one bit (binary digit) of data. A bit can be written to a cell through the transistor and can be read by sensing charge in the capacitor.
• Some memory technologies employ elements that can act as both a storage device and a switch ⁇ e.g., dendritic memory employing silver-doped chalcogenide glass) and some nonvolatile memories do not require switches for each cell ⁇ e.g., magnetoresistive RAM).
• some elements can act as both charge storage and charge sensing devices. For example, this is the case with flash memory, thus, allowing this type of memory to have one of the smallest cell sizes (4F ) of all memory technologies.
• 4F cell sizes
• Pitch is defined as the distance between an identical point in two neighboring features when the pattern includes repeating features, as in arrays. These features are typically defined by spaces between adjacent features, which spaces are typically filled by a material, such as an insulator. As a result, pitch can be viewed as the sum of the width of a feature and of the width of the space on one side of the feature separating that feature from a neighboring feature.
• photolithography techniques each have a minimum pitch below which a particular photolithographic technique cannot reliably form features. Thus, the minimum pitch of a photolithographic technique is an obstacle to continued feature size reduction.
• Pitch doubling or "pitch multiplication” is one method for extending the capabilities of photolithographic techniques beyond their minimum pitch.
• a pitch multiplication method is illustrated in Figures 1A-1F and described in U.S. Patent No. 5,328,810, issued to Lowrey ⁇ t ah, the entire disclosure of which is incorporated herein by reference.
• a pattern of lines 10 is photolithographically formed in a photoresist layer, which overlies a layer 20 of an expendable material, which in turn overlies a substrate 30.
• the pattern is then transferred using an etch (for example, an anisotropic etch) to the layer 20, thereby fo ⁇ ning placeholders, or mandrels, 40.
• an etch for example, an anisotropic etch
• the photoresist lines 10 can be stripped and the mandrels 40 can be isotropically etched to increase the distance between neighboring mandrels 40, as shown in Figure 1 C.
• a layer 50 of spacer material is subsequently deposited over the mandrels 40, as shown in Figure ID.
• Spacers 60 i.e., the material extending or originally formed extending from sidewalls of another material, are then formed on the sides of the mandrels 40.
• the spacer formation is accomplished by preferentially etching the spacer material from the horizontal surfaces 70 and 80 in a directional spacer etch, as shown in Figure IE.
• the remaining mandrels 40 are then removed, leaving behind only the spacers 60, which together act as a mask for patterning, as shown in Figure IF.
• the same width now includes two features and two spaces, with the spaces defined by, e.g., the spacers 60.
• the smallest feature size possible with a photolithographic technique is effectively decreased.
• pitch multiplication is generally useful for forming regularly spaced linear features, such as conductive interconnect lines in a memory array.
• integrated circuits typically contain features having various shapes and sizes which can be difficult to form by conventional pitch multiplication processes.
• the continuing reduction in the sizes of integrated circuits has provided a continuing demand for reductions in the sizes of features.
• Figures 1A-1F are schematic, cross-sectional side views showing a sequence of masking patterns for fo ⁇ ning conductive lines, in accordance with a prior art pitch doubling method;
• Figure 2A and 2B are schematic, cross-sectional views showing intermediate masking structures, in accordance with some embodiments;
• Figures 3A-3K are schematic, cross-sectional views showing a process sequence for forming features in a target layer, in accordance with some embodiments
• FIGS 4A-4H are schematic, cross-sectional views showing a process sequence for fo ⁇ ning features in a target layer, in accordance with other embodiments:
• Figures 5A-5D are schematic, cross-sectional views showing a process sequence for forming features in a target layer, in accordance with yet other embodiments;
• Figures 6A-6E are schematic, cross-sectional views showing a process sequence for forming features in a target layer, in accordance with yet other embodiments:
• Figures 7A-7F are schematic, cross-sectional views showing a process sequence for fo ⁇ ning features in a target layer, in accordance with yet other embodiments:
• Figures 8A-8E are schematic, cross-sectional views showing a process sequence for forming features in a target layer, in accordance with yet other embodiments:
• Figures 9A-9D are schematic, cross-sectional views showing a process sequence for forming features in a target layer, using anti-spacers and spacers, in accordance with yet other embodiments;
• Figures 10A-12B are schematic, top plan views and cross-sectional views showing a process sequence for forming three dimensional features in a target layer, in accordance with some embodiments, wherein Figures 1OA, 1 IA, and 12A are schematic, top plan views; Figure 1 OB is a cross-sectional view of Figure 1 OA, taken along the line 1 OB- 10B; Figures H B and I I C are cross-sectional views of Figure 1 IA, taken along the lines 1 IB-I IB and 1 1 C-11C, respectively; and Figure 12B is a cross-sectional view of Figure 12A, taken along the line 12B-12B;
• Figure 12C is a schematic perspective view of a structure resulting from the process of Figures 10A-12B;
• Figures 13A-15B are schematic, top plan views and cross-sectional views showing a process sequence for forming three dimensional features in a target layer, in accordance with some embodiments, wherein Figures 13A and 14A are schematic, top plan views; Figure 13B is a cross-section of Figure 13 A, taken along the line 13B-13B; Figures 14B and 14C are cross-sectional views of Figure 14A, taken along the lines 14B-14B and 14C-14C, respectively; and Figures 15A and 15B are cross-sectional views of Figure 14A. taken along the lines 14B-14B and 14C-14C. respectively, after a pattern of features has been transferred into the target layer:
• Figure 15C is a schematic, perspective view of a structure resulting from the process of Figures 13A-15B;
• Figures 16A-16D are schematic, top plan views showing a process sequence for fo ⁇ ning landing pads, in accordance with some embodiments.
• the tenn '"integrated circuit (IC) device refers to a semiconductor device, including, but not limited to. a memory device and a microprocessor.
• the memory device may be a volatile memory such as a random access memory (RAM) or non-volatile memory such as a read-only memory (ROM).
• RAMs include dynamic random access memories (DRAMs) and static random access memories (SRAMs).
• ROMs include programmable read-only memories (PROMs), erasable programmable read-only memories (EPROMs), electrically-erasable programmable read-only memories (EEPROMs), and flash memories.
• semiconductor substrate is defined to mean any construction comprising semiconductor materials, including, but not limited to. bulk semiconductor materials such as a semiconductor wafer (either alone or in integrated assemblies comprising other materials thereon) and semiconductor material layers (either alone or in integrated assemblies comprising other materials).
• substrate refers to any supporting substrate, including, but not limited to, the semiconductor substrates described above.
• layer encompasses both the singular and the plural unless otherwise indicated. A layer may overlie a portion of, or the entirety of, a substrate.
• features refers to parts of a pattern, such as lines, spaces, via, pillars, trenches, troughs, or moats.
• '"mandrels refers to mask features formed at a vertical level.
• intervening mask features refers to mask features that are formed between two immediately neighboring mandrels.
• array refers to a regularly repeating pattern of IC elements on a semiconductor substrate.
• a memory array typically has a number of identical memory cells in a matrix form.
• Logic arrays may similarly include repeating patterns of conductive lines and/or transistors.
• target layer refers to a layer in which a pattern of features is formed.
• a target layer may be part of a semiconductor substrate.
• a target layer may include metal, semiconductor, and/or insulator.
• transferring a pattern from a first (e.g., masking) level to a second level involves forming features in the second level that generally correspond to features on the first level.
• the path of lines in the second level will generally follow the path of lines on the first level.
• the location of other features on the second level will correspond to the location of similar features on the first level.
• the precise shapes and sizes of corresponding features can vary from the first level to the second level, however due, for example, to trim and growth steps.
• the sizes of and relative spacings between the features fo ⁇ ning the transferred pattern can be enlarged or diminished relative to the pattern on the first level, while still resembling the same initial "pattern. " '
• processing through masks is described for some embodiments as etching to transfer a hard mask pattern into a target layer, the skilled artisan will appreciate that processing in other embodiments can comprise, e.g., oxidation, nitridation, selective deposition, doping, etc. through the masks.
• methods are provided for forming a masking pattern for an electronic device, such as an integrated circuit.
• mandrels defining a first pattern are formed in a first masking layer provided over a target layer.
• the mandrels may be formed of a resist, a hard mask material, or part of a substrate.
• a second masking layer is deposited in spaces between the mandrels. The second masking layer at least partly fills the spaces between the mandrels. In some embodiments, the second masking layer may bury the first pattern.
• one or more sacrificial structures are formed to define a second pattern having a smaller pitch than the first pattern.
• the one or more sacrificial structures may be formed by altering, e.g., chemically altering, portions of either or both of the mandrels and the second masking layer.
• the one or more sacrificial structures may be formed by growing or depositing a layer of a material that is different, or selectively etchable relative to, those of the first and second masking layers before depositing the second masking layer.
• the resulting intermediate masking structures according to some embodiments are shown in Figures 2A and 2B.
• an intermediate masking structure 200A includes mandrels 130. a second masking layer 140, and sacrificial structures 150 that are fo ⁇ ned on a target layer 1 10.
• the mandrels 130 are spaced apart.
• the sacrificial structures 150 are formed on top and side surfaces 130a, 130b of the mandrels 130.
• the second masking layer 140 fills the remainder of the spaces between the mandrels 130.
• another intermediate masking structure 200B includes mandrels 130, a second masking layer 140, sacrificial structures 150, and partial gap fillers 155 formed on a target layer 1 10.
• the mandrels 130 are spaced apart from one another on the target layer 1 10.
• the sacrificial structures 150 are conformally fo ⁇ ned on top and side surfaces 130a. 130b of the mandrels 130.
• the partial gap fillers 155 are formed of the same material as the material of the sacrificial structures.
• the partial gap fillers 155 are formed on top surfaces 1 12 of the target layer 1 10 between the mandrels 130 covered with the sacrificial structures 150. In some embodiments, the partial gap fillers 155 may be fo ⁇ ned simultaneously with the sacrificial structures 150.
• the second masking layer 140 fills the remaining spaces between the mandrels 130.
• the sacrificial structures 150 are removed to create gaps between the mandrels 130 and the second masking layer 140. Such sacrificial structures are referred to as "anti-spacers " in the context of this document.
• the resulting masking structure may include the mandrels 130 and intervening mask features fo ⁇ ned of the second masking layer 140 ( Figure 2A).
• the resulting masking structure may include the mandrels ] 30 and intervening mask features including the second masking layer 140 and the partial gap fillers ( Figure 2B).
• the mandrels 130 and the intervening mask features alternate with each other, and together define a second pattern.
• the mandrels in the second pattern have a first pitch between two adjacent mandrels.
• the intervening mask features in the second pattern have a pitch substantially the same as the first pitch.
• the mandrels and intervening mask features are both used as masking features for the second pattern.
• the second pattern has a second pitch defined by the mandrels and an immediately adjacent one of the intervening mask features.
• the second pitch is about a half of the first pitch.
• the pitch of the second pattern may be further reduced by performing an additional process employing anti-spacers as described herein, or by blanket depositing and etching spacer material to form spacers on sidewalls of the mandrels and intervening mask features.
• the methods described herein can be used for forming three dimensional structures in a target layer.
• the three dimensional structures include, but are not limited to. lines, trenches, vias, posts, pillars, troughs, moats, and two or more of the foregoing.
• the methods can form structures having different sizes and shapes, for example, variable width conductive lines and landing pads.
• Tables 1 and 2 The processes and materials of Tables 1 and 2 will be understood by those of skill in the art, particularly in view of the present disclosure.
• the term “single level etch " refers to a process in which a single layer is provided and etched to form features of a pattern.
• the term “multi level etch " refers to a process in which multiple layers are provided and etched to form features of a pattern.
• the term '"diffusion limited shrink” refers to a process in which a solubility change in a feature is caused by a coat, thereby allowing a decrease in a dimension of the feature.
• the term “diffusion limited growth'” refers to a process in which a material is chemically attached to a pre-existing feature, e.g.. through a reaction or adsorption, thereby increasing the dimension of the feature.
• the te ⁇ n “freeze” refers to a surface treatment that protects a pattern by maintaining the integrity of the boundaries of the features forming the pattern; for example, freezing a pattern formed by a photoresist to prevent it from dissolving into an overlying photoresist layer.
• a “freeze” process can be performed to change the chemical solubility of a material that is being “frozen. " After the freeze process, the frozen material no longer exhibits solubility to solvents which would otherwise dissolve the material before the freeze process. For example, a photoresist, after being subjected to a freeze process, would be insoluble to solvents, such as propylene glycol monomethy] ether acetate (PGMEA) or ethyl lactate.
• PGMEA propylene glycol monomethy] ether acetate
• the term "reflow" refers to a process inducing a feature size change, a line increase, and a space decrease, for example, a thermal process that is designed for such a feature size shift to occur.
• the term "deprotection process" refers to a process in which a feature protected from a chemical reaction or dissolution by a solvent is released and allowed to become reactive or soluble.
• the te ⁇ n "furnace” refers to a process that includes a thermal bake at a temperature ranging typically, but not limited to, from about 25O 0 C to about 1000 0 C.
• solvent development refers to a process in which an unconventional solvent-based developer (e.g., a solvent other than tetramethylammonium hydroxide (TMAH)) is used to define a pattern.
• TMAH tetramethylammonium hydroxide
• the term "descum” refers to a process for removing small portions or residues of a material.
• the term “slim process” refers to a process that induces a feature size change, namely, a size decrease and a space increase.
• the term “overcoating” refers to a process of depositing or spinning-on a layer over an existing layer.
• the te ⁇ n "anti-spacer formation” refers to a process of fonning anti-spacers, as described herein.
• the te ⁇ n “selectivity change " refers to an etch process having the ability to differentiate the etch rate of a target material from the etch rate of a non-target material.
• plating process refers to an electrochemical process of depositing a metal on an existing layer(s).
• shrink refers to a process for reducing a size of a feature.
• te ⁇ n plasma growth
• vapor treatment refers to a process in which a gas phase material is used to interact with a substrate.
• silane compound refers to a process of forming a silane compound.
• phase change refers to a process in which a substrate undergoes a phase change during the process.
• solubility change refers to a process that changes the solubility of a material in a specific solution.
• the mandrels 130, the second masking layer 140, the sacrificial structures 150, and/or partial gap fillers 155 may be formed of various materials. Examples of such materials include, but are not limited to, those listed in Table 2.
• the term “specific development chemistry” refers to a chemical or material, such as butyl acetate or other customized solvents for development.
• the te ⁇ n “underlayer” refers to a layer of material used for a pattern transfer into an underlying layer.
• the te ⁇ n “reactivity promoter” refers to a chemical agent that promotes the growth of an organic material on a feature.
• a reactivity promoter may or may not act as a catalyst to a reaction which it promotes
• a reactivity promoter may contribute to the attachment of one mate ⁇ al to the surface of anothei material
• the various mate ⁇ als of Table 2 may be formed by one or more of the processes of Table 1
• the mate ⁇ als can be combined together and possibly with other mate ⁇ als to fo ⁇ n masks for defining patterns
• This list is for illustrative purposes only, such that the application of the processes noted herein to some embodiments of the invention may be expressed The list is not intended to be exhaustive, and as such mate ⁇ als and techniques used m the anti-spacer formation are not limited to this list
• a method for forming a masking pattern for an electronic device such as an integrated ciicuit
• First mandrels defining a first pattern are fo ⁇ ned in a first masking layer deposited over a target layer
• the mandrels may be fo ⁇ ned of a iesist or a hard mask material
• a second masking layer is deposited on and over the first masking layer to at least partly bury the first pattern while maintaining the first pattern
• the first pattern may be maintained by subjecting the first pattern to a surface treatment using, for example, a so-called freeze technique, p ⁇ or to depositing the second masking layer
• Portions of the second masking layei proximate to the mandrels are chemically altered such that the portions are more chemically removable (have higher etchabihty) than unaltered parts of the second masking layer
• the chemically altered portions are immediately adjacent the mandrels and have a selected width, and can be referred to as "anti-spacers " in the context of this document
• the chemical alteration can be achieved by a bake that drives an acid- or base-initiated reaction using an acid or base diffused from the mandrels
• the anti-spacers may not expand into the mandrels in this embodiment
• both portions of the mandrels immediately adjacent to the second masking layer and portions of the second masking layer immediately adjacent to the mandrels may be chemically altered In such embodiments, the altered portions of both the mandrels and the second masking layer fo ⁇ n anti-spacers In yet other embodiments, portions of the mandrels immediately adjacent to the second masking layer may be chemically altered while substantially no portion of the second masking layer is chemically altered, thereby forming anti-spacers only in the altered portions of the mandrels.
• the chemically altered portions are removed, exposing the mandrels.
• an additional step(s) can be perfo ⁇ ned to remove any material over the chemically altered portions to expose top surfaces of the chemically altered portions before removing the chemically altered portions.
• the remainder of the second masking layer forms intervening mask features.
• the mandrels and the intervening mask features together define a second pattern. The second pattern is transferred into the target layer.
• Figures 3A-3K illustrate a method of forming a masking pattern using anti-spacers in accordance with some embodiments.
• a hard mask layer 120 is provided over a target layer 1 10.
• a first resist layer 230 is provided over the hard mask layer 120.
• the target layer 1 10 may be a layer in which various IC components, parts, and structures are to be formed through IC fabrication processes. Examples of the components, parts, and structures include transistors, capacitors, resistors, diodes, conductive lines, electrodes, spacers, trenches, etc.
• the identity of the target layer material depends on the type of device to be fo ⁇ ned in the target layer 1 10. Examples of target layer materials include, but are not limited to, insulators, semiconductors, and metals.
• the target layer 110 may be fo ⁇ ned over a substrate, for example, a semiconductor substrate in certain embodiments. In certain other embodiments, at least a portion of a semiconductor substrate forms the target layer 1 10.
• the hard mask layer 120 is a layer that provides a pattern to be transferred into the target layer 1 10. As described herein, the hard mask layer 120 is patterned to form an array of features that serve as a mask for the target layer 1 10, e.g., in an etch step. While illustrated with one hard mask layer, the processes described herein can employ two or more hard mask layers. In certain embodiments, the hard mask layer 120 may be omitted.
• the hard mask layer 120 may be formed of an inorganic material.
• the hard mask layer 120 is formed of a dielectric anti-reflective coating (DARC). for example, sihcon- ⁇ ch silicon oxynit ⁇ de (SiO x Nv)
• the DARC layer may contain silicon in an amount from about 30 ⁇ t% to about 80 wt% with reference to the total weight of the layer
• the DARC layei may contain silicon in an amount from 35 wt% to about 70 wt% with reference to the total weight of the layer
• the hard mask layer 120 may be formed of silicon, silicon oxide (SiO 2 ) or silicon mt ⁇ de (S1 3 N 4 )
• the hard mask layer 120 may be formed of an organic material
• the hard mask layer 120 may be formed of amorphous carbon
• va ⁇ ous other hard mask materials can be used for the hard mask layer 120
• the hard mask layer 120 may have a
• the first resist layer 230 may be formed of a first resist material
• the first resist material is selected based on the type of lithography used for patterning the first resist layer 230 Examples of such lithography include, but are not limited to. ultiaviolet (UV) lithography, extreme ultraviolet (EUV) lithography, X-ray lithography and imprint contact lithography
• the first resist matenal is a photoresist, such as a positive resist
• the material of the first resist layer 230 may be varied depending on lithography, availability of selective etch chemistries and IC design
• a bottom anti-reflective coating (BARC) layer may be provided between the first resist layer 230 and the hard mask layei 120 BARCs, which are typically organic, enhance resolution by preventing reflections of the ultraviolet (UV) radiation that activates the photoresist BARCs are widely available, and are usually selected based upon the selection of the resist matenal and the UV wavelength BARCs, which are typically polymer-based, are usually removed along with the overlying photoresist
• the optional BARC layer may have a thickness of between about 2O ⁇ A and about 6O ⁇ A. optionally between about 3O ⁇ A and about 5O ⁇ A
• the first resist layer 230 is exposed to a pattern of light directed through a photomask over the first resist layer 230
• the first resist layer 230 is fo ⁇ ned of a positive photoresist
• Exposed portions 232 of the first resist layer 230 become soluble in a developer while unexposed portions 234 of the first resist layer 230 remain insoluble in the developer.
• the first resist layer 230 may be formed of a negative photoresist.
• exposed portions 234 of the first resist layer 230 become insoluble in a developer while unexposed portions 232 of the first resist layer 230 remain soluble in the developer.
• the first resist layer 230 is subjected to development using any suitable developer.
• developers include, but are not limited to. sodium hydroxide and tetramethylammonium hydroxide (TMAH).
• TMAH tetramethylammonium hydroxide
• rinsing solutions e.g., propylene glycol monomethyl ether acetate (PGMEA) and/or propylene glycol monomethyl ether (PGME)
• PMEA propylene glycol monomethyl ether acetate
• PGME propylene glycol monomethyl ether
• PEB post-exposure bake
• the exposed portions 232 of the first resist layer 230 are removed by the development.
• the mandrels 234 provide a first pattern 231 while exposing surfaces 122 of the hard mask layer 120.
• the first pattern 231 has a first pitch Pl between two neighboring mandrels 234, as shown in Figure 3B.
• Each of the mandrels 234 has a top surface 236 and a side surface 238.
• the illustrated mandrels 234 have a substantially rectangular or square cross-section. The skilled artisan will, however, appreciate that the cross-sectional shape of the mandrels 234 can be different from that illustrated. For example, the cross-sectional slope can be rounded.
• a chemically active species for example, an acid solution
• the acid solution can be a spin-on coating that covers the mandrels 234 and the exposed portions 122 of the hard mask layer 120.
• the acid solution can include an acid such as a conventional photo resist PAG or other organic acid.
• a bake process is conducted to thermally diffuse the acid into at least portions of the features 234 that are proximate to the top and side surfaces 236. 238 thereof.
• the acid may coat the top and side surfaces 236. 238 of the features 234 without being diffused into the features 234.
• this step may be omitted.
• a base solution may be deposited over the structure in place of the acid solution.
• the mandrels 234 may be subjected to a surface treatment.
• the surfaces 236. 238 of the mandrels 234 are modified such that the integrity of the mandrels 234 is maintained while a second resist layer is formed and patterned thereon.
• the surface treatment may fo ⁇ n a barrier coat or protective layer 236 on the surfaces 236, 238 of the mandrels 234.
• Such a surface treatment can be referred to as ''freeze " in the context of this document.
• the surface treatment may or may not change the lateral dimensions of the mandrels 234, and may or may not change the spacings between adjacent mandrels 234.
• the mandrels 234 can be frozen by various freeze techniques.
• the mandrels 234 can be frozen by chemical freeze, using a commercially available fluid overcoat.
• An example of a chemical freeze technique is disclosed by JSR corporation of Tokyo, Japan in their present product line.
• the mandrels 234 can be frozen by a plasma freeze.
• a plasma freeze can be conducted, using a plasma directed to the mandrels 234.
• plasmas include a fluorine-containing plasma generated from, e.g., a fluorocarbon (e.g., CF 4 , C 4 F 6 , and/or C 4 Fg), a hydrofluorocarbon (e.g., CH 2 F 2 , and/or CHF 3 ), or NF 3 .
• a fluorocarbon e.g., CF 4 , C 4 F 6 , and/or C 4 Fg
• a hydrofluorocarbon e.g., CH 2 F 2 , and/or CHF 3
• NF 3 NF 3
• the mandrels 234 can be frozen by a the ⁇ nal freeze.
• the thermal freeze can be conducted at a temperature between about 110 0 C and about 18O 0 C.
• An example of a thennal freeze technique is disclosed by Tokyo Ohka Kogyo Co., Ltd. of Kawasaki-shi, Kanagawa Prefecture, Japan in their commercially available products.
• a second resist layer 240 is blanket deposited over the mandrels 234 and the exposed surfaces 122 of the hard mask layer 120.
• the second resist layer 240 can have a substantially planar top surface 244.
• the second resist layer 240 may be formed of a second resist material.
• the second resist material may be of the same composition as the first resist material or of a different composition from the first resist material.
• the first and second resist materials may be of the same or different type with regard to being positive or negative photoresist.
• the second resist material may include a chemically amplified photoresist.
• the chemically amplified photoresist may be an acid-catalyzed or base-catalyzed material.
• Examples of chemically amplified photoresists include, but are not limited to, 193nm and 248nm photo resists. Some 1-line materials are also chemically amplified.
• the second resist material may include a bottom anti-reflective coating (BARC) material modified to be suitable for a solubility change by acid or base diffusion.
• BARC bottom anti-reflective coating
• the second resist layer 240 may be formed to have a thickness sufficient to cover the top surface 236 of the mandrels 234. Portions 242 of the second resist layer 240 overlying the top surfaces 236 of the mandrels 234 can be referred to as "top coat " in the context of this document.
• the top coats 242 may have a thickness selected such that all the resulting masking features have substantially the same height after the frozen mandrels 234 and other features that will be formed from portions of the second resist layer 240 are subjected to development. The resulting masking features will form a pattern to be transferred into the underlying target layer 1 10.
• the structure of Figure 3F is subjected to a bake.
• the bake may be conducted at a temperature of about 1 10 0 C to about 220 0 C for about 0.5 min. to about 3 min.
• the bake may be conducted at a temperature of about 1 10 0 C to about 160 0 C.
• the bake drives an acid- catalyzed reaction that alters the solubility of the second resist layer 240 in a developer.
• the acid-catalyzed reaction changes portions 250 of the second resist layer 240 that are proximate to the mandrels 234, causing those changed portions to become soluble in the developer.
• the portions 250 of the second resist layer 240 may include the top coats 242 of the second resist layer 240 and portions 244 adjoining the side surfaces 238 of the mandrels 234.
• the portions 250 that become soluble can be referred to as l 'anti-spacers.
• the acid-catalyzed reaction is initiated at or near the top and side surfaces 236, 238 of the mandrels 234 during the bake step.
• an acid diffused into the mandrels 234 during the step of Figure 3D now diffuses into the top coats 242 and the adjoining portions 244 of the second resist layer 240 (as indicated by arrows in Figure 3G). and changes the solubility of the portions 242. 244, thereby forming anti-spacers 250 around and on top of the mandrels 234.
• the width Wl of the anti-spacers 250 can be controlled by changing, for example, the bake time and/or temperature, the porosity of layer 240. and the size of acid species.
• the bake drives a base-catalyzed reaction that may alter the solubility of the second resist layer 240 in a developer.
• a base solution is provided in the step of Figure 3D, rather than an acid solution.
• anti-spacers can be formed in the same manner as in the embodiment described herein in connection with Figure 3G.
• other portions (not shown) of the second resist layer 240 may be optionally exposed to a pattern of light before or after the bake step.
• This exposure step can be used to form patterns in the other areas by photolithography, rather than by forming anti-spacers.
• the structure shown in Figure 3F or 3G may be blocked from light, if the structures are formed of a positive photoresist.
• This optional exposure step can form structures larger in width than the structures shown in Figure 3H.
• the optional exposure step can be used to fonn structures in a peripheral region of an IC device or substrate while methods employing anti-spacers can be used to form structures in an array region of the IC device or substrate.
• the structure resulting from the step of Figure 3G is subjected to development which serves to selectively remove the anti-spacers 250.
• Any suitable developer may be used to remove the anti-spacers 250 ( Figure 3G).
• developers include, but are not limited to, sodium hydroxide and tetramethylammonium hydroxide (TMAH).
• TMAH tetramethylammonium hydroxide
• rinsing solutions e.g., propylene glycol monomethyl ether acetate (PGMEA) and/or propylene glycol monomethyl ether (PGME)
• this development step can be performed at room temperature for about 0.5 min. to about 3 min.
• This step exposes the pre-existing mandrels 234 while defining intervening mask features 248 fonned of the second resist material.
• the illustrated intervening mask features 248 have a T-shaped top portion, but the skilled artisan will appreciate that the shape of the intervening mask features 248 can vary, depending on the conditions (e.g., temperature, duration, etc.) of the development.
• the mandrels 234 may have a first height Hl and the intervening mask features 248 may have a second height H2 that is greater than the first height Hl .
• the developer may also anisotropically remove at least part of top portions of the mandrels 234 and the intervening mask features 248.
• the mandrels 234, which have been frozen, may be developed at a slower rate than the intervening mask features 248.
• the mandrels 234 and the intervening mask features 248 can have substantially the same height H3 as each other if the thicknesses of the top coats 242 of the second layer 240 have been selected such that the heights of the mandrels 234 and the intervening mask features 248 are substantially the same as each other after the development.
• both of the mandrels 234 and the intervening mask features 248 can have rounded top portions.
• an isotropic etch process may be conducted after the development to reduce the widths of the mandrels 234 and the intervening mask features 248.
• the second pattern 260 has a second pitch P2 between neighboring features.
• the second pitch P2 is about half of the first pitch Pl in the illustrated embodiment.
• an etch step is conducted to transfer the second pattern 260 into the underlying hard mask layer 120.
• the second pattern 260 may be transferred into the hard mask layer 120 using any suitable etch process.
• the etch process can be a dry or wet etch process.
• the etch process can be a plasma etch process, for example, a high density plasma etch process.
• the plasma etch process may be an anisotropic etch process.
• the target layer 1 10 is etched through the hard mask layer 120. As a result, trenches or troughs 205 are formed in the target layer 1 10. In some embodiments, through-holes can be formed through the target layer 1 10.
• an etch stop layer (not pictured) can be used between the hard mask layer 120 and the target layer 1 10.
• the etch stop can be made of, for example, DARC or silicon nitride, depending upon the composition of the target layer 110.
• the etch stop avoids damage to the target layer 1 10 during the etching of the hard mask layer 120, such as during pattern transfer to the hard mask layer 120 or during removal of the hard mask layer 120. This may be particularly desirable when the target layer 1 10 is a metal, such as a metallization layer.
• the hard mask layer 120 and the overlying features 234, 248 may be removed by etch processes, such as a wet etch. Subsequently, additional steps such as metallizations may be conducted to form integrated circuits.
• Figures 4A-4H illustrate a method of forming a masking pattern using anti-spacers in accordance with other embodiments.
• the mandrels are formed from a hard mask layer or other material other than a photoresist layer.
• the method includes providing the target layer 1 10. Details of the target layer 110 can be as described above in connection with Figure 3A.
• a hard mask layer is formed over the target layer 1 10.
• the hard mask layer may be formed of a silicon-containing organic material.
• the silicon-containing organic layer may contain silicon in an amount from about 10 wt% to about 35 wt% with reference to the total weight of the layer.
• An example of a silicon- containing organic materials includes, but is not limited to, SHB-A629 (available from Shin Etsu, Tokyo, Japan).
• the hard mask layer may have a thickness of between about 40 run and about 800 nm, optionally between about 1 ⁇ m and about 3 ⁇ m.
• the hard mask layer is then patterned to form mandrels 330, as shown in Figure 4A.
• the hard mask layer can be patterned using any suitable process, including, but not limited to, a photolithographic process in which photoresist is patterned and the pattern is transferred to the hard mask layer.
• the mandrels 330 are spaced apart from one another and have a first pitch Pl and expose surfaces 1 12 of the target layer 1 10.
• a chemically active species for example, an acid solution
• the acid solution can be spin-on deposited on the structure to cover the mandrels 330 and the exposed surfaces 1 12 of the target layer 1 10.
• the acid solution can include any organic acid, such as a PAG.
• a bake process is conducted to thermally diffuse the acid into at least portions of the mandrels 330 proximate to the top and side surfaces 332, 334 of the mandrels 330.
• the mandrels 330 are at least partially permeable to the acid while the target layer 1 10 is substantially impermeable to the acid.
• the mandrels 330 can have an acid coat 326 on the surfaces 332, 334 thereof while the exposed portions 1 12 of the target layer 1 10 do not have an acid coat formed thereon, as shown in Figure 4C.
• the chemically active species may be in the form of a gas or may be in the solid state.
• a resist layer 340 is formed over the mandrels 330 and the exposed portions 1 12 of the target layer 1 10 and may have a substantially planar top surface 344.
• the resist layer 340 may be formed of a resist material that is the same as the second resist material described above in connection with Figure 3F.
• the resist material may include a chemically amplified resist.
• the chemically amplified resist may be either acid-catalyzed or base-catalyzed.
• a base coat (rather than an acid coat) is provided over the mandrels 330 and the exposed portions 1 12 of the target layer 1 10 in the step of Figure 4C.
• Other details of forming the resist layer 340 can be as described above in connection with Figure 3F.
• the structure resulting from the step of Figure 4D is subjected to a bake.
• the bake forms anti-spacers 350 at the sides and on top of the mandrels 330.
• Other details of the bake step can be as described in connection with Figure 3G.
• other portions (not shown) of the resist layer 340 may be optionally exposed to a pattern of light before or after the bake step of Figure 4E. This exposure step can be used to form patterns in the other portions by photolithography, rather than by forming anti-spacers.
• the structure shown in Figure 4E may be blocked from light, if the structures are fo ⁇ ned of a positive photoresist.
• This optional exposure step can form structures larger in width than the structures shown in Figure 4F.
• the optional exposure step can be used form structures in a peripheral region of an IC device or substrate while methods employing anti-spacers can be used to form structures in an array region of the IC device or substrate.
• the structure resulting from the step of Figure 4E is subjected to development to remove the anti-spacers 350.
• This step exposes the pre-existing mandrels 330 fonned of the hard mask material while forming intervening mask features 345 fo ⁇ ned of the resist material.
• the illustrated intervening mask features 345 have a T-shaped top portion, but the skilled artisan will appreciate that the shape of the intervening mask features 345 can vary, depending on the conditions (e.g. temperature, duration, etc.) of the development.
• the mandrels 330 may have a first height Hl and the intervening mask features 345 have a second height H2 that is greater than the first height Hl.
• the developer can also remove at least part of the top portions of the intervening mask features 345.
• the mandrels 330 which are formed of a hard mask material, may not be eroded by the developer.
• the mandrels 330 and the intervening mask features 345 may have substantially the same height H3 as each other. As shown in Figure 4G, the mandrels 330 may retain their original shape while the intervening mask features 345 may have rounded top portions.
• the second pattern 360 has a second pitch P2 between a mandrel 330 and a neighboring intervening mask feature 345.
• the second pitch P2 is about half of the first pitch Pl in the illustrated embodiment.
• an etch step is conducted to transfer the second pattern 360 into the target layer 1 10.
• the second pattern 360 may be transferred into the target layer 1 10 using any suitable etch process.
• the etch process can be a dry or wet etch process.
• the etch process can be a plasma etch process, optionally a high density plasma etch process.
• the plasma etch process may be an anisotropic etch process. Other details of this step can be as described above in connection with Figure 3K.
• trenches or troughs 305 are fo ⁇ ned in the target layer 1 10. Because the mandrels 330 (formed of a hard mask material) may be etched at a faster rate than the intervening mask features 345 (formed of a photoresist) during the transfer step of Figure 4H, the height H4 of the remaining mandrels 330 may be greater than the height H5 of the remaining intervening mask features 345 after the completion of the transfer step.
• the mandrels 330 and the intervening mask features 345 may be removed by known etch processes, such as a wet etch step. Subsequently, additional steps such as metallization may be conducted to complete integrated circuits.
• Figures 5A-5D illustrate a method of forming a masking pattern using anti-spacers in accordance with yet other embodiments.
• the method includes providing the target layer 110. Details of the target layer 110 can be as described above in connection with Figure 3A.
• Hard mask layer 120 is formed on the target layer 110. Details of the hard mask layer 120 can be as described above in connection with Figure 3A. In certain embodiments, the hard mask layer 120 may be omitted.
• mandrels 430 are formed of a photoresist material on the hard mask layer 120. Details of forming the mandrels 430 can be as described above in connection with Figures 3A-3C.
• the mandrels 430 provide a first pattern 431 while exposing surfaces 122 of the hard mask layer 120.
• the first pattern 431 has a first pitch Pl between two neighboring mandrels 430, as shown in Figure 5A.
• Each of the mandrels 430 has a top surface 436 and a side surface 438.
• the illustrated mandrels 430 have a substantially rectangular or square cross-section. The skilled artisan will, however, appreciate that the cross-sectional shape of the mandrels 430 can be different from that illustrated.
• a chemically active species 432 for example, an acid or base solution
• the acid or base solution can be spin-on deposited on the structure to cover the mandrels 430 and the exposed portions 122 of the hard mask layer 120.
• the details of the acid or base solution can be as described above in connection with Figure 3D.
• FIG. 5B the structure of Figure 5A is subjected to a bake.
• the details of the bake can be as described above in connection with Figure 3G.
• the bake drives an acid- or base-catalyzed reaction that alters the solubility of portions 452, 454 of the mandrels 430.
• the acid- or base-catalyzed reaction changes top portions 452 and side portions 454 of the mandrels 430, causing those changed portions to become soluble in a developer.
• the top and side portions 452, 454 of the mandrels 430 form anti-spacers 450.
• the resulting mandrels 430' have a reduced size both vertically and horizontally.
• Such mandrels 430' can be referred to as reduced mandrels in the context of this document.
• the reduced mandrels 430' covered with the anti-spacers 450 may be subjected to a surface treatment.
• Surfaces of the anti-spacers 450 are modified such that the integrity of the mandrels is maintained while a second resist layer is formed thereon.
• the details of the surface treatment can be as described above in connection with Figure 3 E.
• a second masking layer 440 is blanket deposited over the anti-spacers 450 and the exposed surfaces 122 of the hard mask layer 120.
• the second masking layer may have a smaller height than the anti-spacers such that the second masking layer surrounds sidewalls of the anti-spacers while exposing top surfaces of the anti-spacers.
• the second masking layer 440 may be formed of an image reversal material, such as an Image Reversal Overcoat (IROC) material and other similar materials, e.g., as outlined in US Patent Application Publication No. 2009/0081595 from Shin-Etsu Chemical Co., Ltd (Tokyo, Japan).
• Bottom Anti-Reflection Coating (BARC) materials can also be used for the second masking layer 440. Other details of this step can be as described above in connection with Figure 3F.
• the second masking layer 440 may be formed to have a thickness sufficient to cover the top portions 452 of the anti-spacers 450. Portions of the second masking layer 440 overlying the top portions 452 of the anti-spacers 450 may be referred to as "top coats " in the context of this document. [0101] Referring to Figure 5D, the structure resulting from the step of Figure 5C is subjected to development. Any suitable developer may be used to remove the anti-spacers 450 ( Figure 5C). This step exposes the reduced mandrels 430' while defining intervening mask features 448 formed of the material of the second masking layer 440.
• the second pattern 460 has a second pitch P2 between a reduced mandrel 430' and a neighboring intervening mask feature 448.
• the second pitch P2 is about half of the first pitch Pl ( Figure 5A) in the illustrated embodiment.
• Other details of this step can be as described above in connection with Figure 3H.
• the step shown in Figure 5D can be followed by steps as described above in connection with Figures 31 to 3K to transfer the second pattern 460 into the target layer 1 10.
• mandrels defining a first pattern are formed in a first masking layer provided over a target layer.
• One or more sacrificial structures may be formed by conformally growing or depositing a layer to cover at least exposed sidewall surfaces of the mandrels.
• the layer may be fonned of a material that is different from that of the first masking layer.
• a second masking layer is deposited to fill spaces defined by the mandrels covered with the sacrificial structures.
• the second masking layer may cover top surfaces and sidewalls of the mandrels covered with the sacrificial structures.
• an additional step(s) e.g., a descum step, can be performed to remove portions of the second masking layer over the sacrificial structures to expose top surfaces of the sacrificial structures.
• the second masking layer may have a smaller height than the anti-spacers such that the second masking layer surrounds sidewalls of the anti-spacers while exposing top surfaces of the anti-spacers.
• the second masking layer may be formed of a material different from the material of the sacrificial structures.
• Figures 6A-6E illustrate a method of forming a masking pattern by growing anti-spacers.
• mandrels may be formed from a hard mask layer or other material other than a photoresist layer, as discussed with reference to Figure 4A.
• the target layer 1 10 is provided. Details of the target layer 1 10 can be as described above in connection with Figure 3 A.
• a hard mask layer is formed over the target layer 1 10, and is patterned to form mandrels 330, as shown in Figure 6A.
• the mandrels 330 are spaced apart from one another with a first pitch Pl while exposing surfaces 1 12 of the target layer 1 10.
• Each of the mandrels 330 has a top surface 332 and side surfaces 334. Other details of this step can be as described above in connection with Figure 4A.
• a sacrificial material such as an organic material, is grown on the top and side surfaces 332, 334 of the mandrels 330, while exposing substantial portions of the exposed surfaces 112 of the target layer 1 10.
• organic materials include, but are not limited to, perhydropolysilazane (PHPS) or polyhedral oligomeric silsesquioxanes (POSS).
• PHPS perhydropolysilazane
• PES polyhedral oligomeric silsesquioxanes
• the organic material can be grown by a diffusion limited growth technique.
• the reaction temperature may be between about 100 0 C and about 18O 0 C, which may be below the glass transition temperature Tg of the original mandrel material.
• Attachment of the sacrificial material may be catalyzed by another wet treatment or a material that may be present in the chemical formulation of the mandrel.
• Critical dimensions can then be modulated by controlling reaction temperature in combination with the chemical compositions used in the sacrificial material.
• the organic material forms anti-spacers 650 that include top portions 652 and side portions 654 covering the top and side surfaces 332. 334, respectively, of the mandrels 330.
• a second masking layer 640 is blanket deposited by, for example, spin-on deposition, over the anti-spacers 650 and the exposed surfaces 1 12 of the target layer 1 10.
• the second masking layer 440 may be formed of a silicon hard mask material, such as STHl 125B manufactured by Shin-Etsu Chemical Co., Ltd (Tokyo, Japan) or similar commercial hardmask material readily available to those versed in the art. Other details of this step can be as described above in connection with Figure 5C.
• the second masking layer 640 may be formed to have a thickness sufficient to slightly cover top portions 652 of the anti-spacers 650. Portions of the second masking layer 640 overlying the top portions 652 of the anti-spacers 650 may be referred to as "top coats " in the context of this document.
• the structure resulting from the step of Figure 6C is subjected to a chemical descum process.
• the chemical descum process serves to remove the top coats of the second masking layer 640, thereby exposing the top portions 652 of the anti-spacers 650.
• the chemical descum may be performed using a wet etch or a plasma etch such as a buffered oxide etch (BOE) dip process or Argon sputter etch.
• Tetram ethyl ammonium hydroxide (TMAH) developer can also be used to clean up these feature areas at a temperature ranging from about 10 0 C to about 5O 0 C.
• the structure resulting from the step of Figure 6D is subjected to an etch process to remove the anti-spacers 650.
• Any suitable etchant may be used to remove the anti-spacers 650, depending on the organic material.
• the etchant can be a dry etchant, such as O 2 or halide-based plasma, or a wet etchant, such as tetramethylammonium hydroxide (TMAH), propylene glycol monomethyl ether (PGME), propylene glycol monomethyl ether acetate (PGMEA), or any other suitable organic solvent.
• TMAH tetramethylammonium hydroxide
• PGME propylene glycol monomethyl ether
• PGMEA propylene glycol monomethyl ether acetate
• This step exposes the mandrels 330 formed of the hard mask material while defining intervening mask features 645 formed of the silicon hard mask material or mandrel material that may have used a process to ensure that its solubility is compatible with the wet etch.
• processes can be “freeze” techniques and they serve to limit the solubility of the mandrels in a wet etch process.
• These "freeze” techniques can take on various forms, for example, a thermal cross linking agent in a resist.
• the mandrels 330 and the intervening mask features 645 together define a second pattern 660.
• the second pattern 660 has a second pitch P2 between a mandrel 330 and a neighboring intervening mask feature 645.
• the second pitch P2 is about half of the first pitch Pl in the illustrated embodiment.
• Other details of this step can be as described above in connection with Figure 3H.
• the step shown in Figure 6E can be followed by steps as described above in connection with Figures 31 to 3K to transfer the second pattern 660 into the target layer 1 10.
• Figures 7A-7F illustrate a method of forming a masking pattern using anti- spacers in accordance with yet other embodiments.
• mandrels may be fo ⁇ ned from a hard mask layer or any other suitable material, using a process that allows selective growth of anti-spacers.
• a photoresist can be used in the step shown in Figure 7A as long as it is appropriately mated to the processing requirements, e.g., with regard to solubility.
• a photoresist used herein can withstand subsequent process steps. This can be achieved with a different solvent resist system, such as an alcohol- based resist or can be achieved with a "freeze " technique.
• the method includes providing the target layer 1 10. Details of the target layer 1 10 can be as described above in connection with Figure 3A. A hard mask layer is formed over the target layer 1 10, and is patterned to form mandrels 330, as shown in Figure 7A. The mandrels 330 are spaced apart from one another with a first pitch Pl while exposing surfaces 112 of the target layer 110. Each of the mandrels 330 has a top surface 332 and side surfaces 334. Other details of this step can be as described above in connection with Figure 4A.
• a reactivity promoter 655 is deposited on the top and side surfaces 332, 334 of the mandrels 330 without covering the exposed surfaces 1 12 of the target layer 1 10.
• the reactivity promoter serves to facilitate the growth of an organic material on the surfaces of the mandrels 330 at the next step.
• examples of such reactivity promoters include, but are not limited to, AZ materials used in RELACS (Resolution Enhancement Lithography Assisted by Chemical Shrink) processes, and a material including a hydroxyl group or organic acid designed to condition the reactivity of the mandrels to a material that covers the mandrels.
• a sacrificial material such as an organic material, is grown on the top and side surfaces 332, 334 of the mandrels 330 that are covered with the reactivity promoter 655.
• the organic material does not cover the exposed surfaces 1 12 of the target layer 1 10 except for portions 1 12a of the exposed surfaces 1 12 proximate to the mandrels 330.
• Examples of such organic materials include, but are not limited to, PHPS or a chain hydrocarbon with a bonding affinity to the mandrels covered with the reactivity promoter.
• the organic material can be grown by a diffusion limited growth technique by means of a fluid overcoat at a controlled temperature, for example, in a range between about 10 0 C and about 180 0 C. .
• the organic material forms anti-spacers 650 that cover the top and side surfaces 332, 334 of the mandrels 330.
• a second masking layer 640 is blanket deposited by, for example, spin-on deposition, over the anti-spacers 650 and the exposed surfaces 1 12 of the target layer 1 10.
• the second masking layer 640 can optionally cover top surfaces of the anti-spacers 650.
• the second masking layer 640 may be formed of, for example, a silicon hard mask material. The details of this step can be as described above in connection with Figure 6C.
• the structure resulting from the step of Figure 7E is subjected to an etch process to remove the anti-spacers 650.
• the details of this step can be as described above in connection with Figure 6E.
• This step exposes the mandrels 330 formed of the hard mask material while defining intervening mask features 645 fo ⁇ ned of the material forming the second masking layer 640, e.g., a silicon hard mask material.
• the mandrels 330 and the intervening mask features 645 together define a second pattern 660.
• the second pattern 660 has a second pitch P2 between a mandrel 330 and a neighboring intervening mask feature 645.
• the second pitch P2 is about half of the first pitch Pl in the illustrated embodiment.
• Other details of this step can be as described above in connection with Figure 3H.
• the step shown in Figure 7F can be followed by steps as described above in connection with Figures 31 to 3K to transfer the second pattern 660 into the target layer 1 10.
• Figures 8A-8F illustrate a method of forming a masking pattern using anti- spacers in accordance with yet other embodiments.
• mandrels may be formed from a hard mask layer or any other suitable material compatible with blanket deposition of an anti-spacer material, including materials discussed with reference to Figure 4A.
• the method includes providing a target layer 1 10. Details of the target layer 110 can be as described above in connection with Figure 3A. A hard mask layer is formed over the target layer 110, and is patterned to form mandrels 330. as shown in Figure 8A. The mandrels 330 are spaced apart from one another with a first pitch Pl while exposing surfaces 1 12 of the target layer 110. Each of the mandrels 330 has a top surface 332 and side surfaces 334. Other details of this step can be as described above in connection with Figure 4A.
• a sacrificial material is conformally deposited on the top and side surfaces 332. 334 of the mandrels 330 and the exposed surfaces 1 12 of the target layer 1 10.
• sacrificial materials include, but are not limited to, BARC, DARC, photoresist, silicon-on-glass (SOG), and hardmask type material.
• the sacrificial material can be deposited by, for example, spin-on coat or deposition.
• Portions 852, 854 of the sacrificial material that cover the top and side surfaces 332. 334, respectively, of the mandrels 330 form anti-spacers 850.
• Portions 855 of the sacrificial material formed on the surfaces 1 12 of the target layer 1 10 may be referred to as "partial gap fillers " in the context of this document.
• a second masking layer 640 is deposited over the partial gap fillers 855 and can also extend over the anti-spacers 850. Other details of this step can be as described above in connection with Figure 6C.
• the structure resulting from the step of Figure 8D is subjected to an etch process to remove the anti-spacers 850.
• the etch process may use an anisotropic etch process, using any suitable dry etchant, such as C 2 F4, O 2 , Hbr, or F 2 .
• the etchant can be a dry etchant, such as C 2 F 4 , O 2 , Hbr, and F 2 .
• This step exposes the mandrels 330 formed of the hard mask material while defining intervening mask features 845 between the mandrels 330.
• Each of the features 845 includes a structure 645 formed of the silicon hard mask material and a partial gap filler 855 underlying the structure 645.
• the mandrels 330 and the intervening mask features 845 together define a second pattern 860.
• the second pattern 860 has a second pitch P2 between a mandrel 330 and a neighboring intervening mask feature 845.
• the second pitch P2 is about half of the first pitch Pl in the illustrated embodiment.
• Other details of this step can be as described above in connection with Figure 3H.
• the step shown in Figure 8E can be followed by steps as described above in connection with Figures 31 to 3K to transfer the second pattern 860 into the target layer 1 10.
• a masking pattern fo ⁇ ned by the methods described herein may be used for further pitch multiplication.
• the pitch of the masking pattern may be further reduced by conducting an additional process using anti-spacers.
• anti-spacers may be formed around the mask features left after anti-spacer removal, e.g., including the mandrels 234 and intervening mask features 248, as shown in Figure 31, and the pitch of the resulting features can be reduced to about half of the second pitch P2.
• a second set of anti-spacers are formed around and optionally over the mask features by repeating the steps of Figures 3D-3I, Figures 4A-4E, Figures 5A-5C, Figures 6A-6D, Figures 7A-7E, or Figures 8A-8D.
• the second set of anti-spacers may be fo ⁇ ned by depositing a third masking layer to at least partially bury the second pattern and chemically altering portions of the third masking layer to form the second set of anti-spacers, as in the steps shown in Figures 3D-31.
• Figures 4A-4E, or Figures 5A-5C are examples of the second set of anti-spacers.
• the second set of anti-spacers may be formed by growing a second set of anti-spacers on the mask features, as in the steps shown in Figures 6A-6D, Figures 7A-7E, or Figures 8A-8D, and a third masking layer is deposited to fill spaces between the mask features covered with the anti-spacers.
• the second set of anti-spacers are removed while leaving at least portions of the third masking layer to form additional intervening mask features.
• the mandrels, the intervening mask features, and the additional intervening mask features together define a third pattern having a pitch that is about a half of the pitch of the second pattern.
• a masking pattern formed by the methods described above may be used for additional pitch multiplication in combination with a process employing so-called spacers.
• Figures 9A- 9D illustrate a method of forming a masking pattern, using anti-spacers and spacers in accordance with one embodiment.
• features forming a masking pattern can have a smaller pitch than the pitches P2 of the second patterns 260. 360, 460, 660, and 860 described above in connection with Figure 31, 4G, 5D, 6E, 7F. and 8E.
• the target layer 1 10 is provided.
• the details of the target layer 1 10 can be as described above in connection with Figures 3A, 4A, 5A, 6A, 7A, and 8 A.
• a first pattern 920 is fo ⁇ ned on the target layer 110.
• the first pattern 920 may include mandrels 922 and intervening mask features 924.
• the mandrels 922 and the intervening mask features 924 may be collectively referred to as "'first masking features. "1
• the mandrels 922 and the intervening mask features 924 can be fo ⁇ ned by the method described above in connection with Figures 3A-3I, Figures 4A-4G. Figures 5A-5D, Figures 6A-6E, Figures 7A-7F, or Figures 8A-8E.
• one or more hard mask layers can be formed on the target layer 1 10, and the first pattern 920 can be formed on the one or more hard mask layers.
• the first pattern 920 may correspond to any one of the second patterns 260, 360, 460, 660. and 860 described above in connection with Figure 31, 4G, 5D, 6E, 7F, and 8E.
• the mandrels 922 have a first pitch Pl therebetween.
• two neighboring first masking features i.e., a mandrel 922 and a neighboring intervening mask feature 924.
• the first masking features 922. 924 in the first pattern 920 may be trimmed or shrunk by an isotropic etching process to increase the distance between neighboring features.
• a layer 930 of spacer material may be blanket-deposited conformally over exposed surfaces, including the target layer 110 and the tops and sidewalls of the first masking features 922, 924.
• the spacer material can be any material capable of use as a mask to transfer a pattern to the underlying target layer 110.
• the spacer material preferably: 1) can be deposited with good step coverage, 2) can be deposited at a temperature compatible with the target layer 1 10 and 3) can be selectively etched relative to the target layer 1 10.
• the spacer material 930 is silicon oxide.
• the spacer material may be polysilicon or a low temperature oxide (LTO).
• the spacer material may be deposited by any suitable method, including, but not limited to. chemical vapor deposition (CVD). atomic layer deposition (ALD), spin- coating, or casting. ALD may have the advantages of both low temperature deposition and high conformality.
• the thickness of the layer 930 corresponds to the width of the spacers 935 and may be determined based upon the desired width of those spacers 935 ( Figure 9C). For example, in some embodiments, the layer 930 may be deposited to a thickness of about 20-80 nm and, optionally, about 40-60 nm. In some embodiments, the step coverage is about 80% or greater and, optionally, about 90% or greater.
• the spacer material may be one of a class of materials available from Clariant International, Ltd. (so-called "AZ R” materials), such as the materials designated as AZ R200TM, AZ R500TM, and AZ R600 1 M .
• the spacer material may be an "AZ R" material with one or more inorganic components (e.g.. one or more of titanium, carbon, fluorine, bromine, silicon, and germanium) dispersed therein.
• the "AZ R " materials contain organic compositions which cross-link upon exposure to acid released from chemically-amplified resist.
• an "AZ R" material may be coated across photoresist, and subsequently the resist may be baked at a temperature of about 100 0 C to about 120 0 C to diffuse acid from the resist and into the "AZ R " material to fo ⁇ n chemical cross-links within regions of the material proximate the resist. Portions of the material adjacent the resist are thus selectively hardened relative to other portions of material in which acids have not diffused. The material may then be exposed to conditions which selectively remove the non-hardened portions relative to the hardened portions. Such removal may be accomplished using, for example, 10% isopropyl alcohol in the ionized water, or a solution marketed as "'SOLUTION cTM " by Clariant International, Ltd.
• the spacer layer 930 is then subjected to an anisotropic etch to remove spacer material from horizontal surfaces 912 of the target layer 1 10 and the first masking features 922, 924.
• an etch also known as a spacer etch, can be performed on the silicon oxide material, using a fluorocarbon plasma, e.g., containing CF 4 /CHF 3 , C 4 FsZCH 2 F 2 or CHF 3 /Ar plasma.
• the etchants are chosen to be selective for the spacer material relative to the target layer 1 10.
• the first masking features 922, 924 are removed to leave freestanding spacers 935.
• the first masking features 922, 924 may be removed by an oxygen-containing plasma etch, such as an etch using HBr/O 2 /N 2 and
• the spacers 935 fonn a second pattern 950 having a third pitch P3.
• the third pitch P3 is roughly half of the second pitch P2 between neighboring first masking features 922, 924 in the first pattern 920.
• first pitch Pl is about 200 nm
• spacers 935 having a pitch of about 50 run or less can be formed.
• the second pattern 950 provided by the spacers 935 is transferred into the target layer 1 10 (not shown).
• the pattern transfer can be performed using any suitable etch process selective for the target layer 1 10 relative to the spacers 935. Other details of this step can be as described above with reference to Figure 3K or 4H.
• the target layer 1 10 may be further processed to form complete IC devices.
• three dimensional structures can be formed by the methods described The three dimensional structures can include, but are not limited to, lines, trenches, vias, pillars, posts, troughs, and moats.
• Figures 10A-12C illustrate a method of forming an array of isolated trenches or vias in a target layer, using anti-spacers in accordance with some embodiments.
• mandrels 1020 extending in the y- direction are fo ⁇ ned by, for example, depositing and patterning a first resist layer on the target layer 1 10, as described above in connection with Figure 3C.
• a second resist layer 1040 is fo ⁇ ned over the mandrels 1020 and the target layer 1 10.
• First anti-spacers 1050 extending in the y-direction are formed around and on top of the mandrels 1020, thereby defining intervening mask features 1048 extending in the y-direction.
• the details of these steps can be as described above in connection with Figures 3D-3G.
• mandrels 1 120 extending in the x-direction are formed by depositing and patterning a third resist layer on the second resist layer 1040 in the manner described above in connection with Figure 3C.
• a fourth resist layer 1 140 is formed over the mandrels 1 120 and the second resist layer 1040.
• Second anti-spacers 1 150 extending in the x-direction are formed around and on top of the mandrels 1120, thereby defining intervening mask features 1 148 extending in the x-direction. The details of this process can be as described above in connection with Figures 3D-3G.
• the structure shown in Figures 1 IA-1 1C is subjected to development using a suitable developer.
• the developer removes the second anti-spacers 1 150, thereby exposing parts of the first anti-spacers 1050 and the intervening mask features 1048.
• the developer further removes the exposed parts of the first anti-spacers 1050, thereby creating an array of holes 1 160 defined by the features 1020, 1048, 1 120, 1 148, as shown in Figures 12A and 12B.
• the holes 1005 can be filled with a mate ⁇ al (e g , a dielectric material, a conductive material, or a semiconductor) such that structures formed m the holes 1005 can serve as posts or pillars in a resulting electronic circuit
• a mate ⁇ al e g , a dielectric material, a conductive material, or a semiconductor
• the method described above may be adapted for forming isolated holes, e g , contact vias or trenches, depending on the design of the electronic circuit
• the mandrels 1020 and the intervening mask features 1048 extending m the y-direction can be formed by any of the methods desc ⁇ bed above in connection with Figures 3A-3I, Figures 4A-4G, Figures 5A-5D, Figures 6A-6E, Figures 7A-7F, or Figures 8A-8E
• the mandrels 1 120 and the intervening mask features 1 148 extending in the x-direction can be fo ⁇ ned over the mandrels 1020 and the intervening mask features 1048 by any of the methods desc ⁇ bed above in connection with Figures 3A-3I.
• a freeze step is required after forming the mandrels 1020 and the intervening mask features 1048 and before forming the mandrels 1 120 and the intervening mask features 1 148 In other embodiments, no freeze step is required after forming the mandrels 1020 and the intervening mask features 1048 and before fo ⁇ mng the mandrels 1 120 and the intervening mask features 1 148
• Figures 13A-15B illustrate a method of forming an array of pillars or posts in a target layer using anti-spacers
• mandrels 1320 extending in the y-direction are formed by depositing and patterning a first resist layer on the target layer 1 10, as desc ⁇ bed above in connection with Figure 3C
• Intervening mask features 1348 extending in the y-direction and alternating with the mandrels 1320 are fomied by forming and removing anti-spacers as descnbed above in connection with Figures 3D-3I
• a pattern defined by the mandrels 1320 and intervening mask features 1348 is transferred into the target layer HO m the manner desc ⁇ bed above in connection with Figure 3K
• Exposed portions of the target layer 1 10 are etched, as shown in Figure 13B, defining elongated trenches or troughs 1302 alternating with elongated mesas 1301 (
• the deposition of the third resist layer wipes the pattern formed by the mandrels 1320 and the intervening mask features 1348 (the deposited resist blends with the existing resist).
• intervening mask features 1448 extending in the x-direction and alternating with the mandrels 1420 are formed by fo ⁇ ning and removing anti-spacers in the manner described above in connection with Figures 3D-31.
• a pattern defined by the mandrels 1420 and the intervening mask features 1448 is transferred into the target layer 1 10, as shown in Figures 15A and 15B. in the manner described above in connection with Figure 3K.
• Exposed portions of the elongated trenches or troughs 1302 of the target layer 110 are etched, as shown in Figure 15A. defining isolated holes or vias 1303 in the target layer 110.
• exposed portions of the mesas 1301 of the target layer 1 10 are etched, defining pillars or posts 1305, as shown in Figure 15B.
• a resulting structure in the target layer 1 10, which includes an array of isolated pillars or posts 1305 and isolated holes 1303, is shown in Figure 15C.
• the mandrels 1320 and the intervening mask features 1348 extending in the y-direction can be fo ⁇ ned by any of the methods described above in connection with Figures 3A-3I, Figures 4A-4G, Figures 5A-5D, Figures 6A-6E, Figures 7A-7F, or Figures 8A-8E.
• the mandrels 1420 and the intervening mask features 1448 extending in the x-direction can be fo ⁇ ned over the mandrels 1320 and the intervening mask features 1348 by any of the methods described above in connection with Figures 3A-3I, Figures 4A-4G, Figures 5A-5D, Figures 6A-6E, Figures 7A-7F, or Figures 8A-8E.
• Electronic devices such as IC devices, typically include a plurality of conductive lines (for example, interconnects) and landing contact pads that electrically connect the conductive lines to other levels in the IC.
• the "landing contact pads " may also be referred to as “landing pads " or "contact tabs.”
• the conductive lines typically have a width narrower than the widths of the landing pads.
• a conventional pitch multiplication process using spacers allows formation of conductive lines having a narrower line-width than that allowed by an available photolithographic process.
• spacers can only provide features having such a narrow line-width, it can be difficult to form larger width landing pads using spacers.
• a process involving anti-spacers may be used to simultaneously form conductive lines and landing pads integrated with the conductive lines. Such a process can provide a single masking pattern for fonning pitch-multiplied conductive lines as well as landing pads wider than the conductive lines.
• FIGS 16A-16C illustrate a method of forming conductive lines and landing pads in an electronic device (for example, an IC circuit), using anti-spacers in accordance with some embodiments.
• mandrels 1620 are formed over a target layer 1 10 that is formed of a conductive material, such as copper, gold, silver, or an alloy thereof.
• Each of the mandrels 1620 may include a line mask feature 1622 that has a first width LWl, and a landing pad mask feature 1624 that has a second width LW2.
• the landing pad mask feature 1624 is connected to one end of the line mask feature 1622.
• the line mask features 1622 of the mandrels 1620 extend parallel to one another. In other embodiments, the configurations of the line mask features 1622 of the mandrels 1620 can vary, depending on the design of the electronic device formed by the method.
• the second width LW2 can be selected, depending on the size of a landing pad to be formed in the target layer 1 10, and is greater than the first width LWl . In one embodiment, the second width LW2 is about 0.5 to about 5 times greater than the first width LWl .
• the illustrated landing pad mask feature 1624 has a substantially circular shape, but the skilled artisan will appreciate the landing pad mask feature 1624 can have various other shapes such as a square shape, a rectangular shape, an oval shape, or the like, depending on the desired shape of the landing pad.
• the mandrels 1620 can be formed as described above in connection with Figures 3A-3C.
• intervening mask features 1630 are formed between two neighboring ones of the mandrels 1620 by forming and removing anti-spacers (not shown).
• Each of the intervening mask features 1630 may include a line mask feature 1632 that has a third width LW3, and a landing pad mask feature 1634 that has a fourth width LW4
• the line mask features 1632 of the intervening mask features 1630 extend parallel to one another and to the line mask featuies 1622 of the mandrels 1620
• the third width LW3 is substantially the same as the first width LWl.
• the fourth width LW4 is substantially the same as the second width LW2
• the thud width LW3 can be different from the first width LWl
• the fourth width LW4 can be different fiom the second width LW2
• the intervening mask features 1630 can be formed as descnbed above in connection with Figures 3D-3I
• mandrels 1620 and the intervening mask features 1630 can be formed by any of the methods descnbed above m connection with Figures 4A-4G. Figuies 5A-5D Figures 6A-6E, Figuies 7A-7F, or Figures 8A-8E
• a cut mask 1650 is provided over the structure of Figure 16B
• the cut mask 1650 includes an opening 1652 that exposes parts of the landing pad mask features 1634 of the intervening mask features 1630 (and optionally end parts of the landing pad mask featuies 1624 of the mandrels 1620) while blocking the other portions of the features 1620.
• the opening 1652 is shaped such that the landing pad mask features 1634 of the intervening mask features 1630 are electrically separated from one another by a subsequent etch process
• the exposed parts of the landing pad mask features 1624, 1634 of the features 1620, 1630 are removed by any suitable etch piocess that can remove the materials of the landing pad mask features selectively relative to the target layer 1 10
• a pattern formed by the features 1620, 1630 shown in Figure 16B is first transferred into the target layer 1 10, and then landing pads are defined by another etch step so as to be electrically isolated from one another
• the landing pads can be formed simultaneously with conductive lines, thus eliminating separate steps for defining and connecting the landing pads to conductive lines.
• the pitch of the conductive lines can be reduced at least to the same extent as in a conventional pitch multiplication process using spacers. While the embodiments above were described in connection with forming conductive lines and landing pads, the skilled artisan will appreciate that the embodiments can be adapted for forming various other structures or parts of electronic devices where different shapes or sizes of features are formed simultaneously.
• electronic devices such as arrays in ICs, can be made by the methods described above.
• the electronic devices may also include a system including a microprocessor and/or a memory device, each of which includes features arranged in an array.
• a system may be a computer system, an electronic system, or an electromechanical system.
• Examples of electronic devices include, but are not limited to, consumer electronic products, electronic circuits, electronic circuit components, parts of the consumer electronic products, electronic test equipments, etc.
• the consumer electronic products may include, but are not limited to, a mobile phone, a telephone, a television, a computer monitor, a computer, a hand-held computer, a personal digital assistant (PDA), a microwave, a refrigerator, a stereo system, a cassette recorder or player, a DVD player, a CD player, a VCR, an MP3 player, a radio, a camcorder, a camera, a digital camera, a portable memory chip, a washer, a dryer, a washer/dryer, a copier, a facsimile machine, a scanner, a multi functional peripheral device, a wrist watch, a clock, etc.
• the electronic device may include unfinished intermediate products.
• a method of forming features in an electronic device includes forming mandrels defining a first pattern in a first masking layer on one or more underlying layers comprising a target layer.
• the first pattern includes spaces between the mandrels, and has a first pitch.
• the method also includes depositing a second masking layer to at least partly fill the spaces of the first pattern.
• the second masking layer contacts the one or more underlying layers through the spaces between the mandrels.
• the method further includes forming sacrificial structures to define gaps between at least parts of the mandrels and at least parts of the second masking layer; and after depositing the second masking layer and forming the sacrificial structures, removing the sacrificial structures to define a second pattern having a second pitch smaller than the first pitch.
• the second pattern includes the at least parts of the mandrels and intervening mask features alternating with the at least parts of the mandrels.
• a method of forming features in an electronic device includes photolithographic ally fo ⁇ ning mandrels defining a first pattern in a first masking layer over a target layer.
• the first pattern includes spaces between the mandrels, and has a first pitch.
• the method also includes depositing a second masking layer to at least partially fill the spaces of the first pattern; fo ⁇ ning sacrificial structures to define gaps between at least parts of the mandrels and at least parts of the second masking layer; and after depositing the second masking layer and forming the sacrificial structures, removing the sacrificial structures to define a second pattern having a second pitch smaller than the first pitch.
• the second pattern includes the at least parts of the mandrels and intervening mask features alternating with the at least parts of the mandrels.
• a method of forming an integrated circuit includes fo ⁇ ning a first pattern comprising first lines extending substantially parallel to one another in a first direction over a target layer.
• Forming the first pattern includes: providing first mandrels in a first masking layer over the target layer, the first mandrels having spaces therebetween; depositing a second masking layer to at least partially fill the spaces between the first mandrels; and forming first sacrificial structures to define gaps between at least parts of the first mandrels and at least parts of the second masking layer.
• the method also includes fomiing a second pattern comprising second lines extending substantially parallel to one another in a second direction over the first pattern, the second direction being different from the first direction.
• Forming the second pattern includes: providing second mandrels in a third masking layer over the second masking layer, the second mandrels having spaces therebetween; depositing a fourth masking layer to at least partially fill the spaces between the second mandrels; and forming second sacrificial structures to define gaps between at least parts of the second mandrels and at least parts of the fourth masking layer.
• the method further includes: removing the first sacrificial structures; removing the second sacrificial structures; and etching the target layer through the first pattern, the second pattern, or a combination of the first and second patterns.

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