WO2009122680A1 - 多層回路基板、絶縁シート、および多層回路基板を用いた半導体パッケージ - Google Patents
多層回路基板、絶縁シート、および多層回路基板を用いた半導体パッケージ Download PDFInfo
- Publication number
- WO2009122680A1 WO2009122680A1 PCT/JP2009/001331 JP2009001331W WO2009122680A1 WO 2009122680 A1 WO2009122680 A1 WO 2009122680A1 JP 2009001331 W JP2009001331 W JP 2009001331W WO 2009122680 A1 WO2009122680 A1 WO 2009122680A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- insulating layer
- circuit board
- multilayer circuit
- interlayer insulating
- resin
- Prior art date
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
- H01L23/49894—Materials of the insulating layers or coatings
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4688—Composite multilayer circuits, i.e. comprising insulating layers having different properties
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0104—Properties and characteristics in general
- H05K2201/0133—Elastomeric or compliant polymer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0183—Dielectric layers
- H05K2201/0195—Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
Definitions
- the present invention relates to a multilayer circuit board, an insulating sheet, and a semiconductor package using the multilayer circuit board.
- a conventional semiconductor package using a lead frame has a limit in miniaturization, and recently, such as a ball grid array (BGA) in which a semiconductor chip is mounted on a circuit board and a chip scale package (CSP).
- BGA ball grid array
- CSP chip scale package
- An area mounted semiconductor package system has been proposed.
- a wire bonding method, a TAB (Tape Automated Bonding) method, and a flip chip (FC) method are known as methods for connecting a semiconductor chip mounted on a BGA to a circuit board.
- TAB Transmission Automated Bonding
- FC flip chip
- the flip-chip connection method has an advantage that the mounting area can be reduced as compared with the wire bonding connection method.
- flip-chip mounting is characterized by good electrical characteristics due to short circuit wiring.
- Flip chip mounting is an excellent connection method for circuits of portable devices that are strongly demanded to be small and thin, and high-frequency circuits where electrical characteristics are important.
- an interposer for connecting a semiconductor chip generally has a core layer, a conductor circuit layer, and an insulating layer.
- this multilayer circuit board has a thinner core layer or a wiring pattern formed on resin without providing a core layer.
- a thin build-up interposer has been proposed in which the thickness of the entire interposer is reduced and the interlayer connection length is shortened to cope with a high frequency.
- a reinforcing resin composition (underfill) is usually filled in the gap between the semiconductor chip and the circuit board in order to ensure the reliability of the joints such as the semiconductor chip, circuit board, and metal bump.
- thermosetting resins such as epoxy resins have been widely used as underfill materials.
- This semiconductor package is a semiconductor in which the active surface of a silicon chip is electrically connected to the circuit board through a conductive material with the active surface of the silicon chip facing the circuit board, and the gap between the silicon chip and the circuit board is filled and cured with a thermosetting resin composition. It is a package.
- this thermosetting resin composition has a linear aliphatic hydrocarbon compound having 10 to 30 carbon atoms that is chemically bonded to the thermosetting resin. While having high temperature cycle reliability, the silicon chip can be removed at a low temperature and with a small shearing force and without damaging the silicon chip or the circuit board. (For example, see Patent Document 2.)
- Patent Documents 3 and 4 there are those described in Patent Documents 3 and 4 as interlayer insulating layers used for multilayer printed wiring boards.
- Patent Document 3 describes that copper foils are stacked via a single prepreg.
- Patent Document 4 describes that prepregs are stacked and copper foils are disposed on both sides thereof and stacked. That is, the interlayer insulating layer sandwiched between the wirings is formed from a resin layer made of the same material.
- JP 2006-24842 A JP-A-11-233571 JP 2007-59838 A JP 2008-37881 A
- the conductor circuit layer and the insulating resin layer generally have different linear expansion coefficients, and the semiconductor chip mounting side and the opposite side have different conductor circuits.
- the conductor circuit is different, the degree of restraint between the conductor circuit and the insulating resin is different, and the lower the restraint, the greater the fluctuation due to the difference in the coefficient of linear expansion between the conductor circuit and the resin.
- the yield of semiconductor chip mounting becomes very bad, which causes a decrease in semiconductor package reliability.
- warping has occurred due to the difference in the coefficient of linear expansion between the interlayer insulating layer sandwiched between the conductor circuits and the conductor circuits. Further, the warping direction tends to be determined in either the convex direction or the concave direction for each circuit board.
- the present invention has been made in view of the above circumstances, and aims to solve the problems in the prior art.
- the insulating resin layers between the circuit layers of the multilayer circuit board are a plurality of insulating resin layers having different elastic moduli.
- the insulating resin layer having a low elastic modulus serves as a buffer material, and warpage between circuit layers can be suppressed. Thereby, it becomes possible to suppress the curvature of the whole multilayer circuit board.
- the insulating resin layer having a low elastic modulus is a cushioning material against warping in any direction, so that the multilayer circuit Warpage of the entire substrate can be suppressed. Therefore, a multilayer circuit board can be used regardless of the type of semiconductor chip.
- An object of the present invention is to provide a multilayer circuit board, an insulating sheet, and a semiconductor package that can improve the yield of semiconductor chip mounting and the reliability of semiconductor packages.
- a multilayer circuit board in which conductor circuit layers and interlayer insulating layers are alternately laminated The multilayer circuit board, wherein the interlayer insulating layer includes a first insulating layer and a second insulating layer having a higher elastic modulus than the first insulating layer.
- the interlayer insulating layer includes a first insulating layer and a second insulating layer having a higher elastic modulus than the first insulating layer.
- a multilayer circuit board wherein the interlayer insulating layer is laminated in the order of a first insulating layer, a second insulating layer, and a first insulating layer.
- a multilayer circuit board comprising: a laminated structure of the interlayer insulating layer; and a second interlayer insulating layer made of the second insulating layer.
- the multilayer circuit board wherein the interlayer insulating layer is made of a resin composition containing a cyanate resin.
- the multilayer circuit board, wherein the cyanate resin is a novolac type cyanate resin.
- the multilayer circuit board further includes a core layer, The interlayer insulating layer is laminated above and below the core layer, 2.
- a multilayer circuit board, wherein the laminated structure of the interlayer insulating layers located symmetrically with respect to the core layer is the same.
- the interlayer insulating layer includes a first insulating layer, and a second insulating layer having a higher elastic modulus than the first insulating layer, As a result, warpage of the entire multilayer circuit board can be suppressed, and the yield of semiconductor chip mounting and the reliability of semiconductor packages can be improved.
- a multilayer circuit board 1 is a multilayer circuit board 1 having conductor circuit layers 11 and interlayer insulation layers 6 alternately, and builds up an interlayer insulation layer 6 and conductor circuit layers 11 on a core layer 5.
- the multilayer circuit board 1 is manufactured as described above.
- the interlayer insulating layer 6 used for the multilayer circuit board 1 in which the conductor circuit layers 11 and the interlayer insulating layers 6 are alternately laminated is constituted by an insulating sheet.
- the elastic modulus of the first insulating layer is (Ea)
- the elastic modulus of the second insulating layer is (Eb)
- the elastic modulus is obtained by dynamic viscoelasticity measurement at a frequency of 10 Hz.
- the characteristics of the interlayer insulating layer 6 include a first insulating layer and a second insulating layer having different elastic moduli. Regarding the relationship between the elastic moduli of the first insulating layer and the second insulating layer, the elastic modulus of the first insulating layer is preferably lower than the elastic modulus of the second insulating layer. By using a plurality of insulating layers having different elastic moduli, it is possible to suppress warping of the entire multilayer circuit board 1.
- the relationship between the elastic moduli of the first insulating layer and the second insulating layer is preferably (Eb / Ea)> 3.
- the 1st insulating layer of the interlayer insulation layer 6 becomes a buffer material, and the curvature of the multilayer circuit board 1 whole can be suppressed.
- the elastic modulus (Ea) of the first insulating layer is (Ea) ⁇ 2 GPa, more preferably (Ea) ⁇ 1 GPa. Thereby, it becomes a buffer material which relieves the curvature of the whole multilayer circuit board 1 more.
- the elastic modulus (Eb) of the second insulating layer is (Eb) ⁇ 4 GPa, more preferably (Eb) ⁇ 5 GPa. Thereby, curvature can be further suppressed.
- the glass transition temperature of the cured product of the second insulating layer is 170 ° C. or higher, and the linear expansion coefficient in the in-plane direction below the glass transition temperature is 40 ppm / ° C. or lower.
- the linear expansion coefficient in the in-plane direction can be evaluated by elevating the temperature at 10 ° C./min using, for example, a TMA apparatus (manufactured by TA Instruments). If the linear expansion coefficient of the cured product of the second insulating layer is greater than 40 ppm / ° C, it will be more than twice as large as the linear expansion coefficient (17-18 ppm / ° C) of copper used in normal circuits, and this may cause warpage. Become.
- the linear expansion coefficient below the glass transition temperature is 10 to 35 ppm / ° C., more preferably 15 to 30 ppm / ° C.
- the first insulating layer relaxes the strain due to the difference in linear expansion coefficient, and the handling property and workability at the time of manufacturing the semiconductor package are improved.
- the thickness of the interlayer insulating layer 6 is 10 to 60 ⁇ m, preferably 20 to 50 ⁇ m. Among them, the thickness of the first insulating layer is preferably 3 to 20 ⁇ m, and the thickness of the second insulating layer is preferably 10 to 50 ⁇ m.
- the conductor circuit layer 11 is not particularly limited as long as it is a conductive metal, but is preferably made of copper or a copper alloy and patterned into a necessary circuit shape.
- the conductor circuit layer of the core layer 5 is mainly formed by patterning a core material with copper foil by a subtractive method, and the conductor circuit layer 11 formed on the interlayer insulating layer 6 is mainly patterned by a semi-additive method or a full additive method.
- the thickness of the core layer 5 is preferably 500 ⁇ m or less, more preferably 50 ⁇ m to 400 ⁇ m.
- the multilayer circuit board 1 includes a core layer 5, for example, 2 to 10 conductor circuit layers 11 and an interlayer insulating layer 6. Preferably, two to six conductor circuit layers 11 and an interlayer insulating layer 6 are included.
- the outer surface of the multilayer circuit board 1 may be provided with a heat resistant coating layer such as a solder resist for the purpose of protecting the conductor and maintaining the insulation.
- the material used for the insulating layer of the core layer 5 in the multilayer circuit board 1 is not particularly limited as long as it has an appropriate strength.
- epoxy resin, phenol resin, cyanate resin, triazine resin A plate formed by impregnating a fiber base material (for example, a glass fiber sheet) with a resin composition of at least one or more of bismaleimide resin, polyimide resin, polyamideimide resin, and benzocyclobutene resin.
- the material (so-called prepreg) can be preferably used.
- a plate-like material obtained by impregnating a fiber base material (for example, a glass fiber sheet) with a resin composition containing a cyanate resin, a phenol resin, an epoxy resin, and an inorganic filler and semi-curing it.
- a fiber base material for example, a glass fiber sheet
- a resin composition containing a cyanate resin, a phenol resin, an epoxy resin, and an inorganic filler and semi-curing it can be used.
- the materials used for the first insulating layer and the second insulating layer of the interlayer insulating layer 6 are the glass transition temperature, elastic modulus, and linear expansion of the cured products of the first insulating layer and the second insulating layer described above.
- the resin composition containing a thermosetting resin it is preferable to be comprised with the resin composition containing a thermosetting resin.
- the resin composition used for the second insulating layer of the interlayer insulating layer 6 may be impregnated into a fiber base material such as a glass fiber sheet, or the resin composition may be cured as it is.
- the method for impregnating the fiber base material with the resin composition is not particularly limited.
- the interlayer insulation layer 6 with a carrier base material forms the interlayer insulation layer 6 comprised with the said resin composition in a carrier base material.
- thermosetting resin examples include an epoxy resin, a phenol resin, a cyanate resin, a triazine resin, a bismaleimide resin, a polyimide resin, a polyamideimide resin, a benzocyclobutene resin, a resin having a benzoxazine ring, and a urea (urea) resin.
- resins having a triazine ring such as melamine resin, unsaturated polyester resin, polyurethane resin, diallyl phthalate resin, and silicone resin.
- One of these can be used alone, two or more having different weight average molecular weights can be used in combination, or one or two or more thereof and a prepolymer thereof can be used in combination.
- the thermosetting resin is preferably an epoxy resin, a phenol resin, a cyanate resin, a triazine resin, a bismaleimide resin, a polyimide resin, a polyamideimide resin, a benzocyclobutene resin, or a resin having a benzoxazine ring. Or it includes multiple types.
- epoxy resin examples include bisphenol A epoxy resin, bisphenol F epoxy resin, bisphenol E type epoxy resin, bisphenol S type epoxy resin, bisphenol Z type epoxy resin, bisphenol P type epoxy resin, and bisphenol M type epoxy resin.
- Resin phenol novolac type epoxy resin, cresol novolac epoxy resin and other novolak type epoxy resin, biphenyl type epoxy resin, biphenyl aralkyl type epoxy resin, aryl alkylene type epoxy resin, naphthalene type epoxy resin, anthracene type epoxy resin, phenoxy type epoxy resin , Dicyclopentadiene type epoxy resin, norbornene type epoxy resin, adamantane type epoxy resin, fluorene type epoxy An epoxy resin such as a resin and the like.
- phenol resin examples include novolac type phenol resins such as phenol novolak resin, cresol novolak resin, bisphenol A novolak resin, unmodified resol phenol resin, oil-modified resol phenol resin modified with tung oil, linseed oil, walnut oil, and the like. And phenol resin such as resol type phenol resin.
- cyanate resins including prepolymers of cyanate resins
- the linear expansion coefficient of the interlayer insulation layer 6 can be made small.
- the interlayer insulating layer 6 is excellent in electrical characteristics (low dielectric constant, low dielectric loss tangent), mechanical strength, and the like.
- the cyanate resin can be obtained, for example, by reacting a halogenated cyanide compound with a phenol and prepolymerizing it by a method such as heating as necessary.
- Specific examples include bisphenol type cyanate resins such as novolak type cyanate resin, bisphenol A type cyanate resin, bisphenol E type cyanate resin, and tetramethylbisphenol F type cyanate resin.
- novolac type cyanate resin is preferable. Thereby, the heat resistance improvement by an increase in a crosslinking density and flame retardances, such as a resin composition, can be improved. This is because the novolac-type cyanate resin forms a triazine ring after the curing reaction. Furthermore, it is considered that novolak-type cyanate resin has a high benzene ring ratio due to its structure and is easily carbonized.
- the novolak type cyanate resin for example, the one represented by the formula (1) can be used.
- the average repeating unit n of the novolak cyanate resin represented by the above formula (1) is not particularly limited, but is preferably 1 to 10, and particularly preferably 2 to 7.
- the average repeating unit n is less than the above lower limit value, the novolak cyanate resin is easily crystallized, and the solubility in a general-purpose solvent is relatively lowered, which may make handling difficult.
- the average repeating unit n exceeds the above upper limit, the melt viscosity becomes too high, and the moldability of the interlayer insulating layer 6 may be lowered.
- the weight average molecular weight of the cyanate resin is not particularly limited, but a weight average molecular weight of 500 to 4,500 is preferable, and 600 to 3,000 is particularly preferable. If the weight average molecular weight is less than the above lower limit, the mechanical strength of the cured product of the interlayer insulating layer 6 may decrease, and when the interlayer insulating layer 6 is produced, tackiness may occur and transfer of the resin may occur. There is a case. Further, when the weight average molecular weight exceeds the above actual value, the curing reaction is accelerated, and when it is used as a substrate (particularly a circuit substrate), a molding defect may occur or the interlayer peel strength may be lowered.
- the weight average molecular weight of the cyanate resin and the like can be measured by, for example, GPC (gel permeation chromatography, standard substance: converted to polystyrene).
- the cyanate resin can be used alone, including its derivatives, or two or more having different weight average molecular weights can be used in combination, or one or two or more thereof. These prepolymers can also be used in combination.
- the content of the thermosetting resin is not particularly limited, but is preferably 5 to 50% by weight, particularly preferably 10 to 40% by weight, based on the entire resin composition. If the content is less than the lower limit, it may be difficult to form the interlayer insulating layer 6, and if the content exceeds the upper limit, the strength of the interlayer insulating layer 6 may be reduced.
- thermosetting resin When using a cyanate resin (particularly a novolac type cyanate resin) as the thermosetting resin, it is preferable to use an epoxy resin (substantially free of halogen atoms) in combination.
- epoxy resin examples include bisphenol A epoxy resin, bisphenol F epoxy resin, bisphenol E type epoxy resin, bisphenol S type epoxy resin, bisphenol Z type epoxy resin, bisphenol P type epoxy resin, and bisphenol M type epoxy resin.
- epoxy resin one of these can be used alone, or two or more having different weight average molecular weights can be used in combination, or one or two or more and those prepolymers can be used in combination. You can also
- aryl alkylene type epoxy resins are particularly preferable. Thereby, moisture absorption solder heat resistance and a flame retardance can be improved.
- the above arylalkylene type epoxy resin refers to an epoxy resin having one or more arylalkylene groups in a repeating unit.
- a xylylene type epoxy resin, a biphenyl dimethylene type epoxy resin, etc. are mentioned.
- a biphenyl dimethylene type epoxy resin is preferable.
- mold epoxy resin can be shown, for example by Formula (2).
- the average repeating unit n of the biphenyldimethylene type epoxy resin represented by the above formula (2) is not particularly limited, but is preferably 1 to 10, and particularly preferably 2 to 5.
- the average repeating unit n is less than the lower limit, the biphenyldimethylene type epoxy resin is easily crystallized, and its solubility in a general-purpose solvent is relatively lowered, which may make handling difficult.
- the average repeating unit n exceeds the above upper limit, the fluidity of the resin is lowered, which may cause molding defects.
- the content of the epoxy resin is not particularly limited, but is preferably 1 to 55% by weight, particularly preferably 5 to 40% by weight, based on the entire resin composition. If the content is less than the above lower limit, the reactivity of the cyanate resin may decrease, or the moisture resistance of the resulting product may decrease, and if the content exceeds the above upper limit, the low linear expansion and heat resistance will decrease. There is a case.
- the weight average molecular weight of the epoxy resin is not particularly limited, but the weight average molecular weight is preferably 500 to 20,000, and particularly preferably 800 to 15,000. If the weight average molecular weight is less than the lower limit, tackiness may occur on the surface of the interlayer insulating layer 6, and if it exceeds the upper limit, solder heat resistance may be reduced. By setting the weight average molecular weight within the above range, it is possible to achieve an excellent balance of these characteristics.
- the weight average molecular weight of the epoxy resin can be measured by, for example, GPC.
- the resin composition preferably contains a film-forming resin.
- a film-forming resin examples include phenoxy resins, bisphenol F resins, and olefin resins.
- the film-forming resin one kind including derivatives thereof can be used alone, or two or more kinds having different weight average molecular weights can be used in combination, or one kind or two kinds or more can be used.
- a prepolymer can also be used in combination.
- a phenoxy resin is preferable. Thereby, heat resistance and a flame retardance can be improved.
- phenoxy resin which has bisphenol A frame, phenoxy resin which has bisphenol F frame, phenoxy resin which has bisphenol S frame, phenoxy resin which has bisphenol M frame, and bisphenol P frame
- phenoxy resins having a bisphenol skeleton such as phenoxy resins having a bisphenol Z skeleton, phenoxy resins having a novolac skeleton, phenoxy resins having an anthracene skeleton, phenoxy resins having a fluorene skeleton, phenoxy resins having a dicyclopentadiene skeleton, norbornene skeleton Phenoxy resin having naphthalene skeleton, phenoxy resin having biphenyl skeleton, adamantane skeleton Such as that phenoxy resins, and the like.
- phenoxy resin a structure having a plurality of skeletons in these can be used, and phenoxy resins having different ratios of the skeletons can be used. Furthermore, a plurality of types of phenoxy resins having different skeletons can be used, a plurality of types of phenoxy resins having different weight average molecular weights can be used, or prepolymers thereof can be used in combination.
- a phenoxy resin having a biphenyl skeleton and a bisphenol S skeleton can be used.
- the glass transition temperature can be increased due to the rigidity of the biphenyl skeleton, and the adhesion of the plating metal when the multilayer circuit board 1 is manufactured can be improved by the bisphenol S skeleton.
- a phenoxy resin having a bisphenol A skeleton and a bisphenol F skeleton can be used. Thereby, the adhesiveness to the inner layer circuit board can be improved when the multilayer circuit board 1 is manufactured. Further, the phenoxy resin having the biphenyl skeleton and the bisphenol S skeleton and the phenoxy resin having the bisphenol A skeleton and the bisphenol F skeleton may be used in combination.
- the molecular weight of the film-forming resin is not particularly limited, but the weight average molecular weight is preferably 1,000 to 100,000. More preferably, it is 10,000 to 60,000.
- the weight average molecular weight of the film forming resin is less than the lower limit, the effect of improving the film forming property may not be sufficient. On the other hand, when the above upper limit is exceeded, the solubility of the film-forming resin may decrease. By making the weight average molecular weight of the film-forming resin within the above range, it is possible to achieve an excellent balance of these characteristics.
- the content of the film-forming resin is not particularly limited, but is preferably 1 to 40% by weight based on the entire resin composition. More preferably, it is 5 to 30% by weight. If the content of the film-forming resin is less than the lower limit, the effect of improving the film-forming property may not be sufficient. On the other hand, when the above upper limit is exceeded, the content of the cyanate resin is relatively reduced, and thus the effect of imparting low linear expansion may be reduced. By setting the content of the film-forming resin within the above range, it is possible to achieve an excellent balance of these characteristics.
- both the thermosetting resin and the film-forming resin used for the interlayer insulating layer 6 are substantially free of halogen atoms.
- a flame retardance can be provided, without using a halogen compound.
- the phrase “substantially free of halogen atoms” means, for example, that the halogen atom content in the epoxy resin or phenoxy resin is 0.15 wt% or less (JPCA-ES01-2003).
- a curing accelerator may be used as necessary.
- a known product can be used as the curing accelerator.
- organometallic salts such as imidazole compounds, zinc naphthenate, cobalt naphthenate, tin octylate, cobalt octylate, bisacetylacetonate cobalt (II), trisacetylacetonate cobalt (III), triethylamine, tributylamine, diazabicyclo [ And tertiary amines such as 2,2,2] octane, phenolic compounds such as phenol, bisphenol A, and nonylphenol, organic acids such as acetic acid, benzoic acid, salicylic acid, and paratoluenesulfonic acid, and mixtures thereof.
- the curing accelerator one kind including these derivatives can be used alone, or two or more kinds including these derivatives can be used in combination.
- imidazole compounds are particularly preferable. Thereby, moisture absorption solder heat resistance can be improved. And although the said imidazole compound is not specifically limited, It is desirable to have compatibility with the said cyanate resin, an epoxy resin, and a film forming resin component.
- epoxy resin and film-forming resin component means that the imidazole compound is mixed with the cyanate resin, epoxy resin and film-forming resin component, or the imidazole compound is mixed with the cyanate resin.
- an epoxy resin, a film-forming resin component and an organic solvent it indicates a property that can be dissolved or dispersed to a state substantially close to the molecular level.
- Examples of the imidazole compound used in the resin composition of the interlayer insulating layer 6 include 1-benzyl-2-methylimidazole, 1-benzyl-2-phenylimidazole, 2-phenyl-4-methylimidazole, 2-ethyl- 4-methylimidazole, 2,4-diamino-6- [2'-methylimidazolyl- (1 ')]-ethyl-s-triazine, 2,4-diamino-6- (2'-undecylimidazolyl) -ethyl -S-triazine, 2,4-diamino-6- [2'-ethyl-4-methylimidazolyl- (1 ')]-ethyl-s-triazine, 2-phenyl-4,5-dihydroxymethylimidazole, 2- And phenyl-4-methyl-5-hydroxymethylimidazole.
- an imidazole compound selected from 1-benzyl-2-methylimidazole, 1-benzyl-2-phenylimidazole, and 2-ethyl-4-methylimidazole is preferable.
- These imidazole compounds have particularly excellent compatibility, so that a highly uniform cured product can be obtained and a fine and uniform roughened surface can be formed, so that a fine conductor circuit can be easily formed.
- the multilayer circuit board 1 can exhibit high heat resistance.
- a resin composition using such an imidazole compound can be cured with high uniformity from a minute matrix unit with a resin component. Thereby, the insulation of the interlayer insulation layer 6 formed in the multilayer circuit board 1 and heat resistance can be improved.
- the content of the imidazole compound is not particularly limited, but is preferably 0.01 to 5% by weight, particularly preferably 0.05 to 3% by weight, based on the total of the cyanate resin and the epoxy resin. Thereby, especially heat resistance can be improved.
- the resin composition preferably contains an inorganic filler.
- an inorganic filler preferably contains an inorganic filler.
- the elastic modulus can be improved by a combination of the cyanate resin and / or a prepolymer thereof (particularly a novolac-type cyanate resin) and an inorganic filler.
- examples of the inorganic filler include silicates such as talc, fired clay, unfired clay, mica and glass, oxides such as titanium oxide, alumina, silica and fused silica, calcium carbonate, magnesium carbonate, hydrotalcite and the like.
- examples thereof include borates such as calcium oxide and sodium borate, nitrides such as aluminum nitride, boron nitride, silicon nitride, and carbon nitride, and titanates such as strontium titanate and barium titanate.
- the inorganic filler one of these can be used alone, or two or more can be used in combination.
- silica is particularly preferable, and fused silica (particularly spherical fused silica) is preferable in terms of excellent low linear expansion.
- the shape is crushed and spherical, but in order to reduce the melt viscosity of the resin composition in order to ensure the impregnation of the fiber substrate, a method of use that suits the purpose, such as using spherical silica, is adopted. .
- the average particle diameter of the inorganic filler is not particularly limited, but is preferably 0.01 to 5 ⁇ m. More preferably, it is 0.1 to 2 ⁇ m.
- the average particle size of the inorganic filler is less than the lower limit, when the resin varnish is prepared using the resin composition of the present invention, the viscosity of the resin varnish is increased. 6 may be affected in workability. On the other hand, if the upper limit is exceeded, phenomena such as sedimentation of the inorganic filler may occur in the resin varnish.
- the inorganic filler is not particularly limited, and an inorganic filler having a monodispersed average particle diameter can be used, and an inorganic filler having a polydispersed average particle diameter can be used. Furthermore, one type or two or more types of inorganic fillers having an average particle size of monodisperse and / or polydisperse may be used in combination.
- the content of the inorganic filler is not particularly limited, but is preferably 20 to 70% by weight based on the entire resin composition. More preferably, it is 30 to 60% by weight. If the content of the inorganic filler is less than the lower limit, the effect of imparting low thermal expansion and low water absorption may be reduced. Moreover, when the said upper limit is exceeded, the moldability of the interlayer insulation layer 6 may fall by the fall of the fluidity
- the resin composition is not particularly limited, but it is preferable to use a coupling agent.
- the coupling agent can improve heat resistance, in particular, moisture absorption solder heat resistance, by improving the wettability of the interface between the thermosetting resin and the inorganic filler.
- Any coupling agent can be used as long as it is usually used.
- an epoxy silane coupling agent, a cationic silane coupling agent, an amino silane coupling agent, a titanate coupling agent, and a silicone oil type coupling It is preferable to use one or more coupling agents selected from among the agents. Thereby, the wettability with the interface of an inorganic filler can be made high, and thereby heat resistance can be improved more.
- the content of the coupling agent is not particularly limited, but is preferably 0.05 to 3 parts by weight with respect to 100 parts by weight of the inorganic filler.
- the content of the coupling agent is less than the lower limit, the effect of improving the heat resistance by covering the inorganic filler may not be sufficient.
- the above upper limit is exceeded, the bending strength of the interlayer insulating layer 6 may decrease.
- a phenoxy resin a polyimide resin, a polyamideimide resin, a polyphenylene oxide resin, a polyethersulfone resin, a polyester resin, a polyethylene resin, a polystyrene resin such as a polystyrene resin, a polystyrene-based thermoplastic elastomer (for example, a styrene-butadiene copolymer).
- thermoplastic elastomers such as polyolefin-based thermoplastic elastomers, polyamide-based elastomers, polyester-based elastomers, and diene-based elastomers such as polybutadiene, epoxy-modified polybutadiene, acrylic-modified polybutadiene, and methacryl-modified polybutadiene. You may use together.
- additives other than the above components such as pigments, dyes, antifoaming agents, leveling agents, ultraviolet absorbers, foaming agents, antioxidants, flame retardants, and ion scavengers are added to the resin composition as necessary. May be added.
- the method of forming the resin composition on the carrier substrate is not particularly limited.
- the resin varnish is prepared by dissolving and dispersing the resin composition in a solvent or the like, and using various coater devices.
- coating to a carrier base material, the method of drying this after spray-coating a resin varnish on a carrier base material using a spray apparatus, etc. are mentioned.
- the interlayer insulating layer 6 with a carrier base material having no void and having a uniform thickness of the interlayer insulating layer 6 can be efficiently manufactured.
- polyester resin such as a polyethylene terephthalate and a polybutylene terephthalate
- thermoplastic resin film with heat resistance such as a fluorine resin, a polyimide resin, or copper and / or a copper alloy
- a metal foil or the like can be used.
- the thickness of the carrier base material is not particularly limited, but a thickness of 10 to 100 ⁇ m is preferable because it is easy to handle when producing the interlayer insulating layer 6 with a carrier base material.
- the solvent used in the resin varnish desirably exhibits good solubility in the resin component in the resin composition, but a poor solvent may be used as long as it does not have an adverse effect.
- the solvent exhibiting good solubility include acetone, methyl ethyl ketone, methyl isobutyl ketone, cyclohexanone, tetrahydrofuran, dimethylformamide, dimethylacetamide, dimethyl sulfoxide, ethylene glycol, cellosolve and carbitol.
- the solid content in the resin varnish is not particularly limited, but is preferably 30 to 80% by weight, particularly preferably 40 to 70% by weight.
- the interlayer insulating layer 6 formed from such a resin composition is subjected to a roughening treatment on the surface using an oxidizing agent such as permanganate or dichromate, for example. Many minute uneven shapes with high uniformity can be formed on the surface of the insulating layer 6.
- the smoothness of the roughening treatment surface is high, so that a fine conductor circuit can be accurately formed. Further, the anchor effect can be enhanced by the minute uneven shape, and high adhesion can be imparted between the interlayer insulating layer 6 and the plated metal.
- the interlayer insulating layers 6 having different elastic moduli are respectively prepared and laminated when the interlayer insulating layer 6 of the multilayer circuit board 1 is manufactured.
- a method in which an interlayer insulating layer 6 having different elastic moduli is first laminated to form one interlayer insulating layer 6 is used when the multilayer circuit board 1 is manufactured. It is not particularly limited.
- the laminated structure of the interlayer insulating layer 6 is preferably two or more layers, particularly preferably a three-layer structure.
- the first insulating layer, the second insulating layer, and the first insulating layer are stacked in this order, and the first insulating layer, the second insulating layer, and the first insulating layer are of different types. Examples include a configuration in which different first insulating layers are stacked in this order.
- the inner layer wiring board 10 is produced by forming a conductor layer having a desired pattern by performing copper plating or the like on the surface including the inner surface of the through hole 7.
- the inner wiring board 10 itself may be a multilayer wiring board having an insulating layer and a conductor circuit layer.
- FIG. 1 shows a multilayer circuit board 1 having a structure in which three conductor circuit layers 11 and three interlayer insulation layers 6 are laminated on both sides of an inner layer wiring board 10, respectively.
- At least one interlayer insulating layer 6 includes a first insulating layer and a second insulating layer, and the elastic modulus of the first insulating layer is the elasticity of the second insulating layer. It is lower than the rate. Therefore, the first insulating layer serves as a buffer material, and warpage of the entire multilayer circuit board 1 can be suppressed.
- the first insulating layer has a lower elastic modulus than the second insulating layer, so that the first insulating layer Since the layer serves as a cushioning material against warping in any direction, warping of the entire multilayer circuit board 1 can be suppressed. Therefore, the multilayer circuit board 1 can be used regardless of the type of semiconductor chip.
- FIG. 2 shows details of the three interlayer insulating layers 6. That is, on one surface (the semiconductor chip 2 mounting surface side) of the inner wiring board 10, the first conductor circuit layer 11 and the interlayer insulating layer 6a, the second conductor circuit layer 11 and the interlayer insulating layer 6b, The third conductor circuit layer 11 and the interlayer insulating layer 6c are laminated.
- the elastic modulus of the interlayer insulating layer 6a, the interlayer insulating layer 6b, and the interlayer insulating layer 6c may be different from each other.
- a laminated structure in which the interlayer insulating layer 6a and the interlayer insulating layer 6c have the same elastic modulus and the interlayer insulating layer 6b has a different elastic modulus may be used, and the interlayer insulating layer 6a and the interlayer insulating layer 6b have the same elastic modulus
- the interlayer insulating layer 6c may have a laminated structure having different elastic moduli, and in this case, the elastic modulus of the entire interlayer insulating layer 6 may be equal to each other in any laminated structure.
- the interlayer insulating layers 6 are formed in a line-symmetric relationship with the core layer 5 interposed therebetween.
- the elastic moduli of the interlayer insulating layers 6 located symmetrically with respect to the core layer 5 are the same.
- the interlayer insulating layers 6 are stacked on the upper and lower sides of the core layer 5, and the stacked structures of the interlayer insulating layers 6 that are in line-symmetrical positions with the core layer 5 interposed therebetween are preferably the same. Thereby, the curvature of the multilayer circuit board 1 whole can further be suppressed.
- the number of layers of the conductor circuit layer 11 and the interlayer insulating layer 6 is not limited to this, and can be appropriately set according to the number of signal wirings, wiring patterns, and the like.
- the conductor circuit layer 11 and the interlayer insulating layer 6 may be formed only on one surface of the inner wiring board 10.
- the conductor circuit layer 11 and the interlayer insulating layer 6 are formed by heating the conductor circuit layer 11 and the interlayer insulating layer 6 on one side or both sides of the inner wiring board 10. Specifically, the conductor circuit layer 11 and the interlayer insulating layer 6 and the inner wiring board 10 are combined and vacuum-heated and pressure-molded using a vacuum-pressure laminator device or the like, and then heated and cured with a hot-air drying device or the like. Can be obtained.
- the conditions for heat and pressure molding are not particularly limited, but as an example, it can be carried out at a temperature of 60 to 160 ° C. and a pressure of 0.2 to 3 MPa.
- the conditions for heat curing are not particularly limited, but it can be carried out at a temperature of 140 to 240 ° C. for 30 to 120 minutes.
- the insulating resin of the interlayer insulating layer 6 can be obtained by superposing the inner layer wiring board 10 on the inner wiring board 10 and heating and pressing using a flat plate press device or the like.
- the conditions for heat and pressure molding are not particularly limited, but for example, it can be carried out at a temperature of 140 to 240 ° C. and a pressure of 1 to 4 MPa.
- the plurality of conductor circuit layers 11 are laminated in the order of the interlayer insulating layer 6 and the conductor circuit layer 11, and the conductor circuit layers 11 of each layer are electrically connected by the stacked vias 8, whereby the plurality of conductor circuit layers 11 and the interlayer insulation are formed.
- a multilayer wiring structure by the layer 6 is formed.
- an additive method such as a semi-additive method or a full additive method can be applied to the process of forming the plurality of conductor circuit layers 11 and the interlayer insulating layer 6.
- via holes are formed in the conductor circuit layer 11 and the interlayer insulating layer 6 by, for example, laser processing.
- electroless copper plating and electrolytic copper plating are sequentially performed on the surfaces of the conductor circuit layer 11 and the interlayer insulating layer 6 including the inside of the via hole, thereby forming the stacked via 8 and the conductor circuit layer 11.
- a heat treatment may be performed to improve the adhesion between the interlayer insulating layer 6 and copper.
- Such a process of forming the interlayer insulating layer 6 and the conductor circuit layer 11 (including the stacked via 8) is repeatedly performed a plurality of times according to the number of stacked layers.
- electrode pads connected to the internal wiring formed by the conductor circuit layer 11, the stacked via 8 and the through hole 7. 12 is formed on the semiconductor chip 2 mounting surface side of the multilayer circuit board 1 having the conductor circuit layer 11 and the interlayer insulating layer 6 described above.
- an external connection terminal 9 connected to the internal wiring is formed on the surface of the multilayer circuit board 1 opposite to the surface on which the semiconductor chip 2 is mounted.
- the electrode pad 12 and the external connection terminal 9 are electrically connected via an internal wiring by the conductor circuit layer 11, the stacked via 8, and the through hole 7.
- a metal terminal such as a solder bump or an Au bump is applied to the external connection terminal 9.
- the difference from the multilayer circuit board 1 is that a base board with peelable foil is used instead of the core layer 5, and an interlayer insulating layer 6 and a conductor circuit layer 11 are formed thereon.
- the required number of layers can be obtained by repeating this process.
- the method for forming the interlayer insulating layer 6 and the conductor circuit layer 11 can be the same method as that for the multilayer circuit board 1.
- the base board is removed by peeling off at the peelable copper foil.
- the peelable copper foil remaining on the multilayer circuit board 1 side is removed by etching, the coreless multilayer circuit board 1 can be obtained.
- Interlayer connection, surface treatment, and terminal formation of the coreless multilayer circuit board 1 can be formed by the same method as the multilayer circuit board 1.
- the sealing resin composition 4 is inject
- the sealing step the semiconductor package before filling the sealing resin composition 4 in which the multilayer circuit board 1 and the semiconductor chip 2 are flip-chip bonded by the metal bumps 3 and the sealing resin composition 4 are heated.
- the sealing resin composition 4 is applied to the side edge portion of the semiconductor chip 2 and spreads to the gap by capillary action.
- the semiconductor package is inclined or a pressure difference is used. A method of accelerating the injection may be used in combination.
- the temperature profile of the curing may be changed.
- the heating and curing may be performed while changing the temperature stepwise such that heating is performed at 100 ° C. for 1 hour followed by heating at 150 ° C. for 2 hours.
- the viscosity of the sealing resin composition 4 for forming the sealing resin composition 4 is desirably 50 Pa ⁇ sec or less (25 ° C.).
- the viscosity of the sealing resin composition 4 when the sealing resin composition 4 is injected is desirably 2 Pa ⁇ sec or less.
- the temperature at the time of injection is 60 to 140 ° C., more preferably 100 to 120 ° C.
- the material of the second insulating layer having a high elastic modulus 25 parts by weight of a novolak-type cyanate resin (Lonza Japan Co., Ltd., Primaset PT-30, weight average molecular weight of about 700), biphenyldimethylene type epoxy resin (Nippon Kayaku Co., Ltd.) NC-3000, epoxy equivalent 275, weight average molecular weight 2000) 24.7 parts by weight, a copolymer of phenoxy resin / biphenyl epoxy resin and bisphenol S epoxy resin, the terminal part having an epoxy group 10 parts by weight (manufactured by Japan Epoxy Resin Co., Ltd., YX-8100H30, weight average molecular weight 30000), 0.1 parts by weight of imidazole compound (manufactured by Shikoku Kasei Kogyo Co., Ltd., Curesol 1B2PZ (1-benzyl-2-phenylimidazole)) Dissolved and dispersed in methyl ethyl ket
- inorganic filler / spherical fused silica manufactured by Admatechs Co., Ltd., SO-25R, average particle size 0.5 ⁇ m
- coupling agent / epoxysilane coupling agent GE Toshiba Silicone Co., Ltd., A- 187
- Each resin varnish obtained above has a predetermined thickness of resin layer after drying on one side of a PET (polyethylene terephthalate) film having a thickness of 25 ⁇ m using a comma coater device. This was coated so as to have a thickness of 10 mm and dried for 10 minutes with a drying apparatus at 160 ° C. to produce an insulating layer.
- the produced insulating layers were defined as a first insulating layer (a) and a second insulating layer (b), respectively.
- This multi-layer circuit board for evaluation was a multi-layer circuit board having eight conductor circuits in which three layers of insulating layers and conductor circuit layers were laminated on both sides of a core material (Sumitomo Bakelite Co., Ltd. Sumitrite ELC-4785GS 0.20 mmt). .
- the inner layer wiring has a through hole in the core layer, three stages of stacked vias are arranged on both sides of the through hole, and the stacked vias formed on both sides of the electrode pads on the semiconductor chip mounting surface and the through holes are linearly connected.
- the size of the multilayer circuit board is 50 mm ⁇ 50 mm, the electrode pads are plated with Ni / Au, and the electrode pads to be flip-chip connected are pre-solder (tin 96.5% silver 3% Copper 0.5%).
- Multi-layer circuit boards A, B, C, D, and F were produced with the above-described configuration.
- the first insulating layer having a low elastic modulus and the second insulating layer having a high elastic modulus were used as an interlayer insulating layer.
- a first insulating layer having a low elastic modulus of 10 ⁇ m and a second insulating layer having a high elastic modulus of 20 ⁇ m are formed on a PET film.
- the first insulating layer (a) having a low elastic modulus, the second insulating layer (b) having a high elastic modulus, and the first insulating layer (a) having a low elastic modulus are separately manufactured and built during the build-up process between the circuit layers. The layers were laminated in this order.
- This interlayer insulating layer was defined as an interlayer insulating layer (1) (first interlayer insulating layer).
- a conductor circuit layer was produced on this interlayer insulation layer (1), and further, an interlayer insulation layer (1) and a conductor circuit layer were produced to obtain a multilayer circuit board having 8 conductor circuit layers.
- the total thickness of the multilayer circuit board was 0.69 mm.
- the multilayer circuit board B is composed of an interlayer insulation layer (2) (second interlayer insulation layer) having a thickness of 40 ⁇ m, consisting of only the interlayer insulation layer (1) fabricated on the multilayer circuit board A and the second insulation layer (b) having a high elastic modulus.
- an interlayer insulating layer (2) having a thickness of 40 ⁇ m is prepared on a PET film, and each of the upper and lower layers of the core layer is formed as an interlayer insulating layer (in the build-up process between circuit layers).
- Two layers above and below the interlayer insulating layer (1) were used as the interlayer insulating layer (2).
- the total thickness of the multilayer circuit board was 0.69 mm.
- the multilayer circuit board C uses the same interlayer insulating layer (1) and interlayer insulating layer (2) as the multilayer circuit board B, and the upper and lower layers of the core layer 5 are divided into an interlayer insulating layer (2) and an interlayer insulating layer (2 Each of the upper and lower layers of 1) was used as an interlayer insulating layer (1), and was produced in the same manner as the multilayer circuit board B.
- the total thickness of the multilayer circuit board was 0.69 mm.
- the multilayer circuit board D uses the same interlayer insulating layer (1) and interlayer insulating layer (2) as those of the multilayer circuit board B, and each of the upper and lower layers of the core layer 5 is divided into an interlayer insulating layer (2) and an interlayer insulating layer (2 Each of the upper and lower layers of 2) was used as an interlayer insulating layer (1), and was produced in the same manner as the multilayer circuit board B.
- the total thickness of the multilayer circuit board was 0.69 mm.
- the multilayer circuit board F was produced in the same manner as the multilayer circuit board A using only the interlayer insulating layer (2) having a thickness of 40 ⁇ m as the insulating layer.
- the total thickness of the multilayer circuit board was 0.69 mm.
- a multilayer circuit board without a core layer was produced by a semi-additive method. Specifically, a double-sided board with a total thickness of 0.8 mm (Sumitomo Bakelite Co., Ltd. Sumitrite ELC-4785GS) provided with peelable copper foil YSNAP (NIPPON ELECTRIC ELECTRIC CO., LTD.) Is used as a base board and insulated on one side by a build-up method.
- the interlayer insulating layer (1) was used as a layer.
- a conductor circuit layer was produced on the interlayer insulating layer (1), and this was repeated 6 times to obtain a multilayer structure.
- the base board was peeled and removed at the peelable copper foil, and the peelable copper layer remaining on the multilayer circuit board side was removed by etching to obtain a multilayer circuit board E.
- the total thickness of the multilayer circuit board was 0.4 mm.
- the multilayer circuit board G was produced in the same manner as the multilayer circuit board E except that the interlayer insulating layer (1) used in the multilayer circuit board E was changed to the interlayer insulating layer (2).
- Warpage Evaluation Using the laser three-dimensional shape measuring machine (Hitachi Technology & Service Co., Ltd. LS220-MT), the warpage of the multilayer circuit boards A to G and the semiconductor packages A to G produced above was measured at room temperature. The results are shown in Table 2 as 1 to 5 and Comparative Examples 1 and 2. The measurement range is 15 mm x 15 mm, the same as the semiconductor chip size, and the laser is applied to the BGA surface opposite to the semiconductor chip mounting surface. The distance from the laser head is the difference between the farthest point and the nearest point. Was the warp value.
- ⁇ Warpage of less than 60 ⁇ m
- ⁇ Warpage of 60 ⁇ m or more
- the warpage of the entire multilayer circuit board and the warpage of the semiconductor package are improved by changing the characteristics of the interlayer insulation layer of the multilayer circuit board by using a plurality of insulation layers having different elastic moduli as the interlayer insulation layer. I was able to. This makes it possible to improve the yield of semiconductor chip mounting and improve the reliability of the semiconductor package.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
半導体チップ実装前の多層回路基板において、一般的に導体回路層と絶縁樹脂層の線膨張係数が異なり、半導体チップ搭載側とその反対側では異なる導体回路を有している。導体回路が異なるということは、導体回路と絶縁樹脂間の拘束度合いが異なることになり、拘束の低いほうが導体回路と樹脂間の線膨張係数の差によって、より大きく変動することになる。その結果、裏表面での変動の差が生じ、回路基板全体の反りとなって現れると、半導体チップ実装歩留が非常に悪くなり、半導体パッケージ信頼性を下げる要因にもなる。
[1] 導体回路層と、層間絶縁層とが交互に積層した多層回路基板であって、
前記層間絶縁層が、第1絶縁層と、前記第1絶縁層よりも弾性率が高い第2絶縁層と、を含むことを特徴とする多層回路基板。
[2] [1]に記載された多層回路基板において、
前記層間絶縁層が複数であって、
前記層間絶縁層の弾性率が互いに等しいことを特徴とする多層回路基板。
[3] [2]に記載された多層回路基板において、
前記層間絶縁層の積層構成が同一であることを特徴とする多層回路基板。
[4] [3]に記載された多層回路基板において、
前記層間絶縁層が、第1絶縁層、第2絶縁層及び第1絶縁層の順に積層されてなることを特徴とする多層回路基板。
[5] [1]に記載された多層回路基板において、
前記層間絶縁層が複数であって、
前記層間絶縁層の積層構成が前記第1絶縁層、前記第2絶縁層及び前記第1絶縁層の順に積層されてなる第1層間絶縁層と、
前記層間絶縁層の積層構成が前記第2絶縁層からなる第2層間絶縁層と、を含むことを特徴とする多層回路基板。
[6] [1]乃至[5]いずれかに記載された多層回路基板において、
前記層間絶縁層が、シアネート樹脂を含む樹脂組成物で構成されてなることを特徴とする多層回路基板。
[7] [6]に記載された多層回路基板において、
前記シアネート樹脂が、ノボラック型シアネート樹脂であることを特徴とする多層回路基板。
[8] [1]乃至[6]いずれかに記載された多層回路基板において、
前記多層回路基板は、コア層をさらに含み、
前記層間絶縁層が前記コア層の上下に積層され、
前記コア層を挟んで線対称の位置にある前記層間絶縁層の積層構成が互いに同一であることを特徴とする多層回路基板。
[9] [1]乃至[7]いずれかに記載された多層回路基板において、
前記第1絶縁層の弾性率を(Ea)、前記第2絶縁層の弾性率を(Eb)としたとき、
(Eb/Ea)>3 であることを特徴とする多層回路基板。
[10] [1]乃至[7]いずれかに記載された多層回路基板において、
周波数10Hzでの動的粘弾性測定による前記第2絶縁層の弾性率を(Eb)としたとき、
(Eb)≧4GPa であることを特徴とする多層回路基板。
[11] [1]乃至[8]いずれかに記載された多層回路基板において、
周波数10Hzでの動的粘弾性測定による前記第1絶縁層の弾性率を(Ea)としたとき、
(Ea)≦2GPa であることを特徴とする多層回路基板。
[12] 導体回路層と、層間絶縁層とが交互に積層した多層回路基板に用いられる前記層間絶縁層を構成する絶縁シートであって、前記層間絶縁層が、第1絶縁層と、前記第1絶縁層よりも弾性率が高い第2絶縁層と、を含むことを特徴とする絶縁シート。
[13] [12]に記載された絶縁シートにおいて、
前記層間絶縁層が、前記第1絶縁層、前記第2絶縁層及び前記第1絶縁層の順に積層されてなることを特徴とする絶縁シート。
[14] [12]または[13]に記載された絶縁シートにおいて、
前記層間絶縁層が、シアネート樹脂を含む樹脂組成物で構成されてなることを特徴とする絶縁シート。
[15] [14]に記載された絶縁シートにおいて、
前記シアネート樹脂が、ノボラック型シアネート樹脂であることを特徴とする絶縁シート。
[16] [12]乃至[14]いずれかに記載された絶縁シートにおいて、
前記第1絶縁層の弾性率を(Ea)、前記第2絶縁層の弾性率を(Eb)としたとき、
(Eb/Ea)>3 であることを特徴とする絶縁シート。
[17] [12]乃至[16]いずれかに記載された絶縁シートにおいて、
周波数10Hzでの動的粘弾性測定による前記第2絶縁層の弾性率を(Eb)としたとき、
(Eb)≧4GPa であることを特徴とする絶縁シート。
[18] [12]乃至[17]いずれかに記載された絶縁シートにおいて、
周波数10Hzでの動的粘弾性測定による前記第1絶縁層の弾性率を(Ea)としたとき、
(Ea)≦2GPa であることを特徴とする絶縁シート。
[19] [1]乃至[11]いずれかに記載された多層回路基板を用いたことを特徴とする半導体パッケージ。
図1において、多層回路基板1は、導体回路層11と、層間絶縁層6を交互に有する多層回路基板1であって、コア層5に、層間絶縁層6と導体回路層11をビルドアップして作製した多層回路基板1である。絶縁層と導体回路層を有するコア層5にスルーホール7を有し、そのコア層5の上下に層間絶縁層6と導体回路層11をビルドアップして、導電部であるビアを有する多層回路基板1である。
多層回路基板1において、コア層5の絶縁層に用いられる材料は、適切な強度を有していればよく、特に限定するものではないが、例えば、エポキシ樹脂、フェノール樹脂、シアネート樹脂、トリアジン樹脂、ビスマレイミド樹脂、ポリイミド樹脂、ポリアミドイミド樹脂、ベンゾシクロブテン樹脂のうち、少なくとも一種または複数種の樹脂組成物を繊維基材(例えばガラス繊維シートなど)に含浸させて半硬化させてなる板状の材料(いわゆるプリプレグ)を好適に用いることができる。特にシアネート樹脂とフェノール樹脂とエポキシ樹脂と無機充填材とを含む樹脂組成物を繊維基材(例えばガラス繊維シートなど)に含浸させて半硬化させてなる板状の材料(いわゆるプリプレグ)を好適に用いることができる。
多層回路基板1において、層間絶縁層6の第1絶縁層および第2絶縁層に用いられる材料は、前述した第1絶縁層及び第2絶縁層の硬化物のガラス転移温度、弾性率および線膨張係数の条件を満たし、適切な強度を有していればよく、特に限定するものではないが、熱硬化性樹脂を含む樹脂組成物で構成されていることが好ましい。これにより、層間絶縁層6の耐熱性を向上することができる。また、層間絶縁層6の第2絶縁層に用いる樹脂組成物は、ガラス繊維シートをはじめとする繊維基材に含浸させてもよく、樹脂組成物をそのまま硬化させてもよい。ここで、樹脂組成物を繊維基材に含浸させる方法としては特に限定されない。また、キャリア基材付き層間絶縁層6は、上記樹脂組成物で構成される層間絶縁層6をキャリア基材に形成してなるものである。
またこれらの中でも、特にシアネート樹脂(シアネート樹脂のプレポリマーを含む)が好ましい。これにより、層間絶縁層6の線膨張係数を小さくすることができる。さらに、層間絶縁層6の電気特性(低誘電率、低誘電正接)、機械強度などにも優れる。
上記エポキシ樹脂の重量平均分子量は、例えばGPCで測定することができる。
前述のコア層5に用いる材料にスルーホール7を形成した後、スルーホール7内面を含む表面に銅めっきなどを施して、所望パターンの導体層を形成することによって、内層配線板10が作製される。なお、内層配線板10自体が絶縁層と導体回路層を有する多層配線板であってもよい。
次に、図1におけるフリップチップ半導体パッケージについて説明する。
本発明の一実施形態では、多層回路基板1の半導体チップ2接続用電極面と半導体チップ2の電極面を金属バンプ3によりフリップチップ接合する接合工程と、上記多層回路基板1と上記半導体チップ2との間に封止樹脂組成物4を注入してアンダーフィル部を形成する封止工程を具備する。
封止樹脂組成物4を形成するための封止樹脂組成物4の粘度は、50Pa・sec以下(25℃)とするのが望ましい。また、封止樹脂組成物4を注入する時の封止樹脂組成物4の粘度は、2Pa・sec以下とするのが望ましい。注入時の温度は、60~140℃で、より好ましくは100~120℃である。
1.絶縁層に用いる材料の硬化物の物性試験
絶縁層に用いる材料として以下の材料を用いた。
弾性率の低い第1絶縁層の材料については、ビフェニルジメチレン型エポキシ樹脂(日本化薬株式会社製、NC-3000、エポキシ当量275、重量平均分子量2000)49.7重量部、フェノキシ樹脂/ビフェニルエポキシ樹脂とビスフェノールSエポキシ樹脂との共重合体であり、末端部はエポキシ基を有している(ジャパンエポキシレジン株式会社製、YX-8100H30、重量平均分子量30000)10重量部、イミダゾール化合物(四国化成工業株式会社製、キュアゾール1B2PZ(1-ベンジル-2-フェニルイミダゾール))0.1重量部をメチルエチルケトンに溶解、分散させた。さらに、無機充填材/球状溶融シリカ(株式会社アドマテックス製、SO-25R、平均粒子径0.5μm)40重量部とカップリング剤/エポキシシランカップリング剤(GE東芝シリコーン株式会社製、A-187)0.2重量部を添加して、高速攪拌装置を用いて10分間攪拌して、固形分50重量%の樹脂ワニス(a)を調製した。
弾性率の高い第2絶縁層の材料についてノボラック型シアネート樹脂(ロンザジャパン株式会社製、プリマセットPT-30、重量平均分子量約700)25重量部、ビフェニルジメチレン型エポキシ樹脂(日本化薬株式会社製、NC-3000、エポキシ当量275、重量平均分子量2000)24.7重量部、フェノキシ樹脂/ビフェニルエポキシ樹脂とビスフェノールSエポキシ樹脂との共重合体であり、末端部はエポキシ基を有している(ジャパンエポキシレジン株式会社製、YX-8100H30、重量平均分子量30000)10重量部、イミダゾール化合物(四国化成工業株式会社製、キュアゾール1B2PZ(1-ベンジル-2-フェニルイミダゾール))0.1重量部をメチルエチルケトンに溶解、分散させた。さらに、無機充填材/球状溶融シリカ(株式会社アドマテックス製、SO-25R、平均粒子径0.5μm)40重量部とカップリング剤/エポキシシランカップリング剤(GE東芝シリコーン株式会社製、A-187)0.2重量部を添加して、高速攪拌装置を用いて10分間攪拌して、固形分50重量%の樹脂ワニス(b)を調製した。
上記で得られた各樹脂ワニスを、厚さ25μmのPET(ポリエチレンテレフタレート)フィルムの片面に、コンマコーター装置を用いて乾燥後の樹脂層の厚さが所定の厚さとなるように塗工し、これを160℃の乾燥装置で10分間乾燥して、絶縁層を作製した。作製した絶縁層をそれぞれ第1絶縁層(a)、第2絶縁層(b)とした。
上記で得られた第1絶縁層(a)、第2絶縁層(b)を用いて、常圧ラミネーターで80μm厚の絶縁層を作製し、200℃、2時間で硬化した。この樹脂硬化物から試験片5mm×30mmの評価用試料を採取した。動的粘弾性測定装置(DMA)(セイコーインスツルメント社製 DMS6100)を用いて、5℃/分で昇温しながら、周波数10Hzの歪みを与えて動的粘弾性の測定を行い、tanδのピーク値からガラス転移温度(Tg)を判定し、また測定より25℃での弾性率を求めた。
上記で得られた樹脂硬化物から4mm×20mmの評価用試料を採取した。
TMA装置(TMA)(TAインスツルメント社製)を用いて、10℃/分で昇温して測定しガラス転移温度以下における線膨張係数を算出した。
上記、絶縁層を用いて評価用多層回路基板をセミアディティブ法により作製した。この評価用多層回路基板は、コア材(住友ベークライト株式会社スミライトELC-4785GS 0.20mmt)の両側にそれぞれ3層の絶縁層および導体回路層が積層された導体回路8層の多層回路基板とした。内層配線はコア層にスルーホールを有し、そのスルーホールの両側に3段のスタックドビアを配し、半導体チップ搭載面の電極パッドとスルーホールの両側に形成されたスタックドビアが直線的に接続された内層配線構造を有し、多層回路基板のサイズは50mm×50mm、前記電極パッドにはNi/Auメッキが施され、フリップチップ接続される電極パッドにはさらにプレソルダ(錫96.5%銀3%銅0.5%)を施した。
前記構成にて、多層回路基板A、B、C、D、およびFを作製した。
上記作製した多層回路基板A~Gを用いて、フリップチップ実装による半導体パッケージA~Gを作製した。半導体チップサイズ15mm×15mm、半導体チップ厚さ725μm、バンプサイズ100μm、バンプピッチ200μmの半導体チップをフリップチップ搭載し、アンダーフィル材として住友ベークライト株式会社スミレジンエクセルCRP-4160を用いた。
レーザー3次元形状測定機(株式会社日立テクノロジーアンドサービス LS220-MT)を用いて、上記作製した多層回路基板A~Gおよび半導体パッケージA~Gについて、常温における反りの測定を行い、実施例1~5、比較例1~2として表2に、その結果を示した。測定範囲は半導体チップサイズと同じ15mm×15mmの範囲で、半導体チップ搭載面とは反対側のBGA面にレーザーを当てて測定を行い、レーザーヘッドからの距離が、最遠点と最近点の差を反り値とした。
Claims (19)
- 導体回路層と、層間絶縁層とが交互に積層した多層回路基板であって、
前記層間絶縁層が、第1絶縁層と、前記第1絶縁層よりも弾性率が高い第2絶縁層と、を含むことを特徴とする多層回路基板。 - 請求項1に記載された多層回路基板において、
前記層間絶縁層が複数であって、
前記層間絶縁層の弾性率が互いに等しいことを特徴とする多層回路基板。 - 請求項2に記載された多層回路基板において、
前記層間絶縁層の積層構成が同一であることを特徴とする多層回路基板。 - 請求項3に記載された多層回路基板において、
前記層間絶縁層が、第1絶縁層、第2絶縁層及び第1絶縁層の順に積層されてなることを特徴とする多層回路基板。 - 請求項1に記載された多層回路基板において、
前記層間絶縁層が複数であって、
前記層間絶縁層の積層構成が前記第1絶縁層、前記第2絶縁層及び前記第1絶縁層の順に積層されてなる第1層間絶縁層と、
前記層間絶縁層の積層構成が前記第2絶縁層からなる第2層間絶縁層と、を含むことを特徴とする多層回路基板。 - 請求項1乃至5いずれかに記載された多層回路基板において、
前記層間絶縁層が、シアネート樹脂を含む樹脂組成物で構成されてなることを特徴とする多層回路基板。 - 請求項6に記載された多層回路基板において、
前記シアネート樹脂が、ノボラック型シアネート樹脂であることを特徴とする多層回路基板。 - 請求項1乃至6いずれかに記載された多層回路基板において、
前記多層回路基板は、コア層をさらに含み、
前記層間絶縁層が前記コア層の上下に積層され、
前記コア層を挟んで線対称の位置にある前記層間絶縁層の積層構成が互いに同一であることを特徴とする多層回路基板。 - 請求項1乃至7いずれかに記載された多層回路基板において、
前記第1絶縁層の弾性率を(Ea)、前記第2絶縁層の弾性率を(Eb)としたとき、
(Eb/Ea)>3 であることを特徴とする多層回路基板。 - 請求項1乃至7いずれかに記載された多層回路基板において、
周波数10Hzでの動的粘弾性測定による前記第2絶縁層の弾性率を(Eb)としたとき、
(Eb)≧4GPa であることを特徴とする多層回路基板。 - 請求項1乃至8いずれかに記載された多層回路基板において、
周波数10Hzでの動的粘弾性測定による前記第1絶縁層の弾性率を(Ea)としたとき、
(Ea)≦2GPa であることを特徴とする多層回路基板。 - 導体回路層と、層間絶縁層とが交互に積層した多層回路基板に用いられる前記層間絶縁層を構成する絶縁シートであって、前記層間絶縁層が、第1絶縁層と、前記第1絶縁層よりも弾性率が高い第2絶縁層と、を含むことを特徴とする絶縁シート。
- 請求項12に記載された絶縁シートにおいて、
前記層間絶縁層が、前記第1絶縁層、前記第2絶縁層及び前記第1絶縁層の順に積層されてなることを特徴とする絶縁シート。 - 請求項12または13に記載された絶縁シートにおいて、
前記層間絶縁層が、シアネート樹脂を含む樹脂組成物で構成されてなることを特徴とする絶縁シート。 - 請求項14に記載された絶縁シートにおいて、
前記シアネート樹脂が、ノボラック型シアネート樹脂であることを特徴とする絶縁シート。 - 請求項12乃至14いずれかに記載された絶縁シートにおいて、
前記第1絶縁層の弾性率を(Ea)、前記第2絶縁層の弾性率を(Eb)としたとき、
(Eb/Ea)>3 であることを特徴とする絶縁シート。 - 請求項12乃至16いずれかに記載された絶縁シートにおいて、
周波数10Hzでの動的粘弾性測定による前記第2絶縁層の弾性率を(Eb)としたとき、
(Eb)≧4GPa であることを特徴とする絶縁シート。 - 請求項12乃至17いずれかに記載された絶縁シートにおいて、
周波数10Hzでの動的粘弾性測定による前記第1絶縁層の弾性率を(Ea)としたとき、
(Ea)≦2GPa であることを特徴とする絶縁シート。 - 請求項1乃至11いずれかに記載された多層回路基板を用いたことを特徴とする半導体パッケージ。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/922,688 US8604352B2 (en) | 2008-03-31 | 2009-03-25 | Multilayer circuit board, insulating sheet, and semiconductor package using multilayer circuit board |
CN200980112176.3A CN101983425B (zh) | 2008-03-31 | 2009-03-25 | 多层电路板、绝缘片和使用多层电路板的半导体封装件 |
JP2010505349A JP5771987B2 (ja) | 2008-03-31 | 2009-03-25 | 多層回路基板、絶縁シート、および多層回路基板を用いた半導体パッケージ |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008092028 | 2008-03-31 | ||
JP2008-092028 | 2008-03-31 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2009122680A1 true WO2009122680A1 (ja) | 2009-10-08 |
Family
ID=41135088
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2009/001331 WO2009122680A1 (ja) | 2008-03-31 | 2009-03-25 | 多層回路基板、絶縁シート、および多層回路基板を用いた半導体パッケージ |
Country Status (7)
Country | Link |
---|---|
US (1) | US8604352B2 (ja) |
JP (1) | JP5771987B2 (ja) |
KR (1) | KR20100134017A (ja) |
CN (1) | CN101983425B (ja) |
MY (1) | MY152730A (ja) |
TW (1) | TWI477220B (ja) |
WO (1) | WO2009122680A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012018952A (ja) * | 2010-07-06 | 2012-01-26 | Furukawa Electric Co Ltd:The | プリント配線基板、半導体装置、プリント配線基板の製造方法及び半導体装置の製造方法 |
Families Citing this family (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI401776B (zh) * | 2009-12-31 | 2013-07-11 | Chipmos Technologies Inc | 四邊扁平無接腳封裝(qfn)結構 |
KR101767381B1 (ko) * | 2010-12-30 | 2017-08-11 | 삼성전자 주식회사 | 인쇄회로기판 및 이를 포함하는 반도체 패키지 |
JP5617028B2 (ja) * | 2011-02-21 | 2014-10-29 | パナソニック株式会社 | 金属張積層板、及びプリント配線板 |
JP2012195568A (ja) * | 2011-02-28 | 2012-10-11 | Koa Corp | 金属ベース回路基板 |
US20120286416A1 (en) * | 2011-05-11 | 2012-11-15 | Tessera Research Llc | Semiconductor chip package assembly and method for making same |
JP5849478B2 (ja) * | 2011-07-11 | 2016-01-27 | 富士通セミコンダクター株式会社 | 半導体装置および試験方法 |
US9117730B2 (en) * | 2011-12-29 | 2015-08-25 | Ibiden Co., Ltd. | Printed wiring board and method for manufacturing printed wiring board |
US20130215586A1 (en) * | 2012-02-16 | 2013-08-22 | Ibiden Co., Ltd. | Wiring substrate |
EP2866535B1 (en) * | 2012-06-22 | 2019-09-04 | Nikon Corporation | Substrate, imaging unit and imaging device |
KR101549735B1 (ko) * | 2013-03-26 | 2015-09-02 | 제일모직주식회사 | 유기발광소자 충전제용 열경화형 조성물 및 이를 포함하는 유기발광소자 디스플레이 장치 |
JP2014216552A (ja) * | 2013-04-26 | 2014-11-17 | 富士通株式会社 | 積層構造体及びその製造方法 |
EP2977406B1 (en) * | 2013-09-24 | 2024-01-24 | LG Chem, Ltd. | Curable composition |
TWI506077B (zh) | 2013-12-31 | 2015-11-01 | Taiwan Union Technology Corp | 樹脂組合物及其應用 |
TW201539596A (zh) * | 2014-04-09 | 2015-10-16 | Tong Hsing Electronic Ind Ltd | 中介體及其製造方法 |
TWI559829B (zh) * | 2014-10-22 | 2016-11-21 | 矽品精密工業股份有限公司 | 封裝結構及其製法 |
KR102493463B1 (ko) | 2016-01-18 | 2023-01-30 | 삼성전자 주식회사 | 인쇄회로기판, 이를 가지는 반도체 패키지, 및 인쇄회로기판의 제조 방법 |
TWI622139B (zh) * | 2016-03-08 | 2018-04-21 | 恆勁科技股份有限公司 | 封裝基板 |
KR20190012485A (ko) * | 2017-07-27 | 2019-02-11 | 삼성전기주식회사 | 인쇄회로기판 및 그 제조 방법 |
CN109803481B (zh) * | 2017-11-17 | 2021-07-06 | 英业达科技有限公司 | 多层印刷电路板及制作多层印刷电路板的方法 |
US10879144B2 (en) * | 2018-08-14 | 2020-12-29 | Texas Instruments Incorporated | Semiconductor package with multilayer mold |
US11264332B2 (en) | 2018-11-28 | 2022-03-01 | Micron Technology, Inc. | Interposers for microelectronic devices |
US11439022B2 (en) * | 2019-09-02 | 2022-09-06 | Samsung Electro-Mechanics Co., Ltd. | Printed circuit board |
US20210392758A1 (en) * | 2019-10-31 | 2021-12-16 | Avary Holding (Shenzhen) Co., Limited. | Thin circuit board and method of manufacturing the same |
CN113130408A (zh) | 2019-12-31 | 2021-07-16 | 奥特斯奥地利科技与系统技术有限公司 | 部件承载件及制造部件承载件的方法 |
GB202018676D0 (en) * | 2020-11-27 | 2021-01-13 | Graphcore Ltd | Controlling warpage of a substrate for mounting a semiconductor die |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004281999A (ja) * | 2003-01-23 | 2004-10-07 | Kyocera Corp | 多層配線基板 |
JP2005286089A (ja) * | 2004-03-30 | 2005-10-13 | Sumitomo Bakelite Co Ltd | 多層プリント配線板の製造方法 |
JP2007149870A (ja) * | 2005-11-25 | 2007-06-14 | Denso Corp | 回路基板及び回路基板の製造方法。 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3199584B2 (ja) * | 1994-10-31 | 2001-08-20 | 京セラ株式会社 | 多層配線基板 |
JPH11233571A (ja) | 1998-02-12 | 1999-08-27 | Hitachi Ltd | 半導体装置及びアンダーフィル材並びに熱硬化性フィルム材 |
JP2001036253A (ja) * | 1999-07-26 | 2001-02-09 | Shinko Electric Ind Co Ltd | 多層配線回路基板及びその製造方法 |
US6423905B1 (en) * | 2000-05-01 | 2002-07-23 | International Business Machines Corporation | Printed wiring board with improved plated through hole fatigue life |
JP5085125B2 (ja) * | 2004-03-29 | 2012-11-28 | 住友ベークライト株式会社 | 樹脂組成物、樹脂付き金属箔、基材付き絶縁シートおよび多層プリント配線板 |
JP4449608B2 (ja) | 2004-07-09 | 2010-04-14 | 凸版印刷株式会社 | 半導体装置 |
US20090056995A1 (en) * | 2005-04-20 | 2009-03-05 | Toyo Boseki Kabushiki Kasiha | Adhesive sheet, metal-laminated sheet and printed wiring board |
JP4244975B2 (ja) | 2005-08-26 | 2009-03-25 | パナソニック電工株式会社 | プリプレグ用エポキシ樹脂組成物、プリプレグ、多層プリント配線板 |
JP4072176B2 (ja) * | 2005-08-29 | 2008-04-09 | 新光電気工業株式会社 | 多層配線基板の製造方法 |
JP4817835B2 (ja) * | 2005-12-21 | 2011-11-16 | 京セラ株式会社 | 配線基板 |
JP4924871B2 (ja) * | 2006-05-08 | 2012-04-25 | 日立化成工業株式会社 | 複合基板および配線板 |
JP2008028302A (ja) * | 2006-07-25 | 2008-02-07 | Sumitomo Bakelite Co Ltd | 多層回路基板及び該多層回路基板を用いた半導体装置 |
JP2008037881A (ja) | 2006-08-01 | 2008-02-21 | Hitachi Chem Co Ltd | プリプレグ、プリプレグを用いた金属箔張り積層板及び多層プリント配線板 |
-
2009
- 2009-03-25 US US12/922,688 patent/US8604352B2/en not_active Expired - Fee Related
- 2009-03-25 JP JP2010505349A patent/JP5771987B2/ja not_active Expired - Fee Related
- 2009-03-25 KR KR1020107022590A patent/KR20100134017A/ko not_active Application Discontinuation
- 2009-03-25 WO PCT/JP2009/001331 patent/WO2009122680A1/ja active Application Filing
- 2009-03-25 CN CN200980112176.3A patent/CN101983425B/zh not_active Expired - Fee Related
- 2009-03-25 MY MYPI20104229 patent/MY152730A/en unknown
- 2009-03-31 TW TW098110595A patent/TWI477220B/zh not_active IP Right Cessation
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004281999A (ja) * | 2003-01-23 | 2004-10-07 | Kyocera Corp | 多層配線基板 |
JP2005286089A (ja) * | 2004-03-30 | 2005-10-13 | Sumitomo Bakelite Co Ltd | 多層プリント配線板の製造方法 |
JP2007149870A (ja) * | 2005-11-25 | 2007-06-14 | Denso Corp | 回路基板及び回路基板の製造方法。 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012018952A (ja) * | 2010-07-06 | 2012-01-26 | Furukawa Electric Co Ltd:The | プリント配線基板、半導体装置、プリント配線基板の製造方法及び半導体装置の製造方法 |
Also Published As
Publication number | Publication date |
---|---|
TWI477220B (zh) | 2015-03-11 |
MY152730A (en) | 2014-11-28 |
JP5771987B2 (ja) | 2015-09-02 |
KR20100134017A (ko) | 2010-12-22 |
TW200950632A (en) | 2009-12-01 |
JPWO2009122680A1 (ja) | 2011-07-28 |
CN101983425B (zh) | 2012-11-21 |
US20110024172A1 (en) | 2011-02-03 |
CN101983425A (zh) | 2011-03-02 |
US8604352B2 (en) | 2013-12-10 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5771987B2 (ja) | 多層回路基板、絶縁シート、および多層回路基板を用いた半導体パッケージ | |
JP5660272B2 (ja) | フリップチップ半導体パッケージ用の接続構造、ビルドアップ層材料、封止樹脂組成物および回路基板 | |
JP4888147B2 (ja) | 樹脂組成物、フィルム付きまたは金属箔付き絶縁樹脂シート、多層プリント配線板、多層プリント配線板の製造方法および半導体装置 | |
JP4802246B2 (ja) | 半導体装置 | |
KR101464008B1 (ko) | 반도체 패키지, 코어층 재료, 빌드업층 재료 및 시일링 수지 조성물 | |
JP5344022B2 (ja) | エポキシ樹脂組成物、プリプレグ、積層板、樹脂シート、プリント配線板及び半導体装置 | |
JP5533657B2 (ja) | 積層板、回路板および半導体装置 | |
JP5200405B2 (ja) | 多層配線板及び半導体パッケージ | |
JPWO2008087972A1 (ja) | 絶縁樹脂シート積層体、該絶縁樹脂シート積層体を積層してなる多層プリント配線板 | |
JP6186977B2 (ja) | 樹脂組成物、樹脂シート、プリプレグ、積層板、プリント配線板、及び半導体装置 | |
WO2008099940A9 (ja) | 回路基板の製造方法、半導体製造装置、回路基板及び半導体装置 | |
WO2007108087A1 (ja) | 絶縁樹脂層、キャリア付き絶縁樹脂層および多層プリント配線板 | |
JP5056787B2 (ja) | 積層板、多層プリント配線板および半導体装置 | |
JP5256681B2 (ja) | 半導体装置、半導体装置用プリント配線板及び銅張積層板 | |
JP2011135034A (ja) | 半導体パッケージおよび半導体装置 | |
JP5672694B2 (ja) | 樹脂シート、プリント配線板、および半導体装置 | |
JP2009067852A (ja) | ガラス繊維織布入り絶縁樹脂シート、積層板、多層プリント配線板、及び半導体装置 | |
JP2009070891A (ja) | 半導体装置 | |
JP2010080609A (ja) | 半導体装置 | |
JP5188075B2 (ja) | 回路基板の製造方法及び半導体製造装置 | |
JP5211624B2 (ja) | 半導体装置の製造方法および半導体装置用プリント配線板の製造方法 | |
JP2008251891A (ja) | 回路基板及びその半導体装置 | |
KR20080104069A (ko) | 절연 수지층, 캐리어부착 절연 수지층 및 다층 프린트 배선판 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WWE | Wipo information: entry into national phase |
Ref document number: 200980112176.3 Country of ref document: CN |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 09728038 Country of ref document: EP Kind code of ref document: A1 |
|
ENP | Entry into the national phase |
Ref document number: 2010505349 Country of ref document: JP Kind code of ref document: A |
|
WWE | Wipo information: entry into national phase |
Ref document number: PI 2010004229 Country of ref document: MY |
|
WWE | Wipo information: entry into national phase |
Ref document number: 12922688 Country of ref document: US |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
ENP | Entry into the national phase |
Ref document number: 20107022590 Country of ref document: KR Kind code of ref document: A |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 09728038 Country of ref document: EP Kind code of ref document: A1 |