JP5188075B2 - 回路基板の製造方法及び半導体製造装置 - Google Patents
回路基板の製造方法及び半導体製造装置 Download PDFInfo
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- JP5188075B2 JP5188075B2 JP2007036257A JP2007036257A JP5188075B2 JP 5188075 B2 JP5188075 B2 JP 5188075B2 JP 2007036257 A JP2007036257 A JP 2007036257A JP 2007036257 A JP2007036257 A JP 2007036257A JP 5188075 B2 JP5188075 B2 JP 5188075B2
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
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- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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Description
(実施例1)
(1)樹脂ワニスの調製
ノボラック型シアネート樹脂(ロンザジャパン株式会社製、プリマセットPT−30、平均分子量約700)19.7重量部、ビフェニルジメチレン型エポキシ樹脂(日本化薬株式会社製、NC−3000H、エポキシ当量275)11重量部、ビフェニルジメチレン型フェノール樹脂(明和化成株式会社製、MEH−7851−3H、水酸基当量230)9重量部、およびエポキシシラン型カップリング剤(GE東芝シリコーン株式会社製、A−187)0.3重量部をメチルエチルケトンに常温で溶解し、球状溶融シリカ(株式会社アドマテックス社製、球状溶融シリカ、SO−25R、平均粒径0.5μm)60重量部を添加し、高速攪拌機を用いて10分攪拌して、樹脂ワニスを得た。
(2)プリプレグの製造
上述の樹脂ワニスをガラスクロス(厚さ94μm、日東紡績製、WEA−2116)に含浸し、150℃の加熱炉で2分間乾燥して、ワニス固形分が約50質量%のプリプレグを得た。
(3)積層板の製造
上述のプリプレグの両面に18μmの銅箔を重ねて、圧力4MPa、温度200℃で2時間加熱加圧成形することによって、厚さ0.2mmの積層板を得た。
(4)回路基板の作製
上記方法により製造された積層板を用いて配線パターンを有する回路基板を10個作製した。このとき作製された回路基板のうち、5個は図13に示すような加熱温度プロファイルが設定されたリフロ装置(HELLER社製 1812EXL−S)で最高温度260度で加熱し(実施例1)、残り5個はかかる加熱を行わなかった(比較例1)。
(実験2)
上記作製したシアネート系のプリプレグをビスマレイミドトリアジン系のプリプレグ(三菱瓦斯化学製 HL832HS)に変更し、実験1と同様の実験を行った。この実験において作製された回路基板のうち、5個は上述の図13の加熱温度プロファイルが設定されたリフロ装置で最高温度260度で加熱し(実施例2)、残り5個はかかる加熱を行わなかった(比較例2)。
(実験3)
実験1の封止樹脂の厚みを1.2mmの厚みに変更し、実施例3として上記加熱処理を行ったサンプルを5個、比較例3としてかかる加熱処理を行っていないサンプルを5個作製した。同様に、実験2の封止樹脂の厚みを1.2mmの厚みに変更し、比較例4として上記加熱処理を行ったサンプルを5個、比較例5としてかかる加熱処理を行っていないサンプルを5個作製した。
12 プリプレグ
14 導体層
15 配線パターン
Claims (4)
- 繊維基材に樹脂を含浸させてなるプリプレグを含む、厚さ500μm以下の回路基板を製造する製造方法であって、
前記製造方法により製造された回路基板は、当該回路基板に半導体素子を実装する半導体素子実装処理、前記実装された半導体素子の少なくとも上部及び側面を封止樹脂組成物により封止する封止処理、前記封止処理後、前記封止樹脂組成物を加熱・硬化させるポストモールドキュア処理、及び前記回路基板における前記半導体素子の実装された面と反対の面にリフロ装置を用いて半田ボールを付けるリフロ処理を行うことにより製造される半導体装置に適用され、
前記製造方法は、
前記半導体素子実装処理の直前に、最高温度が前記含浸される樹脂の硬化後のガラス転移温度より高い温度で前記製造されるべき回路基板を加熱する加熱工程を有し、
前記加熱工程の後は、前記ポストモールドキュア処理前後及び前記リフロ処理後のいずれにおいても、前記回路基板はその両端を基準位置として、前記半導体素子が実装されている面と反対の面側に凸の反りを有することを特徴とする製造方法。 - 前記最高温度は、前記半田ボール付け時に用いられる半田の融点温度以上、当該融点温度+80度以下の範囲であることを特徴とする請求項1記載の製造方法。
- 前記加熱工程では前記リフロ装置を用いて前記回路基板を加熱することを特徴とする請求項1又は2記載の製造方法。
- 繊維基材に樹脂を含浸させてなるプリプレグを含む、厚さ500μm以下の回路基板を製造する回路基板製造処理と、前記回路基板に半導体素子を実装する半導体素子実装処理と、前記実装された半導体素子の少なくとも上部及び側面を封止樹脂組成物により封止する封止処理と、前記封止処理後、前記封止樹脂組成物を加熱・硬化させるポストモールドキュア処理と、前記回路基板における前記半導体素子の実装された面と反対の面にリフロ装置を用いて半田ボールを付けるリフロ処理とを行うことにより半導体装置を製造する半導体製造装置において、
前記回路基板製造処理を行う装置は、前記半導体素子実装処理の直前に、最高温度が前記含浸される樹脂の硬化後のガラス転移温度より高い温度で前記製造されるべき回路基板を加熱する加熱処理を行う前記リフロ装置、オーブン、熱盤プレスのいずれか一つからなる加熱装置を含み、
前記加熱処理の後は、前記ポストモールドキュア処理前後及び前記リフロ処理後のいずれにおいても、前記回路基板はその両端を基準位置として、前記半導体素子が実装されている面と反対の面側に凸の反りを有することを特徴とする半導体製造装置。
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
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JP2007036257A JP5188075B2 (ja) | 2007-02-16 | 2007-02-16 | 回路基板の製造方法及び半導体製造装置 |
CN2008800051824A CN101611490B (zh) | 2007-02-16 | 2008-02-08 | 电路板的制造方法、半导体制造装置、电路板和半导体器件 |
MYPI20093411 MY153017A (en) | 2007-02-16 | 2008-02-08 | Circuit board manufacturing method, semiconductor manufacturing apparatus, circuit board and semiconductor device |
KR1020097016928A KR101409048B1 (ko) | 2007-02-16 | 2008-02-08 | 회로 기판의 제조 방법, 반도체 제조 장치, 회로 기판 및 반도체 장치 |
PCT/JP2008/052586 WO2008099940A1 (ja) | 2007-02-16 | 2008-02-08 | 回路基板の製造方法、半導体製造装置、回路基板及び半導体装置 |
US12/526,631 US8592256B2 (en) | 2007-02-16 | 2008-02-08 | Circuit board manufacturing method, semiconductor manufacturing apparatus, circuit board and semiconductor device |
TW097105483A TWI424510B (zh) | 2007-02-16 | 2008-02-15 | Circuit board manufacturing method and semiconductor manufacturing device |
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JP2007036257A JP5188075B2 (ja) | 2007-02-16 | 2007-02-16 | 回路基板の製造方法及び半導体製造装置 |
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JP5188075B2 true JP5188075B2 (ja) | 2013-04-24 |
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JP2003031926A (ja) * | 2001-07-19 | 2003-01-31 | Kyoei Sangyo Kk | プリント基板のそり矯正方法 |
JP2003283109A (ja) * | 2003-04-25 | 2003-10-03 | Matsushita Electric Ind Co Ltd | 回路形成基板の製造方法 |
TW200638812A (en) * | 2004-11-18 | 2006-11-01 | Matsushita Electric Ind Co Ltd | Wiring board, method for manufacturing same and semiconductor device |
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