WO2008099940A1 - 回路基板の製造方法、半導体製造装置、回路基板及び半導体装置 - Google Patents
回路基板の製造方法、半導体製造装置、回路基板及び半導体装置 Download PDFInfo
- Publication number
- WO2008099940A1 WO2008099940A1 PCT/JP2008/052586 JP2008052586W WO2008099940A1 WO 2008099940 A1 WO2008099940 A1 WO 2008099940A1 JP 2008052586 W JP2008052586 W JP 2008052586W WO 2008099940 A1 WO2008099940 A1 WO 2008099940A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- circuit board
- resin
- semiconductor element
- thickness
- semiconductor
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/145—Organic substrates, e.g. plastic
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48095—Kinked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0313—Organic insulating material
- H05K1/0353—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement
- H05K1/0366—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement reinforced, e.g. by fibres, fabrics
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
- H05K2203/1105—Heating or thermal processing not related to soldering, firing, curing or laminating, e.g. for shaping the substrate or during finish plating
Definitions
- the present invention relates to a circuit board manufacturing method and a semiconductor manufacturing apparatus, and more particularly to a next generation circuit board manufacturing method and a semiconductor manufacturing apparatus.
- Area-mounted semiconductor devices are assembled in the following process. First, a semiconductor element is mounted on one side of a circuit board, and only the semiconductor element mounting surface, that is, one side of the board is molded and sealed with an epoxy resin composition or the like. After that, a Pb-free solder ball is attached to the surface of the circuit board on which the semiconductor element is not mounted at a temperature of 230 ° C. to 2600 ° C. In addition, electronic devices are manufactured by a process (secondary mounting process) for mounting this area-mounted semiconductor device on a substrate.
- the circuit board material must have the property of high elasticity during heat in order to improve the mountability during reflow processing. Also, strain due to thermal expansion When this is large, the stress of the substrate becomes high and the characteristic that the thermal expansion coefficient is low is also required. On the other hand, it is necessary to have high rigidity even at a thin substrate at room temperature. That is, the substrate material must have high heat resistance, that is, high glass transition temperature (T g). For this reason, substrate materials that satisfy these characteristics have been developed.
- T g glass transition temperature
- An object of the present invention is to provide a circuit board manufacturing method and a semiconductor manufacturing apparatus capable of stably manufacturing a next-generation semiconductor device and improving the yield at the time of secondary mounting processing. It is in. Disclosure of the invention
- a fiber substrate is impregnated with a resin to produce a circuit board having a thickness of 500 / zm or less, and a semiconductor element is provided on the circuit board. And at least the upper and side surfaces of the mounted semiconductor element are sealed with a sealing resin composition, and the circuit board is lifted to a surface opposite to the surface on which the semiconductor element is mounted.
- the glass transition temperature after curing of the resin to be impregnated is determined before the soldering.
- the maximum temperature of the circuit board when heated in the heating step is in a range of not less than the melting point temperature of the solder used at the time of solder ball attachment and not more than the melting point temperature + 80 ° C. Is preferred.
- the heating step is performed before mounting the semiconductor element.
- the circuit board is heated using the reflow device in the heating step.
- a fiber substrate is impregnated with a resin to produce a circuit board having a thickness of 500 ⁇ m or less, and a semiconductor element is provided on the circuit board. And at least the upper and side surfaces of the mounted semiconductor element are sealed with a sealing resin composition, and the circuit board is lifted to a surface opposite to the surface on which the semiconductor element is mounted.
- the method includes a heating step of heating the circuit board at a temperature higher than a glass transition temperature after curing of the impregnated resin before the solder ball attachment.
- a semiconductor manufacturing apparatus is provided.
- a fiber substrate A circuit board having a thickness of 500 / xm or less in the core part, the circuit board, a semiconductor element disposed on one surface of the circuit board, and at least an upper part of the semiconductor element and
- the circuit board is applied to a semiconductor device comprising a cured product of a sealing resin composition that seals a side surface, and the thickness of the cured product of the sealing resin composition is four times or less the thickness of the circuit board.
- a circuit board has both ends as reference positions and a convex warp on the surface opposite to the surface on which the semiconductor element is disposed, and the circuit board is placed at 2600 ° C. for 1 minute.
- a circuit board is provided that maintains the convex warpage at room temperature after heat treatment.
- a semiconductor device comprising the above circuit board is provided.
- FIG. 1 is a cross-sectional view of a circuit board manufactured by the manufacturing method according to the first embodiment of the present invention.
- FIGS. 2A to 2J are diagrams used to explain the manufacturing process of the circuit board of FIG.
- 3A to 3E are diagrams used for explaining a manufacturing process of a semiconductor device using a circuit board.
- FIG. 4 is a graph showing the amount of warpage in Comparative Example 1.
- FIG. 5 is a graph showing the amount of warpage in Example 1.
- FIG. 6 is a graph showing the amount of warpage in Comparative Example 2.
- FIG. 7 is a graph showing the amount of warpage in Example 2.
- FIG. 8 is a graph showing the amount of warpage in Comparative Example 3.
- FIG. 9 is a graph showing the amount of warpage in Comparative Example 4.
- FIG. 10 is a graph showing the amount of warpage in Example 3.
- FIG. 11 is a graph showing the amount of warpage in Comparative Example 5.
- Figures 12 A and 12 B are diagrams used to explain the warpage of a semiconductor device.
- Figure 12 A is a case where a smile warp occurs
- Figure 12 B is a warping warpage. The case where it has occurred is shown.
- Figure 13 is a graph showing the heating temperature profile during heat treatment.
- FIG. 14 is a graph showing the amounts of warpage after the PMC treatment and after the heat treatment in Examples 4 and 5 and Comparative Examples 6 and 7.
- the present inventor manufactured a circuit board having a thickness of 500 / m or less by impregnating a fiber base material with a resin, and mounted a semiconductor element on the circuit board. At least the upper and side surfaces of the mounted semiconductor element are sealed with a sealing resin composition, and soldered using a reflow device on the surface of the circuit board opposite to the surface where the semiconductor element is mounted.
- the circuit board is heated at a temperature higher than the glass transition temperature after curing of the resin to be impregnated before soldering. It has been found that having a heating process can stably manufacture a next-generation semiconductor device and can improve the yield during the secondary mounting process.
- the circuit board is a circuit board having a fiber base material in the core portion and having a thickness of 500 ⁇ m or less, and the circuit board and the circuit board.
- a circuit board applied to a semiconductor device comprising a semiconductor element disposed on one surface and a cured product of a sealing resin composition that seals at least the upper and side surfaces of the semiconductor element
- the thickness of the cured product of the fat composition is not more than 4 times the thickness of the circuit board.
- it has a convex warp on the surface opposite to the surface on which the semiconductor element is disposed, and the circuit board is heat-treated at 260 ° C. for 1 minute, and then at room temperature.
- the warpage on the convex side is maintained, the distortion of the circuit board caused by thermal expansion during solder ball attachment and subsequent secondary mounting processing is small, and the next-generation semiconductor device can be stably manufactured. We found that the yield during the secondary mounting process can be improved.
- the present invention has been made based on the above findings.
- FIG. 1 is a cross-sectional view of a circuit board manufactured by a manufacturing method according to an embodiment of the present invention.
- a circuit board 1 1 includes a prepreg 1 2 as a substrate material, a conductor layer 1 4, and a wiring pattern 1 5, and the total thickness is 2 3 0 ⁇ m. ⁇ .
- the total thickness of the circuit board 11 is 2300 ⁇ , but the thickness is not limited to this as long as it is a thin board used as a next-generation circuit board.
- the total thickness of the circuit board 11 is preferably 25 to 500 / zm, and more preferably 60 to 400 / im. When the thickness is within the above range, the effect of reducing warpage by heating the circuit board 11 is particularly excellent.
- FIGS. 8 to 2 are drawings used to explain the manufacturing process of the circuit board 11 shown in FIG.
- a resin composition to be impregnated into glass cloth as a fiber base material is prepared.
- the resin composition impregnated into the glass cloth is not particularly limited as long as it has a high glass transition temperature and appropriate strength, but may be composed of a resin composition containing a thermosetting resin. I like it. As a result, the heat resistance of the pre-preg 12 can be improved.
- the thermosetting resin include a novolak type phenolic resin such as phenol novolac resin, cresol novolac resin, bisphenol A novolac resin, and unmodified resole. Phenolic resins such as oil-modified resole phenolic resins modified with phenolic resin, tung oil, Amani oil, walnut oil, etc.
- Phenolic resins such as bisphenol A type epoxy resin, bisphenol F type epoxy resin bisphenol S type epoxy resin Bisphenol E-type epoxy resin Bisphenol M-type epoxy resin, bisphenol t-type P epoxy resin Bisphenol Z-type epoxy resin Bisphenol-type epoxy resin such as phenol novolac type epoxy resin, Crezzo 1 Novolak type epoxy resin such as Renoborak epoxy resin, Bihue Type epoxy resin, biphenyl aralkyl type epoxy resin, aryl alkylene type epoxy resin, naphthalene type epoxy resin, anthracene type epoxy resin, phenoxy type epoxy resin, dicyclopentagen type epoxy resin, Norbornene type epoxy resin, adamantane type epoxy resin, epoxy resin such as fluorene type epoxy resin, resin having triazine ring such as urea (urea) resin, melamine resin, unsaturated polyester resin, Bismalay Examples thereof include a mid resin, a polyurethane resin, a diallyl phthalate resin, a silicone resin,
- One of these can be used alone, or two or more having different average molecular weights can be used in combination, or one or more can be used in combination with these prepolymers. You can also.
- cyanate resin (including prepolymers of cyanate resin) is particularly preferable. This makes it possible to reduce the thermal expansion coefficient of the pre-preda 1 2, and further, the pre-preda 1 2 with excellent electrical characteristics (low dielectric constant, low dielectric loss tangent), machine mechanical strength, etc. can do.
- the cyanate resin can be obtained, for example, by reacting a cyanogen halide compound with phenol and pre-polymerizing it by a method such as heating if necessary.
- bisphenol type silicate resins such as novolac type cyano resin, bisphenol A type cyano resin, bisphenol E type cyano resin, tetramethyl bisphenol F type cyano resin, etc. Can be mentioned.
- the novolak type silicate resin is preferred.
- the heat resistance can be improved by increasing the crosslinking density, and the flame retardancy of the resin composition and the like can be improved.
- the nopolac type cyanate resin forms a triazine ring after the curing reaction.
- the novolac type cyanate resin has a high benzene ring ratio due to its structure and is easily carbonized.
- the pre-preda 1 2 is made to have a thickness of 500 / xm or less, it is possible to give excellent rigidity to the double-sided copper-clad laminate produced by curing the pre-preda 1 2. it can. In particular, since it has excellent rigidity during heating, the reliability of the semiconductor chip 3 1 shown in FIG.
- novolac type silicate resin for example, a resin represented by the formula (I) can be used.
- the average repeating unit n of the novolac type cyanate resin represented by the above formula (I) is not particularly limited, but 1 to 10 is preferable, and 2 to 7 is particularly preferable.
- the average repeating unit n is less than the above lower limit, the novolac type cyanate resin has low heat resistance, and the low-mer may desorb and volatilize when heated.
- the average repeating unit n exceeds the above upper limit, the melt viscosity becomes too high, and the moldability of the prepreg 12 may decrease.
- the average molecular weight of the cyanate resin is not particularly limited, but an average molecular weight of 500 to 4,500 is preferable, and in particular, 600 to 3,00 is preferable.
- an average molecular weight is less than the above lower limit, tackiness may occur when the prepreader 12 is produced, and when the prepreader 12 is brought into contact with each other, it may adhere to each other or transfer of the resin may occur. is there.
- the average molecular weight exceeds the above actual value, the reaction becomes too fast, and when it is used as the circuit board 11, molding defects may occur or the interlayer peel strength may be lowered.
- the average molecular weight of the resin can be measured, for example, by GPC (Gel Permeation Chromatography, Standard: Polystyrene equivalent).
- the above-mentioned cyanate resin can be used alone, or two or more kinds having different average molecular weights can be used in combination, or one or two or more kinds thereof Can also be used together.
- the content of the thermosetting resin is not particularly limited, but is preferably from 50 to 50% by mass, particularly preferably from 20 to 40% by mass, based on the entire resin composition. If the content is less than the above lower limit value, it may be difficult to form the prepreader 12, and if the content exceeds the above upper limit value, the strength of the prepreader 12 may be reduced.
- the resin composition preferably includes an inorganic filler. to this Therefore, even if a laminated plate 20 described later is made thin (thickness of 500 / im or less), the strength can be improved. In addition, the low thermal expansion of the laminate 20 can be improved.
- the inorganic filler examples include talc, calcined clay, unsintered clay, my strength, silicates such as glass, oxides such as titanium oxide, alumina, silica, and molten silica, calcium carbonate , Carbonates such as magnesium carbonate, hydrotalcite, hydroxides such as aluminum hydroxide, magnesium hydroxide, and hydroxide power, sulfates such as barium sulfate, calcium sulfate, calcium sulfite, and sulfites Salts, borates such as zinc borate, barium metaborate, aluminum borate, calcium borate, sodium borate, aluminum nitride, boron nitride, silicon nitride, carbon nitride, etc.
- titanates such as nitrides, strontium titanate, and barium titanate.
- the inorganic filler one of these can be used alone, or two or more can be used together.
- silica is particularly preferable, and molten silica (especially spherical molten silica) is preferable because of its excellent low thermal expansion. There are crushed and spherical shapes, but in order to reduce the melt viscosity of the resin composition in order to ensure the impregnation of the fiber substrate, a method of use that suits the purpose is used, such as using spherical silica. .
- the average particle diameter of the inorganic filler is not particularly limited, but is preferably 0.11 to 5.O / zm, and particularly preferably 0.1 to 2. ⁇ . If the particle size of the inorganic filler is less than the above lower limit, the viscosity of the varnish will increase, which may affect the workability during the preparation of the prepreg 12. When the above upper limit is exceeded, phenomena such as sedimentation of the inorganic filler may occur in the varnish.
- This average particle diameter can be measured by, for example, a particle size distribution meter (manufactured by HORIBA, L A—500).
- the inorganic filler is not particularly limited, but the average particle size is monodisperse.
- An inorganic filler can be used, or an inorganic filler having a polydisperse average particle size can be used.
- one or more inorganic fillers having an average particle size of monodisperse and / or polydisperse may be used in combination.
- spherical silica having an average particle size of 5. ⁇ or less is preferred, and spherical fused silica having an average particle size of 0.01 to 2. ⁇ is particularly preferred.
- content of the said inorganic filler is not specifically limited, 20-80 mass of the whole resin composition. / 0 is preferred, especially 30 to 70 mass. / 0 is preferred. When the content is within the above range, particularly low thermal expansion and low water absorption can be achieved.
- cyanate resin particularly, novolak type cyanate resin
- an epoxy resin substantially free of halogen atoms.
- the epoxy resin include bisphenol-type epoxy resin, bisphenol F-type epoxy resin, bisphenol E-type epoxy resin, bisphenol S-type epoxy resin, and bisphenol M-type epoxy.
- bisphenol type epoxy resin such as bisphenol P type epoxy resin, bisphenol Z type epoxy resin, novolac type epoxy resin such as phenol novolac type epoxy resin, cresol novolac epoxy resin, biphenyl Type epoxy resin, xylylene type epoxy resin, arylalkylene type epoxy resin such as bialkylaralkyl type epoxy resin, naphthalene type epoxy resin, anthracene type epoxy resin, phenoxy type epoxy resin, dicyclopentagen type epoxy Resin, norbornene type Carboxymethyl resins, Adamantan type Epoki shea resins and fluorene type epoxy resins and the like.
- epoxy resin one of these can be used alone, or two or more having different average molecular weights can be used together, or one or two or more can be used. You can also use these pre-polymers together.
- aryl alkylene type epoxy resins are particularly preferable. As a result, the moisture absorption solder heat resistance and flame retardancy can be improved.
- the arylalkylene type epoxy resin refers to an epoxy resin having one or more arylalkylene groups in a repeating unit.
- xylene type epoxy resin, biphenyldimethylene type epoxy resin and the like can be mentioned. Of these, biphenyldimethylene type epoxy resin is preferred.
- Biphenyldimethylene type epoxy resin can be represented, for example, by the formula (I I).
- n is an arbitrary integer
- the average repeating unit n of the bif-di-dimethylene type epoxy resin represented by the above formula (I I) is not particularly limited, but is preferably 110 and particularly preferably 25. If the average repeating unit n is less than the above lower limit, the biphenylindimethylene type epoxy resin is likely to be crystallized, and its solubility in a general-purpose solvent is relatively lowered, which may make handling difficult. In addition, when the average repeat unit n exceeds the above upper limit, the fluidity of the resin is lowered, which may cause molding defects.
- the content of the epoxy resin is not particularly limited, but the entire resin composition 1-5 5 mass. / 0 is preferable, and 2 to 40% by mass is particularly preferable. If the content is less than the above lower limit, the reactivity of the cyanate resin may be reduced, or the moisture resistance of the resulting product may be reduced. If the content exceeds the upper limit, the heat resistance will be reduced. There is.
- the average molecular weight of the epoxy resin is not particularly limited, but an average molecular weight of 500 to 20 and 00 is preferable, and 80 to 15 and 00 is particularly preferable. If the average molecular weight is less than the above lower limit, tackiness may occur in the pre-preder 12, and if it exceeds the above upper limit, the impregnation property into the glass fiber will be lowered and uniform during the preparation of the pre-preder 12. May not be available.
- the average molecular weight of the epoxy resin can be measured, for example, by GPC. When cyanate resin (especially novolac type cyanate resin) is used as the thermosetting resin, it is preferable to use phenol resin.
- phenol resin examples include novolak type phenol resin, resole type phenol resin, aryl alkylene type phenol resin and the like.
- phenolic resin one of these can be used alone, or two or more having different average molecular weights can be used together, or one or two or more can be used as a prepolymer. Can be used together.
- aryl alkylene type phenol resins are particularly preferred. As a result, the heat resistance of the hygroscopic solder can be further improved.
- aryl alkylene type phenol resin examples include a xylylene type phenol resin and a biphenyldimethylene type phenol resin.
- the biphenyldimethylene type phenolic resin can be represented, for example, by the formula (III). [Chemical 3]
- n is an arbitrary integer
- the repeating unit n of the biphenyldimethylene type phenol resin represented by the above formula (I I I) is not particularly limited, but 1 to 12 is preferable, and 2 to 8 is particularly preferable. If the average repeating unit n is less than the lower limit, the heat resistance may be lowered. If the above upper limit is exceeded, compatibility with other resins may be reduced, and workability may be reduced.
- cyanate resins especially novolac-type cyanate resins
- arylalkylene-type phenolic resins control the crosslink density and facilitate reactivity. Can be controlled.
- the content of the phenol resin is not particularly limited, but is 1 to 55 mass of the entire resin composition. / 0 is preferred, especially 5 to 40 mass. / 0 is preferred. When the content is less than the above lower limit value, the heat resistance may be lowered, and when the content exceeds the above upper limit value, the characteristics of low thermal expansion may be impaired.
- the average molecular weight of the phenol resin is not particularly limited, but an average molecular weight of 400 to 18 and 0:00 is preferable, and 5500 to: 15 and 00 is particularly preferable. If the average molecular weight is less than the above lower limit value, tackiness may occur in the pre-preder 12 . If the average molecular weight exceeds the above upper limit value, the impregnation property into the glass cloth is reduced during the preparation of the pre-preder 1 2, A uniform product may not be obtained.
- the average molecular weight of the above funol resin can be measured by GPC, for example.
- the above-mentioned cyanate resin especially a novolac-type cyanate resin
- the above-mentioned phenolic resin arylalkylene-type phenolic resin, particularly biphenylethylene-type phenolic resin
- the above-mentioned epoxy resin realal.
- Particularly excellent dimensional stability can be obtained when the circuit board 11 is produced by using a combination with a xylene type epoxy resin (especially biphenyldimethylene type epoxy resin).
- the resin composition is not particularly limited, but it is preferable to use a coupling agent.
- the above-mentioned coupling agent improves the wettability of the interface between the thermosetting resin and the inorganic filler so that the thermosetting resin and the like and the inorganic filler are uniformly applied to the glass cloth. Fixing can improve heat resistance, especially solder heat resistance after moisture absorption.
- any of those usually used can be used.
- epoxy silane coupling agents, cationic silane coupling agents, amino silane coupling agents, titanate-based caps It is preferable to use at least one type of coupling agent selected from among a coupling agent and a silicone oil type coupling agent. As a result, the wettability with the interface of the inorganic filler can be increased, whereby the heat resistance can be further improved.
- the amount of the cupping agent added is not particularly limited because it depends on the specific surface area of the inorganic filler, but is preferably 0.05 to 3 parts by weight with respect to 100 parts by weight of the inorganic filler. In particular, 0.1 to 2 parts by weight is preferred. If the content is less than the above lower limit value, the effect of improving heat resistance may be reduced because the inorganic filler cannot be coated in plus minutes. If the upper limit value is exceeded, the reaction is affected, bending strength, etc. May decrease.
- a curing accelerator may be used in the resin composition as necessary. As the curing accelerator, known materials can be used.
- organic metal salts such as zinc naphthenate, cobalt naphthenate, tin octylate, cobalt octylate, biacetyl acetate toner cobalt (II), triacetyl acetate toner cobalt (III), triethylamine, etc.
- Tributylamine diazabicyclo [2, 2, 2] octane and other tertiary amines
- 2 — phenilou 4 methinolemidazole
- 2 — echinore 1 4 ethylimidazole Zole
- 2—Phenol / Lae 4-Metinoreid Midazole 2—Phenyl 4-Methyl 1—Hydroxidyl Midazol Nore
- the curing accelerator one kind including these derivatives can be used alone, or two or more kinds including these derivatives can be used in combination.
- the content of the curing accelerator is not particularly limited, but is 0.05 to 5 mass of the entire resin composition. / 0 is preferable, and 0.2 to 2% by mass is particularly preferable. If the content is less than the above lower limit value, the effect of promoting curing may not appear, and if the content exceeds the above upper limit value, the preservability of the pre-pre- der 12 may be lowered.
- a phenoxy resin a polyimide resin, a polyimide resin, a polyphenylene oxide resin, a polyethersulfone resin, a polyester resin, a polyylene resin, a polymer resin.
- Polystyrene thermoplastic elastomers such as styrene resins, polystyrene thermoplastic elastomers such as styrene monobutadiene copolymer, styrene monoisoprene copolymer, polyolefin thermoplastic elastomer, poly Medium Elastomer, Polyester Eras It is also possible to use a combination of gen- eral elastomers such as a thermoplastic elastomer such as Toma, polybutadiene, epoxy-modified polybutadiene, acrylic-modified polybutadiene, and methacryl-modified polybutadiene.
- gen- eral elastomers such as a thermoplastic elastomer such as Toma, polybutadiene, epoxy-modified polybutadiene, acrylic-modified polybutadiene, and methacryl-modified polybutadiene.
- the sd fat composition is impregnated into a glass cloth as a fiber base material to produce a prepreg 12 (FIG. 2A).
- a prepreg 12 (FIG. 2A)
- commercially available products include cyanate-based products manufactured by Sumitomo Belit Corporation, and bismaray-triadine-based materials manufactured by Mitsubishi Gas Chemical Co., Ltd.
- Examples of the glass constituting the glass cross (glass fiber substrate) include E glass, S glass, NE glass,
- a glass cloth (glass fiber base material) is used.
- polyamide resin fiber such as wholly aromatic polyamide resin fibers, polyester resin fibers, polyester resin fibers such as aromatic polyester resin fibers, and polyester resin fibers such as wholly aromatic polyester resin fibers
- Synthetic fiber base materials made of woven or non-woven fabrics mainly composed of resin fibers, fluorine-based resin fibers, etc., craft paper, cotton linter paper, linter and kraft pulp Examples thereof include organic fiber base materials such as paper base materials mainly composed of mixed paper. Of these, glass fiber substrates are preferred.
- the strength and water absorption rate of the pre-preder 12 can be improved.
- the thermal expansion coefficient of the pre-pre- der 12 can be reduced.
- a method of impregnating the glass composition with the resin composition in the present embodiment for example, a method of preparing a resin varnish using the resin composition described above, and immersing the glass cloth in a varnish of varnish, various types Examples include a coating method using a coater and a spraying method. Among these, a method in which glass cloth is immersed in a resin varnish is preferable. Thereby, it is possible to improve the impregnation property of the resin composition with respect to the glass cross. In addition, when dipping glass cloth in a resin varnish, a normal impregnation coating equipment can be used.
- the solvent used in the resin varnish is desirably good solubility with respect to the resin component in the resin composition, but a poor solvent may be used as long as it does not have an adverse effect.
- Solvents that exhibit good solubility include, for example, acetate, methyl ethyl ketone, methyl isobutyl ketone, cyclohexanone, tetrahydrofuran, dimethyl formamide, dimethyl ether.
- Examples include cetamide, dimethyl sulphonoxide, ethylene glycol, cellosolve, and carbitol.
- the solid content of the resin varnish is not particularly limited, the solid content of the resin composition is 40 to 80 mass. / 0 is preferred, especially 50 to 65 mass. / 0 is preferred. As a result, the impregnation property of the resin varnish into the glass cloth can be further improved.
- the pre-preder 12 can be obtained by impregnating the glass composition with the resin composition and drying it at a predetermined temperature, for example, 80 to 200 ° C.
- laminated plate 2 0 After preparation of the pre-preda 1 2, the copper foil 2 3 is stacked on both sides of the pre-preda 1 2 and then heated and pressed to form a double-sided copper-clad laminate 20 (hereinafter simply referred to as “laminated plate 2 0”). Make it ( Figure 2B). As a result, it is possible to obtain a laminated board having excellent dielectric characteristics, high mechanical and electrical connection reliability at high temperature and high humidity.
- the laminate plate 20 of the present embodiment uses a single pre-preda 1 2.
- the copper foils 2 3 are stacked on the upper and lower surfaces, but a metal foil or film other than the copper foils 2 3 may be stacked. It is also possible to stack two or more pre-preders 12.
- the outermost upper and lower surfaces or one side of the stacked pre-preders 1 2 are made of metal.
- the heating temperature at the time of producing the laminated plate 20 is not particularly limited, but is preferably 120 to 220 ° C, and particularly 150 to 200 °.
- the pressure to pressurize is not particularly limited, but 2 to 5 MPa is preferable, and 2.5 to 4 MPa is particularly preferable.
- Examples of the metal constituting the metal foil include copper foil 23, copper alloy, aluminum and aluminum alloy, silver and silver alloy, gold and gold alloy, zinc and zinc alloy, nickel and Examples include nickel-based alloys, tin and tin-based alloys, iron and iron-based alloys.
- Examples of the film include polyethylene, polypropylene, polyethylene terephthalate, polyimide, and fluorine-based resin.
- a through hole 21 is formed in a required portion thereof by using, for example, a mechanical drill (Fig. 2C), and then the inside of the through hole 21 is formed by electroless copper plating.
- the surface of the copper foil 2 3 is coated with a thin electroless copper 2 4 having a thickness of 1 ⁇ (Fig. 2D).
- a conductor layer 14 (FIG. 1) is formed.
- panel plating is performed in which copper 25 is thickened to a thickness of 10 ⁇ or more on electroless copper 24 on the chip mounting surface side, which will be described later, with electrolytic copper plating (FIG. 2E).
- the thickness of the electroless copper 24 is l 1 um
- the thickness of the copper 25 is 10 m or more.
- the present invention is not limited to this.
- the exposed portion of copper 25 is removed by, for example, wet etching (FIG. 2H), and then the resist 26 is removed. By removing, the required wiring pattern 15 is formed on the chip mounting side of the pre-pre- der 12 (FIG. 21).
- 3A to 3E are diagrams used for explaining a manufacturing process of a semiconductor device using the circuit board 11.
- an adhesive 30 such as epoxy resin is applied to the chip mounting area on the wiring pattern 15 of the circuit board 11.
- the semiconductor chip 3 1 is bonded to the chip mounting area with the adhesive 30, with the back surface of the semiconductor chip 31 to be mounted (the surface opposite to the side where the electrodes are formed) facing down,
- the electrode of the semiconductor chip 3 1 and the conductive layer 14 are electrically connected, for example, by an Au bonding wire 3 2 through the wiring pattern 15 (FIG. 3B).
- the sealing resin 3 3 may seal at least the upper and side surfaces of the semiconductor chip 3 1, more specifically, the bonding wire 3 2, as shown in FIG. 3C. It is not limited to the form in which the entire chip mounting surface of the circuit board 11 is sealed.
- the thickness after curing of the sealing ⁇ 3 3 is 6 0 0 ⁇ ⁇
- of the circuit board 1 1 is a thickness of 2 3 0 ⁇ ⁇ thickness Mino 2. 6-fold Although it has a thickness, it is not limited to this as long as it is 4 times or less the thickness of the circuit board 11 used in the next-generation semiconductor device.
- the solder balls 3 4 are joined to the circuit board 11 (FIG. 3D) to manufacture the semiconductor device.
- the temperature of the riffle opening device is set so that the maximum temperature is 2600 degrees.
- an electronic device is manufactured.
- the maximum temperature of the riffle apparatus in the heat treatment of FIG. 2 J is higher than the glass transition temperature after curing of the resin composition impregnated in the glass cloth constituting the prepreg 12.
- the maximum reflow temperature is not particularly limited, but is preferably 20 degrees or more higher than the glass transition temperature of the cured product of the resin composition impregnated in the glass cloth, and more preferably 40 degrees or more. Is preferred.
- the glass transition temperature was determined by cutting the cured product of the above resin composition into a 4 mm x 2 O mm sample as an evaluation sample, and using a TMA apparatus (TMA) (TA Instruments Inc.). The temperature is raised at 10 ° C / min.
- the internal stress of the circuit board 11 can be relaxed.
- the circuit board 1 1 is thin and has a thickness of less than 50 0 ⁇ . Even in this case, the fluctuation of the warp of the circuit board 11 before and after the reflow process in FIG. 3D can be reduced, and the secondary mounting in FIG. 3E can be performed appropriately.
- the heating temperature profile of the lift opening device in the heat treatment of Fig. 2 J can use, for example, JEDEC standard J — STD — 0 2 0 C (Ju 1 y 2 0 0 4).
- the temperature is set according to the melting point of the solder balls 34. Specifically, if the solder balls 3 4 are eutectic solder (melting point 1 83 degrees), 2 25 degrees to 2 40 degrees, and if the solder balls 3 4 are lead free solders (melting point 2 1 In the case of (7 degrees), it may be performed from 2 45 degrees to 2 60 degrees. In other words, it is preferable that the maximum temperature of the circuit board 11 in the heat treatment of FIG.
- 2 J be in the range of the melting point temperature of the solder balls 34 or more and the melting point temperature +80 degrees or less.
- the above maximum temperature is below the melting point temperature of the solder ball 34, the warp fluctuation of the circuit board 11 that occurs before and after the reflow treatment is not sufficiently suppressed, and when the melting point temperature of the solder ball 34 is higher than + 8 ° C, The resin composition contained in the circuit board 1 1 is not preferable because it thermally deteriorates.
- the heat treatment is not limited to the reflow apparatus, and a method using oven heating or hot platen press may be used.
- a method of placing the substrate in an oven or hot platen press set to a heating temperature, or a method of raising the temperature after placing the substrate in an oven or hot platen press lower than the heating temperature may be used.
- the heat treatment in FIG. 2J is performed before the mounting of the semiconductor chip 31.
- the heat treatment is not limited to this if it is performed before the reflow treatment in FIG. 3D.
- the cured resin of the sealing resin 33 it is possible to prevent cracking due to heating and to ensure the fluctuation of the warping of the circuit board 11 that occurs before and after the reflow treatment of FIG. 3D. Therefore, it is most preferable to perform the process before mounting the semiconductor chip 31 as in the present embodiment. ..
- the warping of the circuit board 11 after the reflow treatment of FIG. 3D becomes a smile warp. Therefore, during the secondary mounting process of FIG. Yield is improved.
- the solder balls 3 4 arranged at the end of the circuit board 11 will be replaced with 2 in FIG. 3E.
- the solder balls 3 4 may be in contact with each other and shoot, which may reduce the yield.
- the circuit board 1 1 after processing in FIG. 3C has a smile warp, and the circuit board 1 1 with the smile warp is heat-treated at 26 ° C. for 1 minute. Since the smile warp is maintained at room temperature, the distortion of the circuit board 1 1 caused by thermal expansion during the solder ball mounting process shown in Fig. 3D and the secondary mounting process shown in Fig. 3 £ is small. Generation semiconductor devices can be manufactured stably, and the yield during secondary mounting is improved. ⁇ Example ⁇
- Novolac-type cyanate resin (Lonza Japan Co., Ltd., pre-set PT—30, average molecular weight of about 70,000) 19.7 parts by weight, biphenyldimethylene-type epoxy resin (Nippon Kayaku Co., Ltd.) , NC—300 0 H, Epoxy equivalent 2 7 5) 1 1 part by weight, biphenyldimethylene type phenol resin (Madewa Kasei Co., Ltd., MEH—7 8 5 1-3 H, hydroxyl equivalent 2 3 0) 9 parts by weight, and epoxy silane type coupling agent (GE TOSHIBA A- 1 8 7) 0.3 part by weight is dissolved in methyl ethyl ketone at room temperature, and spherical molten silica (manufactured by Admatechs Co., Ltd., spherical fused silica, SO_25) R, average particle size 0.5 / zm) 60 parts by weight were added and stirred for 10 minutes using a
- the above resin varnish was impregnated into a glass cloth (thickness 94 ⁇ , Nitto Boseki Co., Ltd., WE A-2 1 1 6) and dried for 2 minutes in a heating furnace at 1550 ° C. As a result, a cyanate-based pre-preda of about 50 mass% was obtained.
- Laminate with a thickness of 0.2 mm is obtained by stacking 18 / zm copper foil on both sides of the above pre-preder and then heat-pressing it at a pressure of 4 MPa and a temperature of 200 ° C for 2 hours. Got.
- the glass transition temperature of the cyanate-based pre-preder after the heat curing was 220 °.
- a Pb-free solder ball (manufactured by Senju Metal Co., Ltd., melting point 2 17 degrees) is placed on the back side of the circuit board, and the heating conditions shown in FIG. Heating reflow treatment was performed. After that, DRY treatment was performed in which secondary mounting was performed and drying was performed at 150 ° C. for 8 hours.
- the amount of warpage here refers to the height of the sample surface when both ends of the sample are used as reference positions, and was calculated from the average value of five samples.
- the cyanate-based pre-preparer prepared above was changed to a Bismalay-triadine-based pre-preda (Mitsubishi Gas Chemical's HL832HS), and an experiment similar to Experiment 1 was performed.
- the glass transition temperature of the above-mentioned heat-cured bismaleimide triazine pre-preda was 1850 degrees.
- five were heated at a maximum temperature of 2600 degrees with the reflow apparatus in which the heating temperature profile shown in Fig. 13 was set (Example 2). The remaining 5 were not heated (Comparative Example 2).
- Example 2 As a result of Experiment 2, in Comparative Example 2, it was found that the amount of warpage of the sample that had been warped before PMC treatment became larger after reflow treatment as shown in Fig. 6. . On the other hand, as shown in FIG. 7, it was found that Example 2 was a smile warpage before PMC treatment, and that there was almost no warpage fluctuation before and after each treatment.
- the thickness of the sealing resin in Experiment 1 was changed to 1.2 mm, and Example 3 was used. Thus, five samples that were subjected to the above heat treatment and five samples that were not subjected to such heat treatment were produced as Comparative Example 3. Similarly, the thickness of the sealing resin in Experiment 2 was changed to 1.2 mm, and five samples were subjected to the above heat treatment as Comparative Example 4 and the heat treatment was conducted as Comparative Example 5. Five samples were prepared.
- Example 3 has a larger amount of smile warpage than Comparative Example 3 before PMC treatment, but almost no warpage fluctuation occurs before and after each treatment. I understood it.
- the thickness of the sealing resin is 0.6 mm, either when the pre-preg is of the above-mentioned cyanate type, or when the thickness of the above-mentioned bismale mid-triazine type is used.
- the amount of warpage and warpage fluctuation can both be reduced by heat treatment before mounting the semiconductor chip.
- Novolac-type cyanate resin (Lonza Japan Co., Ltd., Primacet PT—30, average molecular weight of about 70,000) 19.7 parts by weight, biphenyldimethylene type epoxy resin (Nippon Kayaku NC-3O 0 0 0 H, Epoxy equivalent 2 7 5) 1 1 parts by weight, biphenyldimethylene type phenolic tree Moonlight (Maywa Kasei Co., Ltd., MEH-7 8 5 1 1 3 H, hydroxyl group equivalent 2 3 0) 9 parts by weight, and epoxy silane type coupling agent (GE Toshiba Silicone Co., Ltd., A— 1 8 7) 0.3 part by weight is dissolved in methylethylketone at room temperature, and spherical molten silica (manufactured by Admatechs Co., Ltd., spherical fused silica, SO-25 5 R, average particle size 0.5) ⁇ ⁇ ) 60 parts by weight was added and stirred for 10 minutes using a high-
- rosin varnish was impregnated in a glass cloth (thickness 94 ⁇ , Nitto Boseki Co., Ltd., WE A— 2 1 1 6), dried in a heating furnace at 1550 ° C. for 2 minutes, and varnish solid A cyanate pre-predder having a content of about 50% by mass was obtained.
- Example 5 Five of the circuit boards produced in the same manner as in Experiment 4 were obtained by changing the bismutale imide triazine prepare manufactured by Mitsubishi Gas Chemical Co., Ltd. Heating was performed at a maximum temperature of 2600 degrees using a reflow apparatus in which a heating temperature profile of 3 was set (Example 5), and the remaining 5 pieces were not heated (Comparative Example 7).
- the glass transition temperature of the above-described heat-cured Bismare-Mia-triazine pre-preda was 1850 degrees.
- PMC treatment was performed under the same heating conditions as in Experiment 4, the amount of warpage of each sample was measured by laser scanning. As a result, as shown in FIG. 5, it was found that Example 5 had a smile warpage and Comparative Example 7 had a warpage.
- a circuit board having a thickness of 500 ⁇ m or less manufactured by impregnating a fiber base material with a resin is applied before soldering. Since the resin impregnated above is heated at a temperature higher than the glass transition temperature after curing, the internal stress of the circuit board can be relieved.
- the circuit board 7) has a thickness of 500 ⁇ m or less. It is possible to reduce the fluctuation of the warping of the rotating substrate that occurs before and after the processing, and to stably manufacture the next generation semiconductor device, and to perform secondary mounting. Yield during processing can be improved.
- the maximum temperature of the circuit board when heated in the heating step is in the range of not less than the melting point temperature of the solder used for solder ball attachment and not more than the melting point temperature + 80 degrees.
- the maximum temperature is higher than the melting point temperature of the solder, the glass transition temperature after curing of the resin to be impregnated can be surely exceeded. Variations in substrate warpage can be sufficiently suppressed.
- the maximum temperature is set to the melting point temperature of solder + 80 ° C. or less, the thermal deterioration of the resin composition contained in the circuit board can be prevented.
- the heating step is performed before mounting the semiconductor element, cracks or the like due to heating may be generated in the cured product of the sealing resin composition constituting the semiconductor device.
- it is possible to reliably reduce the fluctuation of the circuit board warpage that occurs before and after the reflow treatment.
- the circuit board since the circuit board is heated using the lift opening device in the heating step, the circuit board can be easily and reliably heated.
- a circuit board having a thickness of 500 / zm or less manufactured by impregnating a fiber base material with resin is used as a solder ball. Heating is performed at a temperature lower than the glass transition temperature after curing of the resin to be impregnated before application, so that the internal stress of the circuit board can be relieved.
- the circuit board has a thickness of 50 Stable manufacturing of next-generation semiconductor devices by minimizing the fluctuations in circuit board warpage that occurs before and after the opening process even if it is as thin as 0 ⁇ or less. It is possible to improve the yield during the secondary mounting process.
- the thickness of the cured product of the sealing resin composition is not more than 4 times the thickness of the circuit board having a thickness of 500 / m or less.
- the substrate has a convex warp on the opposite side of the surface where the semiconductor element is disposed, with both ends of the substrate as reference positions, and the circuit board is heat-treated at 2600 ° C. for 1 minute.
- the convex warp is maintained at room temperature, which stabilizes the next-generation semiconductor device by using the circuit board distortion force zJ caused by thermal expansion during solder pole attachment and subsequent secondary mounting processing. Manufacturing and improving the yield during the primary mounting process.
- the next-generation semiconductor device can be more reliably stabilized because it has a convex warp of 0 100 ⁇ m on the opposite surface side from the reference position. And the yield during the secondary mounting process can be improved.
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN2008800051824A CN101611490B (zh) | 2007-02-16 | 2008-02-08 | 电路板的制造方法、半导体制造装置、电路板和半导体器件 |
US12/526,631 US8592256B2 (en) | 2007-02-16 | 2008-02-08 | Circuit board manufacturing method, semiconductor manufacturing apparatus, circuit board and semiconductor device |
KR1020097016928A KR101409048B1 (ko) | 2007-02-16 | 2008-02-08 | 회로 기판의 제조 방법, 반도체 제조 장치, 회로 기판 및 반도체 장치 |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007036257A JP5188075B2 (ja) | 2007-02-16 | 2007-02-16 | 回路基板の製造方法及び半導体製造装置 |
JP2007-036257 | 2007-02-16 | ||
JP2007092209A JP2008251891A (ja) | 2007-03-30 | 2007-03-30 | 回路基板及びその半導体装置 |
JP2007-092209 | 2007-03-30 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2008099940A1 true WO2008099940A1 (ja) | 2008-08-21 |
WO2008099940A9 WO2008099940A9 (ja) | 2011-06-03 |
Family
ID=39690165
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2008/052586 WO2008099940A1 (ja) | 2007-02-16 | 2008-02-08 | 回路基板の製造方法、半導体製造装置、回路基板及び半導体装置 |
Country Status (6)
Country | Link |
---|---|
US (1) | US8592256B2 (ja) |
KR (1) | KR101409048B1 (ja) |
CN (1) | CN101611490B (ja) |
MY (1) | MY153017A (ja) |
TW (1) | TWI424510B (ja) |
WO (1) | WO2008099940A1 (ja) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2008099940A1 (ja) * | 2007-02-16 | 2008-08-21 | Sumitomo Bakelite Co., Ltd. | 回路基板の製造方法、半導体製造装置、回路基板及び半導体装置 |
JP5249150B2 (ja) * | 2009-07-23 | 2013-07-31 | 株式会社東海理化電機製作所 | 磁気センサの製造方法及び磁気センサ |
US9059240B2 (en) | 2012-06-05 | 2015-06-16 | International Business Machines Corporation | Fixture for shaping a laminate substrate |
US9048245B2 (en) | 2012-06-05 | 2015-06-02 | International Business Machines Corporation | Method for shaping a laminate substrate |
TWI499020B (zh) * | 2012-11-28 | 2015-09-01 | 矽品精密工業股份有限公司 | 半導體基板之製法 |
SG11201600586XA (en) | 2013-09-09 | 2016-02-26 | Mitsubishi Gas Chemical Co | Prepreg, metal foil-clad laminate, and printed wiring board |
EP3451804B1 (en) * | 2017-08-28 | 2020-04-01 | Goodrich Actuation Systems Limited | Potting method |
CN108417501B (zh) | 2018-03-05 | 2020-03-24 | 台达电子企业管理(上海)有限公司 | 功率模块及其制备方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000091476A (ja) * | 1998-07-16 | 2000-03-31 | Nitto Denko Corp | 半導体装置 |
JP2003031926A (ja) * | 2001-07-19 | 2003-01-31 | Kyoei Sangyo Kk | プリント基板のそり矯正方法 |
JP2003283109A (ja) * | 2003-04-25 | 2003-10-03 | Matsushita Electric Ind Co Ltd | 回路形成基板の製造方法 |
WO2006054637A1 (ja) * | 2004-11-18 | 2006-05-26 | Matsushita Electric Industrial Co., Ltd. | 配線基板とその製造方法および半導体装置 |
Family Cites Families (42)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4794217A (en) * | 1985-04-01 | 1988-12-27 | Qing Hua University | Induction system for rapid heat treatment of semiconductor wafers |
US4983804A (en) * | 1989-12-21 | 1991-01-08 | At&T Bell Laboratories | Localized soldering by inductive heating |
TW272311B (ja) * | 1994-01-12 | 1996-03-11 | At & T Corp | |
US5516030A (en) * | 1994-07-20 | 1996-05-14 | Compaq Computer Corporation | Method and apparatus for assembling ball grid array components on printed circuit boards by reflowing before placement |
JPH1041615A (ja) * | 1996-07-19 | 1998-02-13 | Matsushita Electric Ind Co Ltd | 半導体チップ実装用基板、及び半導体チップの実装方法 |
US6077382A (en) * | 1997-05-09 | 2000-06-20 | Citizen Watch Co., Ltd | Mounting method of semiconductor chip |
TW396471B (en) * | 1997-06-04 | 2000-07-01 | Ibm | Electrodeposition of low temperature, high conductivity, powder materials for electrically conductive paste formulations |
US5919329A (en) * | 1997-10-14 | 1999-07-06 | Gore Enterprise Holdings, Inc. | Method for assembling an integrated circuit chip package having at least one semiconductor device |
US6448665B1 (en) * | 1997-10-15 | 2002-09-10 | Kabushiki Kaisha Toshiba | Semiconductor package and manufacturing method thereof |
US6593255B1 (en) * | 1998-03-03 | 2003-07-15 | Ppg Industries Ohio, Inc. | Impregnated glass fiber strands and products including the same |
JP2000216299A (ja) | 1999-01-21 | 2000-08-04 | Toshiba Corp | 半導体パッケ―ジ、半導体装置、及び半導体パッケ―ジの製造方法 |
JP2000286362A (ja) * | 1999-03-30 | 2000-10-13 | Mitsubishi Gas Chem Co Inc | 極薄bgaタイプ半導体プラスチックパッケージ用プリント配線板 |
US6362436B1 (en) * | 1999-02-15 | 2002-03-26 | Mitsubishi Gas Chemical Company, Inc. | Printed wiring board for semiconductor plastic package |
JP3690171B2 (ja) * | 1999-03-16 | 2005-08-31 | 株式会社日立製作所 | 複合材料とその製造方法及び用途 |
JP4423779B2 (ja) * | 1999-10-13 | 2010-03-03 | 味の素株式会社 | エポキシ樹脂組成物並びに該組成物を用いた接着フィルム及びプリプレグ、及びこれらを用いた多層プリント配線板及びその製造法 |
JP3414342B2 (ja) * | 1999-11-25 | 2003-06-09 | 日本電気株式会社 | 集積回路チップの実装構造および実装方法 |
WO2001042253A2 (en) * | 1999-12-13 | 2001-06-14 | The Dow Chemical Company | Phosphorus element-containing crosslinking agents and flame retardant phosphorus element-containing epoxy resin compositions prepared therewith |
US6537400B1 (en) * | 2000-03-06 | 2003-03-25 | Micron Technology, Inc. | Automated method of attaching flip chip devices to a substrate |
US6720080B2 (en) * | 2000-09-08 | 2004-04-13 | Jps Glass And Industrial Fabrics | Finish for glass fabrics used for reinforcing epoxy structures |
JP4626919B2 (ja) * | 2001-03-27 | 2011-02-09 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
EP1457515A4 (en) * | 2001-08-31 | 2004-11-24 | Sumitomo Bakelite Co | RESIN COMPOSITION, PREMIX, LAMINATED SHEET, AND SEMICONDUCTOR PACKAGE |
US6432748B1 (en) * | 2001-09-24 | 2002-08-13 | Phoenix Precision Technology Corp. | Substrate structure for semiconductor package and manufacturing method thereof |
US6906425B2 (en) * | 2002-03-05 | 2005-06-14 | Resolution Performance Products Llc | Attachment of surface mount devices to printed circuit boards using a thermoplastic adhesive |
KR20040060450A (ko) * | 2002-12-30 | 2004-07-06 | 삼성전자주식회사 | 반도체 패키지 실장방법 |
JP4325337B2 (ja) * | 2003-09-19 | 2009-09-02 | 日立化成工業株式会社 | 樹脂組成物、それを用いたプリプレグ、積層板及び多層プリント配線板 |
WO2005032227A1 (ja) * | 2003-09-29 | 2005-04-07 | Ibiden Co., Ltd. | プリント配線板用層間絶縁層、プリント配線板およびその製造方法 |
JP4232605B2 (ja) * | 2003-10-30 | 2009-03-04 | 住友電気工業株式会社 | 窒化物半導体基板の製造方法と窒化物半導体基板 |
US6897410B1 (en) * | 2003-11-07 | 2005-05-24 | Delaware Capital Formation, Inc. | Dual stage pre-heater |
WO2005085335A1 (ja) * | 2004-03-04 | 2005-09-15 | Hitachi Chemical Co., Ltd. | プリプレグ、金属箔張積層板及びこれらを使用した印刷回路板 |
JP2005340761A (ja) * | 2004-04-27 | 2005-12-08 | Seiko Epson Corp | 半導体装置の実装方法、回路基板、電気光学装置並びに電子機器 |
JP4271095B2 (ja) * | 2004-07-15 | 2009-06-03 | 東京エレクトロン株式会社 | 基板加熱装置及び基板加熱方法 |
US7560821B2 (en) * | 2005-03-24 | 2009-07-14 | Sumitomo Bakelite Company, Ltd | Area mount type semiconductor device, and die bonding resin composition and encapsulating resin composition used for the same |
JP4553765B2 (ja) * | 2005-03-25 | 2010-09-29 | Okiセミコンダクタ株式会社 | 半導体装置の製造方法 |
US20090301760A1 (en) * | 2005-06-16 | 2009-12-10 | Masato Shimamura | Method of Soldering a Module Board |
KR20070021817A (ko) * | 2005-08-19 | 2007-02-23 | 삼성전자주식회사 | 솔더링 장치 및 솔더링 방법 |
JP4553813B2 (ja) * | 2005-08-29 | 2010-09-29 | Okiセミコンダクタ株式会社 | 半導体装置の製造方法 |
KR101131138B1 (ko) * | 2006-01-04 | 2012-04-03 | 삼성전자주식회사 | 다양한 크기의 볼 패드를 갖는 배선기판과, 그를 갖는반도체 패키지 및 그를 이용한 적층 패키지 |
WO2008099940A1 (ja) * | 2007-02-16 | 2008-08-21 | Sumitomo Bakelite Co., Ltd. | 回路基板の製造方法、半導体製造装置、回路基板及び半導体装置 |
JP2008300678A (ja) * | 2007-05-31 | 2008-12-11 | Oki Electric Ind Co Ltd | 半導体素子の製造方法、及び半導体素子 |
US8073316B2 (en) * | 2008-01-31 | 2011-12-06 | Kabushiki Kaisha Toshiba | Oven for semiconductor wafer |
JP2010109032A (ja) * | 2008-10-29 | 2010-05-13 | Fujitsu Microelectronics Ltd | 半導体装置の製造方法 |
US8299393B2 (en) * | 2010-08-17 | 2012-10-30 | International Business Machines Corporation | Selective thermal conditioning components on a PCB |
-
2008
- 2008-02-08 WO PCT/JP2008/052586 patent/WO2008099940A1/ja active Application Filing
- 2008-02-08 CN CN2008800051824A patent/CN101611490B/zh not_active Expired - Fee Related
- 2008-02-08 KR KR1020097016928A patent/KR101409048B1/ko not_active IP Right Cessation
- 2008-02-08 US US12/526,631 patent/US8592256B2/en not_active Expired - Fee Related
- 2008-02-08 MY MYPI20093411 patent/MY153017A/en unknown
- 2008-02-15 TW TW097105483A patent/TWI424510B/zh not_active IP Right Cessation
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000091476A (ja) * | 1998-07-16 | 2000-03-31 | Nitto Denko Corp | 半導体装置 |
JP2003031926A (ja) * | 2001-07-19 | 2003-01-31 | Kyoei Sangyo Kk | プリント基板のそり矯正方法 |
JP2003283109A (ja) * | 2003-04-25 | 2003-10-03 | Matsushita Electric Ind Co Ltd | 回路形成基板の製造方法 |
WO2006054637A1 (ja) * | 2004-11-18 | 2006-05-26 | Matsushita Electric Industrial Co., Ltd. | 配線基板とその製造方法および半導体装置 |
Also Published As
Publication number | Publication date |
---|---|
WO2008099940A9 (ja) | 2011-06-03 |
TW200845250A (en) | 2008-11-16 |
KR101409048B1 (ko) | 2014-06-18 |
US8592256B2 (en) | 2013-11-26 |
MY153017A (en) | 2014-12-31 |
TWI424510B (zh) | 2014-01-21 |
CN101611490A (zh) | 2009-12-23 |
CN101611490B (zh) | 2011-07-27 |
KR20090109558A (ko) | 2009-10-20 |
US20100038762A1 (en) | 2010-02-18 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR101464008B1 (ko) | 반도체 패키지, 코어층 재료, 빌드업층 재료 및 시일링 수지 조성물 | |
JP5771987B2 (ja) | 多層回路基板、絶縁シート、および多層回路基板を用いた半導体パッケージ | |
JP5660272B2 (ja) | フリップチップ半導体パッケージ用の接続構造、ビルドアップ層材料、封止樹脂組成物および回路基板 | |
JP5533657B2 (ja) | 積層板、回路板および半導体装置 | |
US20110120754A1 (en) | Multilayer wiring board and semiconductor device | |
WO2008099940A1 (ja) | 回路基板の製造方法、半導体製造装置、回路基板及び半導体装置 | |
JP5056787B2 (ja) | 積層板、多層プリント配線板および半導体装置 | |
JP2008244189A (ja) | 回路基板および半導体装置 | |
JPWO2009051120A1 (ja) | 半導体素子搭載基板 | |
JP2011135034A (ja) | 半導体パッケージおよび半導体装置 | |
JP5256681B2 (ja) | 半導体装置、半導体装置用プリント配線板及び銅張積層板 | |
JP2009067852A (ja) | ガラス繊維織布入り絶縁樹脂シート、積層板、多層プリント配線板、及び半導体装置 | |
JP5448414B2 (ja) | 樹脂組成物、プリプレグ、積層板、多層プリント配線板、及び半導体装置 | |
JP4840303B2 (ja) | ガラス繊維織布入り絶縁樹脂シート、積層板、多層プリント配線板、及び半導体装置 | |
JP5292847B2 (ja) | 半導体素子搭載基板 | |
JP2009070891A (ja) | 半導体装置 | |
JP7098881B2 (ja) | 熱硬化性樹脂組成物、キャリア付樹脂膜、プリプレグ、プリント配線基板および半導体装置 | |
JP5188075B2 (ja) | 回路基板の製造方法及び半導体製造装置 | |
JP5105030B2 (ja) | 基板、半導体装置および基板の製造方法 | |
JP2010080609A (ja) | 半導体装置 | |
JP4385555B2 (ja) | インターポーザ、半導体パッケージおよびその製造方法 | |
JP2008251891A (ja) | 回路基板及びその半導体装置 | |
JP5211624B2 (ja) | 半導体装置の製造方法および半導体装置用プリント配線板の製造方法 | |
JP2009302554A (ja) | 金属箔付きプリプレグ、積層板およびインターポーザ |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WWE | Wipo information: entry into national phase |
Ref document number: 200880005182.4 Country of ref document: CN |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 08711416 Country of ref document: EP Kind code of ref document: A1 |
|
WWE | Wipo information: entry into national phase |
Ref document number: 12526631 Country of ref document: US |
|
WWE | Wipo information: entry into national phase |
Ref document number: 1020097016928 Country of ref document: KR |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 08711416 Country of ref document: EP Kind code of ref document: A1 |