Classifications

• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
  • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
  • G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
  • G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
  • G11C19/184—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET
  • G11C19/186—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET using only one transistor per capacitor, e.g. bucket brigade shift register
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
  • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
  • G11C19/282—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements with charge storage in a depletion layer, i.e. charge coupled devices [CCD]
  • G11C19/285—Peripheral circuits, e.g. for writing into the first stage; for reading-out of the last stage
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C5/00—Details of stores covered by group G11C11/00
  • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels

Definitions

• signals are represented as charge packets. These charge packets are stored, transferred from one storage location to another, and otherwise processed to carry out specific signal-processing functions. Charge packets are capable of representing analog quantities, with the charge-packet size in coulombs being proportional to the signal represented. Charge-domain operations such as charge-transfer are driven by 'clock' voltages, providing discrete-time processing. Thus, charge-domain circuits provide analog, discrete-time signal-processing capability.
• Charge-domain circuits are implemented as charge-coupled devices (CCDs), as Metal Oxide Semiconductor (MOS) bucket-brigade devices (BBDs), and as bipolar BBDs.
• CCDs charge-coupled devices
• MOS Metal Oxide Semiconductor
• BBDs Battery-brigade devices
• the present invention pertains primarily to MOS BBDs; it also has application to CCDs, in the area of charge-packet creation. Note that all circuits discussed below assume electrons as the signal-charge carriers, and use N-Channel Field Effect Transistors (NFETs) or N-channel CCDs for signal-charge processing. The identical circuits can be applied equally well using holes as charge carriers, by employing PFETs or P-channel CCDs and with reversed signal and control voltage polarities.
• NFETs N-Channel Field Effect Transistors
• FIG. 2 shows voltage waveforms associated with the circuit of Figure 1.
• Vx is at a high voltage 21 ; node 5 has been initialized to a relatively high voltage 23; and node 4 to a lower voltage 22.
• V T is the threshold of FET 2. Under these conditions FET 2 is biased below threshold, so no significant current flows through it.
• V 4 the voltage of node 4
• V 4 becomes equal to VG — VT, causing FET 2 to turn on.
• the resulting current flow through FET 2 limits further negative excursion OfV 4 .
• Vx reaches its lower value 24.
• Current continues to flow through FET 2 into capacitor 1, causing node 4 to charge in a positive direction.
• V 4 approaches V G - 25 VT, the current through FET 2 diminishes.
• V 4 settles towards VQ - VT at a continuously-diminishing rate, reaching voltage 26 at time t 4 .
• U Vx is returned to its original voltage. This positive-going transition is coupled through capacitor 1 to node 4, causing FET 2 to turn off altogether and ending the charge transfer.
• QT can also be expressed in terms of the voltage change across capacitor 1.
• Charge-transfer operation essentially similar to that described above is used in all conventional BBDs. Practical details, such as the means of establishing the described initial conditions, realistic clock waveforms, etc. are not pertinent to the present invention and will not be further described here.
• the same charge-transfer technique is also used to provide charge-packet input in many CCD signal- processing circuits. (Subsequent charge transfers in CCDs use a different principle, not described here.)
• Passive charge transfer The mode of charge-transfer described above will be termed "passive" charge transfer in the following discussion. This term refers to the fact that, during the charge-transfer process, the gate voltage V G applied to FET 2 is static, not actively controlled in response to the charge being transferred. (In practical BBDs, VQ is typically clocked rather than static, but it is not responsive to the charge being transferred.) This passive charge transfer process is subject to two important error sources.
• the first error source derives from the nature of the settling of node 4 during the t 3 -to-t 4 interval in Figure 2.
• node 4 is charging in a positive direction, reducing the gate-source voltage of FET 2.
• This decreasing gate-source voltage causes a decrease in current through the FET.
• This declining current in turn results in a declining rate of charging of node 4.
• This process is very non-linear in time, and also depends in a non-linear manner on the size of charge packet being transferred.
• the residual voltage 26 in Figure 2 (and Equation 6) depends non-linearly on Q T , resulting in an overall non-linear charge-transfer operation.
• the settling time of node 4 is unacceptably long for high-speed circuit operation. Passive charge- transfer is thus both slow and non-linear; in many applications these limitations degrade speed and accuracy unacceptably.
• the second error source arises due to the change ⁇ V 5 in FET drain voltage V5.
• this change is proportional to Q T - FETS exhibit a feedback effect, in which a variation in drain voltage causes, in effect, a variation in threshold voltage V x .
• the "final" voltage VQ-V T towards which V 4 settles, is not in fact a constant (as in the idealized discussion above) but a function of the charge being transferred.
• This effect is equivalent to a dependency of voltage 26 on the size of Q T : larger
• This effect amounts to a charge-transfer gain of less than 100%. It typically includes a small non-linear component as well, exacerbating the non-linearity issue discussed above.
• Embodiments of the present invention provide a charge-transfer circuit in which the effects of the two error sources described above are significantly reduced.
• the charge transfer method of the present invention is termed "boosted". The performance of a boosted charge-transfer circuit is sufficiently improved over that of the passive circuit that it makes high-speed, high-precision applications feasible.
• FIG. 1 is a simplified diagram of a charge transfer circuit.
• Figure 2 illustrates voltage waveforms associated with Figure 1.
• Figure 3 is a boosted charge transfer circuit according to aspects of the invention.
• Figure 4 illustrates voltage waveforms for the circuit of Figure 3.
• Figure 5 is a boosted charge transfer circuit incorporating a CMOS amplifier.
• Figure 6 is another boosted charge transfer circuit using an amplifier that reduces Miller capacitance.
• Figure 7 is a boosted charge transfer circuit that uses an NFET as a common gate amplifier.
• Figure 8 is a boosted charge transfer circuit that uses resistor elements to dampen the circuit response.
• Figure 9 is a boosted charge transfer circuit that provides greater control over start and end of current flow.
• Figure 10 is a boosted charge transfer circuit using an FET that controls power consumption.
• Figure 11 is a boosted charge transfer circuit that provides a voltage-to- charge sample-and-hold function.
• Figure 12 illustrates voltage waveforms associated with the circuit of Figure
• Figure 13 illustrates voltage waveforms associated with the circuit of Figure
• Figure 14A and 14B are a circuit diagram and cross-sectional device structure diagram of a boosted charge transfer circuit which provides input charge to a CCD.
• the present invention provides a charge-transfer circuit in which the effects of the two error sources described above are significantly reduced.
• the charge transfer method of the present invention is termed "boosted".
• the performance of a boosted charge- transfer circuit is sufficiently improved over that of the passive circuit that it makes high-speed, high-precision applications feasible.
• This boosted charge-transfer technique can be understood with the aid of Figures 3 and 4, which illustrate the basic features of its operation.
• the elements of Figure 3 are the same as similarly-identified elements of Figure 1, except for the addition of amplifier 36 and its reference voltage VR, and the omission of voltage V G .
• Capacitor 31 in Figure 3 corresponds to capacitor 1 in Figure 1, node 34 to node 4, etc.
• the added amplifier 36 is the unique feature of this invention; it has moderate voltage gain (typically 10-100) and very high speed.
• FIG. 4 The operating waveforms of this circuit are shown in Figure 4, using the same naming conventions employed in Figure 2 (e.g., the voltage of node 34 is called V 3 4, etc.).
• Initial conditions in Figure 4 are similar to those in Figure 2.
• Input voltage Vx starts at a high value, 41.
• Drain node 35 is initialized to a high voltage 43.
• Source node 34 is initialized to a lower voltage 42, which is more positive than VR.
• V 34 > V R amplifier 36 drives its output, node 37, to a low voltage 48.
• Node 37 is also connected to the gate of FET 32, so a low value of V 37 assures that FET 32 is initially turned off, and no current flows through it.
• V34 follows Vx in a negative direction.
• V34 becomes more negative than V R , causing amplifier 36 to drive its output node 37 to a high voltage.
• This high voltage turns on FET 32; the resulting current through FET 32 limits the negative excursion of node 34.
• Amplifier 36 then operates, by feedback via FET 32, to maintain V 34 slightly below V R . This balance persists until time t 3 when Vx reaches its lower value 44.
• the current flowing through FET 32 then charges node 34 positively until t4, when V 34 approaches V R .
• V R5 the reference voltage for amplifier 36.
• the value OfV 34 at the end of charge transfer (time t$) is voltage 46.
• any difference between voltage 46 and V R represents an error in the transferred charge.
• the key difference between the boosted and passive charge transfer lies in the improved precision and speed with which V 34 approaches V R .
• Equation 12 Comparing Equation 12 to Equation 10 shows that the rate at which VQ S settles is increased by the gain of amplifier 36 compared to the passive case. The time required after t 3 for settling to any given level of precision is similarly reduced. The non-linearity of the final voltage 46 is similarly reduced by approximately the same factor relative to final voltage 26 in Figure 2.
• FIG 8. This circuit is identical to the basic boosted charge-transfer circuit of Figure 3, with similarly-identified elements, except that the resistors 88 and 89 are added. When appropriately sized, the sum of these resistors adds a zero which partially cancels the second pole mentioned above, thus providing an adequately damped overall response. If the combined resistance is made larger than necessary, it reduces the speed of the charge-transfer operation, reducing the benefit of the boosted circuit. With practical circuit parameters, a significant range exists for an appropriate choice of resistor values. Either resistor 88 or 89 or a combination can be used to achieve the needed effect.
• FIG. 9 This circuit is identical to the basic circuit of Figure 3, with similarly- identified elements, except for the addition of NFET 98 which is controlled by a logic voltage signal V O FF- When V O FF is high, FET 98 is turned on, and drives node 97 to near zero volts.
• node 144 is connected to the input terminal 149 of CCD 148.
• the initial condition for the potential well under gate 143 is zero charge.
• the operation and timing of the circuit of Figure 14A are identical to those of Figure 4, except for the aforementioned difference in the means of collection of transferred charge.
• the transferred charge Q T has is accumulated under gate 143, and gate 142 is driven off by amplifier 146.
• Q T can be transferred along CCD 148 by appropriate clocking of ⁇ i and ⁇ 2 using well-known CCD methods which are not part of this invention.

Landscapes

• Engineering & Computer Science (AREA)
• Power Engineering (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Amplifiers (AREA)
• Networks Using Active Elements (AREA)
• Solid State Image Pick-Up Elements (AREA)

Priority Applications (4)

Applications Claiming Priority (2)

Publications (2)

Family

ID=38802067

Family Applications (1)

Country Status (7)

Cited By (1)

Families Citing this family (12)

Family Cites Families (37)

• 2007
  • 2007-05-30 TW TW96119259A patent/TWI474597B/zh active
  • 2007-05-30 US US11/807,914 patent/US8385498B2/en active Active
  • 2007-05-31 JP JP2009513290A patent/JP5798715B2/ja active Active
  • 2007-05-31 CN CN2007800198716A patent/CN101454843B/zh not_active Expired - Fee Related
  • 2007-05-31 KR KR1020147020912A patent/KR101517745B1/ko not_active Expired - Fee Related
  • 2007-05-31 WO PCT/US2007/012906 patent/WO2007143074A2/en not_active Ceased
  • 2007-05-31 KR KR1020087029051A patent/KR20090031675A/ko not_active Ceased
  • 2007-05-31 EP EP07795582.1A patent/EP2038893B1/en not_active Not-in-force

Also Published As

Similar Documents

Legal Events