Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
  • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
  • H01L21/568—Temporary substrate used as encapsulation process aid
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
  • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/93—Batch processes
  • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
  • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/0001—Technical content checked by a classifier
  • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

• This invention relates in general to integrated circuit (IC) die encapsulation.
• Carriers are utilized for supporting IC die during encapsulation processes in the manufacture of packaged integrated circuits.
• IC die are attached to a carrier with tape or other types of attaching structures.
• a mold is placed around the IC die where encapsulate is then applied to the die with the tape defining the bottom surface of the mold outside of the die.
• the carrier is removed from the encapsulated structure by heating the tape to soften the adhesives of the tape. The tape is then removed from the encapsulated structure.
• the adhesive of the tape may be degraded by applying Ultra Violet (UN) radiation to the tape.
• UN Ultra Violet
• the UN degradable adhesive on the tape may not function adequately after being subjected to the curing temperatures of the encapsulation processes.
• Figure 1 is a cross sectional view of one embodiment of a carrier according to the present invention.
• Figure 2 is a cross sectional view of one embodiment of a carrier with adhesive tape applied on top thereof during a stage in the manufacture of a packaged integrated circuit according to the present invention.
• Figure 3 is a cross sectional view of one embodiment of a carrier, adhesive tape, and an encapsulant mold during another stage in the manufacture of a packaged integrated circuit according to the present invention.
• Figure 4 is a cross sectional view of one embodiment of a carrier, adhesive tape, an encapsulant mold, and IC die during another stage in the manufacture of a packaged integrated circuit according to the present invention.
• Figure 5 is a cross sectional view of one embodiment of a carrier, adhesive tape, an encapsulant mold, and an encapsulated structure during another stage in the manufacture of a packaged integrated circuit according to the present invention.
• Figure .6 is a cross sectional view of one embodiment of a carrier, adhesive tape, an encapsulant mold, and an encapsulated structure during another stage in the manufacture of a packaged integrated circuit according to the present invention.
• Figure 7 is a cross sectional view of one embodiment of adhesive tape, an encapsulant mold, and an encapsulated structure after the removal of the carrier during another stage in the manufacture of a packaged integrated circuit according to the present invention.
• Figure 8 is a cross sectional view of one embodiment of an encapsulant mold and an encapsulated structure after the removal of tape during another stage in the manufacture of a packaged integrated circuit according to the present invention.
• Figure 9 is a cross sectional view of one embodiment of an encapsulated structure after the removal of the encapsulant mold during another stage in the manufacture of a packaged integrated circuit according to the present invention.
• the use of the same reference symbols in different drawings indicates identical items unless otherwise noted.
• Figures 1-9 show one embodiment of various stages of a process for encapsulating an IC die with the use of a porous carrier to allow for solvent to pass through the carrier to reduce the adhesive strength of an adhesive structure for the removal of a carrier from an encapsulated structure.
• FIG 1 is a cross sectional view of carrier 101 prior to the application of a tape for an encapsulating process.
• Carrier 101 is porous in that has pores that allow a solvent to pass through from one side of the carrier to another side.
• carrier 101 is made of a composite material of aluminum oxide embedded in a glass matrix.
• carrier 101 may be made with other material such as e.g. metal, ceramics, glass, plastics, polymer or a combination thereof, where such materials are made to have a continuous open porosity.
• the carrier is made of a material that can withstand temperatures of the encapsulation process (e.g. 150 C).
• carrier 101 has pores with a .2 micron diameter pore size and a coefficient of thermal expansion (CTE) of 8 parts per million (ppm).
• the pore size of carrier 101 may range from .02 microns up to 30 microns. In other embodiments, the pore size may be bigger. However, in some embodiments, a larger pore size may affect the smoothness of the surface of the carrier beyond a smoothness level that is desired. In one embodiment, the desired smoothness of the surface of the carrier is dependent upon the type of adhesive structure utilized for attachment of IC die. With some embodiments, the adhesive structure may be applied as a planar layer thereby allowing for a carrier to have larger pore sizes.
• a carrier with pores of a smaller pore size may be used. However, with a smaller pore size, a reduced amount of solvent passes thought the carrier. With some embodiments, the time needed for reducing the strength of the adhesive structure is dependent upon the amount of solvent passing through the carrier. Accordingly, with some embodiments, carriers with an open continuous porosity of a .02 micron diameter pour size or greater are utilized depending upon the amount of solvent desired to be passed through. Also, utilizing a carrier with pores of a smaller size may affect the reusability of the carrier in that the small pores may become clogged.
• carrier 101 may have CTE of other values.
• the CTE of carrier 101 is less than the CTE of an encapsulant used for encapsulating the IC die.
• the encapsulant has a CTE ranging from .5- 20 ppm.
• tape 203 is applied to the top surface of carrier 101.
• carrier 101 Prior to applying tape 203, carrier 101 is cleaned e.g. by baking and scrubbing.
• tape 203 is a two sided adhesive tape.
• the die side (the top side in the view of Figure 2) of tape 203 has a silicone adhesive material with a thickness of 50 microns, but may be of other thicknesses (e.g. 12-100 microns) and/or of other adhesive materials (e.g. acrylic or organic) in other embodiments..
• the carrier side (the bottom side in the view of Figure 2) of tape 203 has a silicone adhesive material with a thickness of 75 microns.
• the carrier side adhesive material may be of other types of adhesive material (e.g. acrylic or organic) and/or may be of other thicknesses.
• the thickness of the carrier side adhesive material should be thick enough to fill in pores or other voids in the top side of carrier 101 so as to "planarize" the top surface of carrier 101.
• the maximum thickness of the carrier side adhesive material is limited by the ability to release the carrier from tape 203 with solvent.
• the thickness of the carrier side adhesive material may range from 12-100 microns, but may be of other thicknesses in other embodiments.
• the tape has an adhesive material on the die side that is greater than 30 microns and an adhesive material on the carrier side that is greater than 50 microns.
• the silicone adhesive may have additives to increase or decrease the silicone strength.
• the die side and carrier side adhesive materials are separated by a tape carrier (e.g. polyester or polyamide).
• Figure 3 shows a cross sectional view of carrier 101 after an encapsulant mold is placed on top of tape 203.
• Mold 305 has an opening 307 for exposing the middle portion of tape 203.
• integrated circuit die 403 and 405 are placed on tape 203 in opening 307 in predefined locations.
• multiple die are placed in an array configuration (e.g. 4 x 6, 6 x 6, or 8 x 8) on tape 203.
• the die are placed on tape 203 by a standard pick and place method, but may be placed on tape 203 by other methods.
• die 403 and 405 include integrated circuits built on a semiconductor wafer which was subsequently singulated into separate die.
• die 403 and 405 have a flip chip configuration and are placed active side down on tape 203, wherein the bond pads (not show) are located on the bottom sides of die 403 and 405 relative to the view shown in Figure 4.
• an encapsulant material is dispensed (e.g. with syringe and robotic needle) into opening 307 to form an encapsulant 503 that encapsulates die 403 and 405 in an encapsulated structure 505.
• encapsulant 503 may be formed by other encapsulating processes such as e.g. screen print, extrusion coating, transfer mold, ejection mold, glob top, or other encapsulating processes.
• the bottom portion of carrier 101 is placed in a solvent bath 603. Solvent from solvent bath 603 is absorbed up through the carrier via a capillary action where it contacts the carrier side adhesive material of tape 203. The solvent breaks down the adhesive strength of the carrier side adhesive material of tape 203. In one embodiment where the solvent is acetone and the adhesive material is a silicone adhesive, the solvent softens the adhesive property of the silicone adhesive. In one embodiment, the bottom portion of carrier 101 is placed in bath 603 for about 5 minutes before carrier 101 separates from tape 203. In other embodiments, a greater portion of the carrier may be submerged in bath 603. In some embodiments, the entire carrier/mold/encapsulated structure may be submerged in bath 603.
• the carrier removal process may be performed at room temperature, or in some embodiments, at least at temperatures below the transition temperature (T g ) of the encapsulant.
• T g transition temperature
• the carrier may be removed from the encapsulated structure 505 without causing die 403 and 405 to drift within encapsulated structure 505.
• the transition temperature of encapsulant 503 is about 140 C.
• other types of encapsulant material may have a T g ranging from 90 C to 200 C.
• Figure 7 shows a cross sectional view of mold 305, encapsulated structure 505, and tape 203 after carrier 101 has been removed.
• tape 203 is pulled from encapsulated structure 505 and mold 305.
• mold 305 is removed from encapsulated structure 505.
• structure 505 is subject to further buildup processes (e.g. dielectric and metal interconnect processing) on the active side of the die to form interconnect structures (not shown).
• Encapsulated structure 505 is then singulated into a plurality of packaged ICs.
• each packaged IC includes one IC die (e.g. 403).
• each packaged IC may include multiple die (e.g. in stacked or side by side configurations).
• package ICs of other embodiments may include stand alone devices (e.g. transistors, filters, capacitors, amplifiers) that are encapsulated in the encapsulant (e.g. 503). These additional items by be placed on tape 203 prior to encapsulation.
• entire embedded systems e.g. multichip modules, RF systems, or other wireless or information processing systems may be included in a packaged IC.
• a package substrate may be located between tape 203 and the IC die (e.g. 405) with, in some embodiments, the package substrate defining the bottom portion of the encapsulant.
• the IC die are mounted to the packaged substrate, and then the package substrate is placed in opening 307.
• the package substrate is first placed on tape 203 in opening 307 and then the IC die are placed on the substrate.
• the die may be placed on the packaged substrate active side up wherein wire bonds are attached to bond pads on the active side and bond pads on the package substrate prior to encapsulation.
• tape 203 may be used in place of tape 203.
• two layers of tape may be used for attaching an integrated circuit die.
• One layer of tape would have adhesive material on two sides and the other layer would have adhesive on only one side.
• photo resist or other types of adhesives may be used as an adhesive structure for attaching the die to the carrier.
• a first layer of photo resist (not shown) would be applied to the top surface of carrier 101.
• a second layer of photo resist is applied on the cured layer of photo resist.
• the IC die are then placed on the second layer of photo resist. Afterwards, the second layer of photo resist is cured.
• a dry film photo resist or other adhesive may be used where only one layer is used for attaching the die to the carrier.
• An example of one such adhesive is RISTON as sold byDUPONT.
• acetone or N- Methyl 2-Pyn-olidone may be used as a solvent that dissolves the photo resist or adhesive layer(s) (e.g. as when the bottom portion of carrier 101 is placed in a solvent bath).
• NMP N- Methyl 2-Pyn-olidone
• other types of adhesive structures may be used including, e.g., other types of adhesive materials or other types of photo resist materials.
• the adhesive structure is able to withstand curing temperatures for curing the encapsulant.
• a method in one aspect of the invention, includes providing a porous carrier, providing an adhesive structure overlying the porous carrier, and placing a first integrated circuit die over the adhesive structure. The method also includes encapsulating the first integrated circuit die to form an encapsulated structure and separating the porous carrier from the encapsulated structure.
• a method in another aspect of the invention, includes providing a porous carrier, adhering an adhesive structure to the porous carrier, and placing at least one integrated circuit die over the adhesive structure. The method also includes encapsulating the at least one integrated circuit die to form an encapsulated structure and removing the porous carrier from the encapsulated structure. The removing includes using a solvent that is passed through the porous carrier to reduce adhesive strength between the adhesive structure and the porous carrier.
• a method in another aspect of the invention, includes providing a reusable porous carrier including pores with a pore size diameter of at least 0.02 microns, adhering an adhesive structure to the reusable porous carrier, and placing a plurality of integrated circuit die in an array configuration over the adhesive structure.
• the method also includes encapsulating the plurality of integrated circuit die to form an encapsulated structure and separating the reusable porous carrier from the encapsulated structure. The separating comprises using a solvent that is passed through the porous carrier to reduce adhesive strength between the adhesive structure and the reusable porous carrier.

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• Engineering & Computer Science (AREA)
• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Manufacturing & Machinery (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
• Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
• Wire Bonding (AREA)

Priority Applications (3)

Applications Claiming Priority (2)

Related Parent Applications (1)

Related Child Applications (1)

Publications (2)

Family

ID=34827103

Family Applications (1)

Country Status (6)

Cited By (1)

Families Citing this family (87)

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• 2004
  • 2004-02-09 US US10/774,977 patent/US7015075B2/en not_active Expired - Fee Related
• 2005
  • 2005-01-12 JP JP2006553132A patent/JP4555835B2/ja not_active Expired - Fee Related
  • 2005-01-12 CN CN2005800043966A patent/CN1918702B/zh not_active Expired - Fee Related
  • 2005-01-12 WO PCT/US2005/001529 patent/WO2005076794A2/en not_active Ceased
  • 2005-01-12 EP EP05705847A patent/EP1721332A2/en not_active Withdrawn
  • 2005-01-25 TW TW094102210A patent/TWI389221B/zh not_active IP Right Cessation

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