WO2005053013A1 - Flip chip bonding method for enhancing the performance of connection in flip chip packaging process and layered metal architecture of substrate for stud bump - Google Patents

Flip chip bonding method for enhancing the performance of connection in flip chip packaging process and layered metal architecture of substrate for stud bump Download PDF

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Publication number
WO2005053013A1
WO2005053013A1 PCT/KR2004/001956 KR2004001956W WO2005053013A1 WO 2005053013 A1 WO2005053013 A1 WO 2005053013A1 KR 2004001956 W KR2004001956 W KR 2004001956W WO 2005053013 A1 WO2005053013 A1 WO 2005053013A1
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Prior art keywords
bump
chip
substrate
bonding
ultrasonic wave
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English (en)
French (fr)
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Ja-Uk Koo
Hyoung-Chan Kim
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
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    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/012—Manufacture or treatment of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills
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    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01221—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using local deposition
    • H10W72/01225—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using local deposition in solid form, e.g. by using a powder or by stud bumping
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    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07231—Techniques
    • H10W72/07232—Compression bonding, e.g. thermocompression bonding
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    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
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    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
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    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5524—Materials of bond wires comprising metals or metalloids, e.g. silver comprising aluminium [Al]
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    • H10W72/00—Interconnections or connectors in packages
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    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5525—Materials of bond wires comprising metals or metalloids, e.g. silver comprising copper [Cu]
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/853—On the same surface
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    • H10W72/853—On the same surface
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
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    • H10W72/941—Dispositions of bond pads
    • H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding
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    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
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    • H10W80/00—Direct bonding of chips, wafers or substrates
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    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
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    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
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    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
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    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Definitions

  • This invention relates to a semiconductor packaging technology, and more particularly to a flip chip bonding method for enhancing a bonding performance between a chip and a substrate by forming a bump on the chip, the substrate, or both the chip and the substrate and for bonding the chip and the substrate using a thermosonic process, and a layer-built structure of the substrate for the same.
  • a wire bonding, a TAP bonding, a flip chip bonding, and the like have been disclosed as methods for bonding a semiconductor chip to a substrate. Meanwhile, the size of an electronic product is gradually minimized, and its performance is more enhanced. The number of a bonding pad for input and output is increased, while the size of the chip used in the electronic product is gradually smaller. Thus, the conventional wire bonding process for bonding the semiconductor chip on the substrate arrives at limit. Instead of the wire bonding method, a flip chip bonding method, which is not only superior in view of integrity or performance, but also has no wire connection process and has the light weight and short length, has been widely used.
  • the flip chip bonding method is a technology for forming a bump on a bonding pad of a chip and directly bonding the bonding pad of the chip on a lead pad of a substrate without connecting the bonding pad of the chip to the lead pad of the substrate using a metal wire.
  • Fig. 1 shows a view for explaining a conventional flip chip bonding.
  • a flip chip bonding has a structure that, after forming a stud bump 13 on a bonding pad 12 of a chip 11 cut away from a wafer 10 and flipping the chip 11, the bonding pad 12 of the chip 11 is directly bonded to a lead pad 22 of a substrate 21.
  • the flip chip bonding is classified into a package typed flip chip bonding for bonding a flip chip in a ceramic package and a on-board typed flip chip bonding for directly bonding a flip chip on a main board.
  • Fig. 2 is a view showing an example of a package typed flip chip bonding
  • Fig. 3 is a view showing an example of a on-board typed flip chip bonding.
  • a chip 11 is bonded to a ceramic package 22 by a flip chip bonding method. At this time, the package is mounted on a main board 25. The ceramic package 22 is sealed by a package cover 26.
  • the part that connected by bumps 53 is molded by resin and the like. Meanwhile, in case of bonding a chip on a substrate as described above, a bonding strength or a production yield depends on the kind of a basic substance of the board 21.
  • a surface treatment is performed to enhance an adhesive property.
  • the surface treatment is conventionally performed by plating with Ni or Au.
  • a substance 21-1 of the substrate is FPCB, FR4, FR5, ceramic, or glass. That is, after coating with a Cu layer 21-2 on the basic substance 21-1, a pattern is formed. Then, a Ni layer 21-3 and an Au layer 21-4 are formed through an electroplating process to perform the surface treatment for enhancing an adhesion property.
  • the invention has been made in view of the above problems, and it is an object of the invention to provide a flip chip bonding method for obtaining high reliability and productivity by speeding up process rate and for enhancing an bonding performance. Further, it is another object of the invention to provide a metal-layered architecture of a substrate for flip chip bonding for maintaining a bonding strength and enhancing a production yield regardless of a kind of basic substance by adding a buffer layer with a hard metal to the substrate.
  • a flip chip bonding method comprising the steps of: performing pretreatment of a wafer having chips, dicing it, and obtaining the pretreated individual chip; performing pretreatment of a substrate; aligning the pads of the pretreated chip with the pads of the pretreated substrate, and bonding the chip and the substrate together by applying an ultrasonic wave and heat using a collet and simultaneously applying pressure; and performing posttreatment for filling or molding resin after bonding.
  • the bump of the substrate may have the same size as the bump of the chip or any one of the bump of the substrate and the bump of the chip may have a larger size than the other of them.
  • the circuit part of the substrate may be plated with Sn.
  • the flip chip bonding may be performed without damaging the pad of the chip, even though the wafer having a weak pad is used.
  • a metal layer-built structure comprising: a substrate which is formed with a copper thin film pattern on a basic substance; a hard metal layer which is formed by plating a metal having a high hardness on the substrate; and a conductive metal layer which is fo ⁇ ned by plating a metal having a high conductivity on the hard metal layer.
  • Figs. 1 to 3 are views for explaining a conventional flip chip bonding
  • Fig. 4 is a view showing a layer-built structure of a conventional substrate for flip chip bonding
  • Fig. 5 is a flow diagram showing a flip chip packaging process for enhancing a bonding property according to the invention
  • Fig. 6 is a view showing a process for forming a plated bump according to the invention
  • Figs. 7 to 9 are views showing a method for giving an annealing effect to enhance an adhesion property of a plated bump according to the invention
  • FIG. 10 is a view showing a process for forming a doping bump on a substrate according to the invention
  • Fig. 11 is a view showing a process for forming a stud bump according to the invention
  • Figs. 12 to 16 are views showing the examples of a stud bump according to the invention
  • Fig. 17 is a view showing a process for forming a wedge bump according to the invention
  • Figs. 18 to 20 are views showing examples of a wedge bump according to the invention
  • Fig. 21 is a view showing an example of a tape adhesion process shown in Fig.
  • Fig. 22 is a view showing an example of a wafer cutting process shown in Fig.
  • Fig. 23 is a view showing an example of a flip chip bonding device developed according to the invention
  • Figs. 24 to 27 are views showing examples of a design of collet developed according to the invention
  • Fig. 28 is a view showing a coating method for minimizing the loss of an ultrasonic energy of a collet according to the invention
  • Figs. 29 to 38 are views showing examples of a structure for bonding a substrate and a chip according to the invention
  • Figs. 39 to 42 are views showing examples of a bonding structure according to the relative size of a stud bump or a wedge bump and examples of applying ACF, ACP, NCF or NCP after forming the bump
  • FIG. 43 to 46 are views showing example of a chip stack method using a flip chip bonding process
  • Fig. 47 is a view showing an example of a bonding posttreatment process shown in Fig. 5
  • Fig. 48 is a view showing a first embodiment of a metal layer-built structure of a substrate for a flip chip bonding according to the invention
  • Fig. 49 is a view showing a second embodiment of a metal layer-built structure of a substrate for a flip chip bonding according to the invention.
  • Fig. 5 is a flow diagram for showing a flip chip packaging process according to the invention.
  • a flip chip packaging method of the invention as shown in Fig.
  • the bonding pretreatment step S2 for a wafer 10 may be any one selected from processes consisting of forming a stud bump made of Au, Al, or Cu on an Aluminum pad 12 of the wafer 10, forming a wedge bump with the same metal by wedge bonding, forming by evaporating a Au plated bump, Al, or Ag on an aluminum pad 12, and forming a first plated bump and then forming a stud bump or a wedge bump, which is made of Au, Ag, Al, or Cu, on the first plated bump.
  • the bonding pretreatment step S9 for a substrate 21 may be any one selected from processes consisting of forming a stud bump or a wedge bump, which is made of Au, Cu, or Al, on an aluminum pad 22 of the substrate 21, forming an Au plated bump on an aluminum pad 22, and applying Anisotropic Conductive Film (ACF), Anisotropic Conductive Paste (ACP), Non Conductive Film (NCF), and Non Conductive Paste (NCP) on the substrate.
  • the substrate 21 to which a semiconductor chip 11 is bonded may be any one selected from the group consisting of ceramic, PCB, and FPCB.
  • [Formation of plated bump] A method for a plated bump 32 on the wafer 10 or the substrate according to the invention, as shown in Fig.
  • the plated bump 32 formed on the wafer 10 or the substrate 21 is made of Au particles.
  • an annealing effect may be applied to make a size of Au particles 36 large.
  • Fig. 3b, 3c and 3d an annealing effect may be applied to make a size of Au particles 36 large.
  • FIG. 7 is a view showing a status for giving an annealing effect on the formed plated bump by applying a heat
  • Fig. 8 shows an example which gives an annealing effect by applying laser beam 37 to the plated bump 32
  • Fig. 9 shows an example which gives an amiealing effect by processing the plated bump 32 with a corning capillary 38.
  • Fig. 10 shows a method for forming a doping bump on a substrate according to the invention.
  • a doping bump 53 may be formed by a doping method for partially projecting particles 46 of Au, Ag, or Cu on the substrate or the wafer and growing the particles.
  • a pad 22 of the substrate that is plated with Au, Cu, Al, or Sn may be used.
  • the stud bump 53 is formed on the pad 12 or 22 using a capillary 52 into which a gold wire 51 is inserted. Specifically, while applying arc to the gold wire 51 and melting the gold wire 51, the melted gold within the capillary 52 is contacted on a pad of the wafer 10 or the substrate 21. Then, the melted gold is adhered to the pad by applying an ultrasonic wave. Then, the capillary 52 is moved a little in the direction of a transverse axis to flatten a projected portion. Then, the capillary 52 is moved upward.
  • the stud bump 53 formed by the above method may have various shapes. That is, as shown if Fig. 12, the stud bump 53 may have a body portion 53-1 and a long neck portion 53-2 formed in the center of the body portion 53-1. Further, as shown in Fig. 13, the stud bump 53 may have a short neck portion 53-2 formed on a body portion 53-1. Further, as shown in Fig. 14, the stud bump 53 may have a convex shape without having projection in the center of a body portion 53-1. Further, as shown in Fig. 15, the stud bump 53 may have a body portion 53-1 having a trapezoid shape without having the neck portion 53-2 in the center of the body portion.
  • the stud bump 53 may have a very thick body portion 53-1 without having the neck portion 53-2. Since a noxious flux is not used in the stud bump forming process, the stud bump forming process is eco-environmental and simple compared to a soldering method.
  • the wedge bump 63 is formed on the pad 12 or 22 using a wedge bonding tool 65 into which a gold wire 61 or a high conductive wire that is made of Al, Cu, or Ag is inserted. Specifically, after inserting the gold wire 61, the aluminum wire 61-2 or the copper wire 61-3 into the wedge bonding tool 65, the melted gold within the wedge bonding tool 65 is contacted on a pad of the wafer 10 or the substrate 21. Then, the melted gold is adhered to the pad by applying ultrasonic wave.
  • the wedge bonding tool 65 is moved a little in the direction of a transverse axis to adhere each wire. Then, each wire is immediately cut. As a result, the wedge bump 63 is formed on the wafer 10 or the substrate 21.
  • the wedge bump 63 formed by the above method has various shapes. That is,
  • Figs. 18 to 20 show the wedge bumps 63 having two projections, one projection and no projection, respectively.
  • the shape of the wedge bump 63 depends on the shapes of various wedge tools.
  • a chip of a wafer status is individually separated by a cutter. According to a sectional side elevation shown in Fig. 22, even if a blade 81 of a cutter 80 completely cuts a wafer 10 and partially cuts a tape 72, a chip 11 is not individually separated by the tape 72.
  • Fig. 23 is a schematic view showing a bonding device upon bonding a flip chip according to the invention.
  • the boding device comprises a collet 95 for holding a chip 11, and a block 100 for supporting a substrate 21.
  • the collet 95 holding the chip 11 may vibrate in the direction of a X axis
  • the block 100 supporting the substrate 21 may vibrate in the direction of a Y axis.
  • the collet 95 may vibrate in the direction of the Y axis
  • the block 100 may vibrate in the direction of the X axis.
  • the collet 95 and the block 100 may transfer the ultrasonic waves while intersecting in the direction of the same axis.
  • Each of the above transmission methods may be used together with a conventional method that transfers the ultrasonic wave only from the collet 95.
  • the ultrasonic waves may be transferred to the substrate 21 as well as the chip 11, a flip chip bonding process is completed in a short time, and an adhesion strength between the chip 11 and the substrate 21 is increased. As a result, a production yield is enhanced.
  • the collet 95 transferring the ultrasonic energy to the chip, as shown in Figs. 24 and 25, is formed with a vacuum hole 96 in the center thereof, it serves to hold the chip 11 using a vacuum pressure and to transfer the ultrasonic energy.
  • the above collet 95 is classified into a polish type that polishes a contact surface as shown in Fig. 26, and a matt type that roughly treat a contact surface as shown in Fig. 27.
  • the collet is manufactured using a material for enduring the ultrasonic wave, such as Zr, Ti, ceramic, stainless alloy, titanium alloy, for example, TiW or TiC, and the like. Further, the collet 95, as shown in Fig.
  • a bonding structure of the invention for flip chip bonding when a chip 11 is bonded on a pretreated substrate 21 has various structures as described in the following Table 1 according to the method for forming a bump on a pad 22 of the substrate and a pad 12 of the chip. [Table 1 ]
  • Example 1 Fig. 29 is a view showing the process for a flip chip bonding between a substrate that is fomied with a stud bump and a chip that is fo ⁇ ned with a plated bump using a thermosonic method according to the invention.
  • an aluminum bonding pad 12 of a chip 11 is fonned with a plated bump 32c that is made of Au, Al, or Ni coated with Au.
  • a lead pad 22 of a substrate 21 is foraied with a stud bump 53s that is made of Au or Cu.
  • the flip chip bonding process S5 After the chip 11 and the substrate 21 are closely contacted, heat is applied to the substrate 21, and an ultrasonic wave of 70KHz or more is applied to the chip 11 through a collet 95. Simultaneously, pressure is applied to the substrate 21. As a result, the plated bump 32c of the chip and the stud bump 53s of the substrate are bonded by energy generated from the heat, the ultrasonic wave and the pressure.
  • the collet 95 that is made of Zr, Ti, ceramic, stainless alloy, TiW alloy, TiC, and the like, is manufactured to have a little smaller size than that of each chip.
  • Example 2 Fig. 30 is a view showing the process for a flip chip bonding between a bare substrate and a chip that is formed with a plated bump using a thermosonic method according to the invention.
  • an aluminum bonding pad 12 of a chip 11 is fo ⁇ ned with a plated bump 32c that is made of Au, Al, or Ni coated with Au.
  • a lead pad 22 of a substrate 21 is bared of any bump.
  • the flip chip bonding process S5 after the chip 11 and the substrate 21 are closely contacted, heat is applied to the substrate 21, and an ultrasonic wave is applied to the chip 11 through a collet 95. Simultaneously, pressure is applied to the substrate 21.
  • the plated bump 32c of the chip and the lead pad 22 of the substrate are bonded by energy generated from the heat, the ultrasonic wave and the pressure.
  • Example 3 Fig. 31 is a view showing the process for a flip chip bonding between a substrate that is foraied with a stud bump and a chip that is fo ⁇ ned with a plated bump and a stud bump fo ⁇ ned on the plated bump using a thennosonic method according to the invention.
  • an aluminum bonding pad 12 of a chip 11 is formed with a plated bump 32c that is made of Au, Al, Ag, Cu or Ni coated with Au.
  • a stud bump 53c is again fo ⁇ ned on the plated bump 32c.
  • a lead pad 22 of a substrate 21 is formed with a stud bump 53s.
  • Example 4 Fig. 32 is a view showing the process for a flip chip bonding between a base substrate and a chip that is formed with a plated bump and a stud bump fo ⁇ ned on the plated bump using a thermosonic method according to the invention. Refe ⁇ ing to Fig. 32, an aluminum bonding pad 12 of a chip 11 is foraied with a plated bump 32c that is made of Au, Al, or Ni coated with Au. A stud bump 53c is again foraied on the plated bump 32c. A lead pad 22 of a substrate 21 is bared of any bump.
  • Example 5 Fig. 33 is a view showing the process for a flip chip bonding between a substrate that is foraied with a stud bump 53s and a chip that is formed with a stud bump 53c using a thermosonic method according to the invention.
  • an aluminum bonding pad 12 of a chip 11 is formed with a stud bump 53c that is made of Au or Cu.
  • a lead pad 22 of a substrate 21 is fo ⁇ ned with a stud bump 53s that is made of Au or Cu.
  • the flip chip bonding process S5 after the chip 11 and the substrate 21 are closely contacted, heat is applied to the substrate 21, and an ultrasonic wave is applied to the chip 11 through a collet 95. Simultaneously, pressure is applied to the substrate 21.
  • the stud bump 53c of the chip and the stud bump 53s of the substrate are bonded by energy generated from the heat, the ultrasonic wave and the pressure.
  • Example 6 Fig. 34 is a view showing the process for a flip chip bonding between a substrate that is formed with a stud bump 53s and a chip that is formed with a basic aluminum pad using a thennosonic method according to the invention.
  • an aluminum bonding pad 12 of a chip 11 is bared of any bump.
  • a lead pad 22 of a substrate 21 is formed with a stud bump 53s that is made of Au or Cu.
  • the flip chip bonding process S5 after the chip 11 and the substrate 21 are closely contacted, heat is applied to the substrate 21, and an ultrasonic wave is applied to the chip 11 through a collet 95. Simultaneously, pressure is applied to the substrate 21.
  • the bonding pad 12 of the chip and the stud bump 53s of the substrate are bonded by energy generated from the heat, the ultrasonic wave and the pressure.
  • Example 7 Fig. 35 is a view showing the process for a flip chip bonding between a base substrate and a chip that is formed with a stud bump 53c using a thermosonic method according to the invention.
  • an aluminum bonding pad 12 of a chip 11 is foraied with a stud bump 53c that is made of Au or Cu.
  • a lead pad 22 of a substrate 21 is bared of any bump.
  • the flip chip bonding process S5 after the chip 11 and the substrate 21 are closely contacted, heat is applied to the substrate 21, and an ultrasonic wave is applied to the chip 11 through a collet 95. Simultaneously, pressure is applied to the substrate 21.
  • the stud bump 53c of the chip and the lead pad 22 of the substrate 21 are bonded by energy generated from the heat, the ultrasonic wave and the pressure.
  • Example 8 Fig. 36 is a view showing the process for a flip chip bonding between a base substrate on which an adhesive (for example, ACF, ACP, NCF or NCP) is applied and a chip that is foraied with a stud bump 53c using a thermosonic method according to the invention.
  • an adhesive for example, ACF, ACP, NCF or NCP
  • an aluminum bonding pad 12 of a chip 11 is formed with a stud bump 53c that is made of Au or Cu.
  • a lead pad 22 of a substrate 21 is bared of any bump.
  • An adhesive 102 that is selected from a group of Anisotropic Conductive Film (ACF), Anisotropic Conductive Paste (ACP), Non Conductive Film (NCF), and
  • Non Conductive Paste is applied on the lead pad 22 of the substrate 21.
  • NCP Non Conductive Paste
  • the flip chip bonding process S5 after the chip 11 and the substrate 21 are closely contacted, heat is applied to the substrate 21, and an ultrasonic wave is applied to the chip 11 through a collet 95. Simultaneously, pressure is applied to the substrate 21. As a result, the stud bump 53c of the chip and the lead pad 22 of the substrate 21 are bonded by energy generated from the heat, the ultrasonic wave and the pressure.
  • Fig. 37 is a view showing the process for a flip chip bonding between a base substrate on which an adhesive (ACF, ACP, NCF or NCP) is applied and a chip that is formed with a plated bump using a thermosonic method according to the invention.
  • an aluminum bonding pad 12 of a chip 11 is fo ⁇ ned with a plated bump 32c that is made of Au, Al, or Ni coated with Au.
  • a lead pad 22 of a substrate 21 is bared of any bump.
  • An adhesive 102 that is selected from a group consisting of ACF, ACP, NCF, and NCP is applied on the lead pad 22 of the substrate 21.
  • the bump formed on the substrate 21 or the chip 11 according to the invention comprises a plated bump that is made of Au or Al, a plated bump that is made of Ni coated with Au, a stud bump that is made of Au, a stud bump that is made of Cu and the like.
  • the substrate 21 may be a conventional PCB or FPCB. Further, the substrate 21 may be a substrate on which Sn is plated, h order to perform a flip chip process for having better adhesion force, ACF, ACP, NCF or NCP is applied on the substrate.
  • a chip 11 may have an aluminum pad 12 that is foraied with a plated bump 32c made of Au, Al or Ni coated with Au. Further, the chip 11 may have only the aluminum bonding pad 12 without forming the plated bump 32c.
  • a substrate 21 may be formed with a doping bump 43.
  • the chip 11 and the substrate 21 are bonded using an ultrasonic energy. From the foregoing, according to a bonding means in the flip chip bonding process S5 of the invention, heat is applied to the substrate 21, ultrasonic wave is applied to the chip 11 through a collet 95, and pressure is applied to the substrate 21. As a result, the chip 11 and the substrate 21 are bonded by energy generated from the heat, the ultrasonic wave and the pressure.
  • the invention has an advantage in that, since the present invention adopts a method for applying the ultrasonic wave as well as a thermocompression method without using only a conventional the ⁇ nocompression method, a process time may be reduced compared to the conventional art. Further, in the case of using a substrate on which Sn is plated, or a substrate on which ACF, ACP, NCF or NCP is applied, a superior adhesion force may be obtained.
  • Figs. 39 to 42 shows the examples of the bonding structure according to a relative size of a stud bump or a wedge bump and the example of applying ACF, ACP, NCF or NCP after forming a bump.
  • a bump 53c or 63c of a chip 11 is larger than a bump 53s or 63s of a substrate 21.
  • a bump 53c or 63c has the same size as a bump 53s or 63s of a substrate 21.
  • a bump 53s or 63s of a substrate is larger than a bump 53c or 63c of a chip.
  • the bump 53c or 63c of the chip and the bump 53s or 63s of the substrate may be bonded while having the same size and kind or differing the size and kind thereof.
  • an anisotropic conductive adhesive 102 or a nonconductive adhesive 102 such as ACF, ACP, NCF, NCP, and the like is applied, and then a chip 11 and the substrate 21 are immediately bonded.
  • the process for filling resin may be removed.
  • the process for applying the anisotropic conductive adhesive 102 or the nonconductive adhesive 102 such as ACF, ACP, NCF, NCP, and the like may be performed around the bump which is formed on the substrate 21.
  • a stud bump 53 or a wedge bump 63 is formed on a pad 12 of an upper chip 11 or a pad 12 of a lower chip 11.
  • the pad 12 of the lower chip has at least two rows.
  • the pads of two chips 11 are positioned to face each other.
  • Heat is applied to the lower chip 11, and ultrasonic wave and force are applied through a collet 95 to the upper chip 11.
  • the upper chip 11 and the lower chip 11 are bonded to form a stacked chip.
  • This stacked chip shows better performance than one chip.
  • Fig. 44 shows a view for manufacturing a stacked chip according to the invention by forming a stud bump 53 or a wedge bump 63 on an upper chip 11, forming a stud bump 53 or a wedge bump 63 on a lower chip 11, facing them each other, and applying ultrasonic wave and force using a tool.
  • Fig. 45 shows a view for manufacturing a stacked chip according to the invention by forming a plated bump 32 on an upper chip 11, forming a stud bump 53 or a wedge bump 63 on a lower chip 11 , and bonding them.
  • Fig. 46 shows a view for manufacturing a stacked chip according to the invention by foraiing a plated bump 32 on an upper chip 11, and bonding this chip 11 to a lower chip 11.
  • the bump adopted in the chip-to-chip method as describe above is made by foraiing a wire with a metal having a good conductivity, such as Au, Ag, Al, and Cu.
  • a resin is filled in a bonding space to protect a chip.
  • Fig. 47 shows an example of foraiing a protection wall 132, forming bumps 53c, 53s and 63 on a chip 11 and a substrate 21, respectively, and forming a molding 134 on them.
  • the protection wall 132 is formed around the chip and then a flip chip bonding is performed in a posttreatment for under-fill and side sealing, an epoxy resin component is prevented from penetrating into a gap between the bump and the substrate.
  • the protection wall 132 may be made of NCP, NCF, ACF, ACP, epoxy, or a molding compound. After performing a flip chip bonding process, it is prefe ⁇ ed that a curing process for hardening the protection wall 132 which is made of a soft material is added.
  • a layer-built structure of a substrate for bonding comprises a substrate which is formed with a copper thin film pattern on a basic substance, a hard metal layer which is fo ⁇ ned by plating a metal having a high hardness on the substrate, a conductive metal layer which is formed by plating a metal having a high conductivity on the hard metal layer.
  • a bonding strength is maintained and a production yield is enhanced i ⁇ espective of a kind of the basic substance.
  • Fig. 48 shows an example of a metal layer-built structure of a substrate for a stud bump according to the invention. Refe ⁇ ing to Fig.
  • a substrate 21 according to the invention is formed with a copper thin film pattern on a basic substance thereof.
  • the basic substance of the substrate is made of FPCB, FR4, FR5, ceramic or glass.
  • a first metal layer 141 and a second metal layer 142 are formed on the substrate 21 by a plating method.
  • the first metal layer 141 serves as a buffer layer for cutting off the effect according to the kind of the substance of the substrate. It is fo ⁇ ned by plating Pd alloy, Pd-Ni or Ni-Pd to have 3 ⁇ m or more in thickness.
  • the second metal layer 142 serves as a part for directly connecting to a stud bump or the like in a bonding process.
  • Fig. 49 shows a layer-built structure having three layers as another embodiment of a metal layer-built structure of a substrate for each bump according to the invention. Referring to Fig. 49, a substrate 21 according to the invention is fonned with a copper thin film pattern on a basic substance thereof.
  • the basic substance of the substrate is made of FPCB, FR4, FR5, ceramic or glass.
  • a first metal layer 141, a second metal layer 142 and a third metal layer 143 are formed on the substrate 21 by a plating method.
  • the first metal layer 151 is formed by plating Ni or Ni alloy to have 3 ⁇ m or more in thicl ⁇ iess.
  • the second metal layer 152 serves as a buffer layer for cutting off the effect according to the kind of the substance of the substrate. It is formed by plating AU alloy to have 0.1 ⁇ m or more in thickness.
  • the third metal layer 153 serves as a part for directly connecting to each bump or the like in a bonding process.
  • a bonding property of a chip may be greatly enhanced by fonning a stud bump or a plated bump on the chip, forming a bump on a substrate, and directly bonding the bumps. That is, the invention may enhance the bonding property by directly connecting the plated bump, a stud bump, a wedge bump or a doping bump using a collet and forming a new intermetallic area after bonding.
  • the invention provides a flip chip bonding device that applies an ultrasonic energy to only the chip or both the chip and the substrate for the flip chip bonding. Further, according to the invention, since a metal having high hardness is plated on a substrate as a buffer layer for cutting off the effect according to the kind of a basic substance of the substrate, a bonding strength can be maintained and a production yield can be enhanced. While a preferred embodiment of the invention has been described, it is to be understood that modifications and variations will be apparent to those skilled in the art without departing from the spirit of the invention. The scope of the invention, therefore, is to be determined solely by the following claims.

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US20050110163A1 (en) 2005-05-26
US7115446B2 (en) 2006-10-03
TWI255019B (en) 2006-05-11
KR20050050155A (ko) 2005-05-30
JP2005159356A (ja) 2005-06-16
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SG128468A1 (en) 2007-01-30
TW200520175A (en) 2005-06-16

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