WO2003001596A1 - Dispositif electronique et son procede de fabrication - Google Patents

Dispositif electronique et son procede de fabrication Download PDF

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Publication number
WO2003001596A1
WO2003001596A1 PCT/JP2002/002187 JP0202187W WO03001596A1 WO 2003001596 A1 WO2003001596 A1 WO 2003001596A1 JP 0202187 W JP0202187 W JP 0202187W WO 03001596 A1 WO03001596 A1 WO 03001596A1
Authority
WO
WIPO (PCT)
Prior art keywords
electronic device
main surface
electronic component
manufacturing
electrode pads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2002/002187
Other languages
English (en)
French (fr)
Japanese (ja)
Inventor
Kazuyuki Taguchi
Norihiko Sugita
Hideki Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
Hitachi Ltd
Original Assignee
Renesas Technology Corp
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp, Hitachi Ltd filed Critical Renesas Technology Corp
Priority to US10/481,463 priority Critical patent/US7026188B2/en
Publication of WO2003001596A1 publication Critical patent/WO2003001596A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/012—Manufacture or treatment of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10734—Ball grid array [BGA]; Bump grid array
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/047—Soldering with different solders, e.g. two different solders on two sides of the PCB
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/321—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by conductive adhesives
    • H05K3/323—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by conductive adhesives by applying an anisotropic conductive adhesive layer over an array of pads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/346—Solder materials or compositions specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01221—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using local deposition
    • H10W72/01225—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using local deposition in solid form, e.g. by using a powder or by stud bumping
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/321—Structures or relative sizes of die-attach connectors
    • H10W72/325—Die-attach connectors having a filler embedded in a matrix
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/351—Materials of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/351—Materials of die-attach connectors
    • H10W72/352—Materials of die-attach connectors comprising metals or metalloids, e.g. solders
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/351—Materials of die-attach connectors
    • H10W72/353—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics
    • H10W72/354—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics comprising polymers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/853—On the same surface
    • H10W72/856—Bump connectors and die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/944—Dispositions of multiple bond pads
    • H10W72/9445—Top-view layouts, e.g. mirror arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to an electronic device and a manufacturing technology thereof, and more particularly to a technology effective when applied to an electronic device employing a flip-chip mounting technology.
  • MCM Multi Chip Module
  • MCM Multi Chip Module
  • MCM multiple semiconductor chips with built-in integrated circuits are mounted on a wiring board on which wiring patterns are formed, and one integrated function is built.
  • MCM there is an active movement to adopt flip-chip mounting technology in order to increase the data transfer speed and reduce the size.
  • Flip chip mounting technology is a technology for mounting a semiconductor chip (flip chip) having protruding electrodes on one main surface on a wiring board.
  • CCB Controlled Collapse Bonding
  • ACF Anagonal Conductive Film
  • the CCB mounting method uses a semiconductor chip that has solder bumps made of a metal material of, for example, lead (Pb) -tin (Sn) as a protruding electrode on one main surface, and wiring is performed by melting the solder bumps.
  • a semiconductor chip is mounted on a substrate.
  • Electronic components mounted on a wiring board by melting solder bumps as in the CCB mounting method include, for example, a semiconductor chip (semiconductor chip for solder bump connection) and a BGA (Ball G) packaged with a semiconductor chip.
  • semiconductor devices such as a rid array (CSP) and a CSP (Chip Size Package or Chip Scale Package) type.
  • CSP rid array
  • CSP Chip Size Package or Chip Scale Package
  • a semiconductor chip is mounted on one main surface of a wiring board called an ink poser, and a projection is formed on the other main surface (rear surface) opposite to the one main surface of the wiring substrate.
  • the configuration is such that solder bumps are arranged as electrodes.
  • a new package structure CSP type semiconductor device (wafer / repel CSP type) is manufactured by manufacturing technology that integrates the wafer process (pre-process) and the package process (post-process). Semiconductor devices) have also been commercialized.
  • This wafer-level CSP type semiconductor device is manufactured by applying a package process to each semiconductor chip divided from a semiconductor wafer because the package has almost the same plane size as the semiconductor chip. Compared with devices (chip-level CSP type semiconductor devices), miniaturization and cost reduction can be achieved.
  • Wafer-level CSP type semiconductor devices mainly consist of a semiconductor chip layer, a redistribution layer (pad rearrangement layer) formed on one main surface of the semiconductor chip layer, and protrusions on the redistribution layer. And a solder bump arranged as a shape electrode.
  • the semiconductor chip layer is mainly formed so as to cover the semiconductor substrate, a multilayer wiring layer in which an insulating layer and a wiring layer are stacked in a plurality of stages on one main surface of the semiconductor substrate, and the multilayer wiring layer. And a protective surface film.
  • the uppermost wiring layer of the multilayer wiring layers An electrode pad is formed, and a bonding opening for exposing the electrode pad is formed in the surface protective film.
  • the rewiring layer is a layer for forming an electrode pad having a wider arrangement pitch than an electrode pad of the semiconductor chip layer.
  • the electrode pads of the redistribution layer are electrically connected to the corresponding electrode pads of the semiconductor chip layer, and are the same as the connection portions arranged in the region of the wiring board on which the wafer-level CSP type semiconductor device is mounted.
  • the arrangement pitch is arranged.
  • the solder bumps are arranged on the electrode pads of the redistribution layer and are electrically and mechanically connected.
  • a wafer-level CSP type semiconductor device is also defined as a kind of semiconductor chip.
  • the ACF mounting method uses a semiconductor chip that has, for example, gold (Au) as a bump on one main surface as a protruding electrode, and uses an anisotropic conductive resin as an adhesive resin between the wiring board and the semiconductor chip.
  • the semiconductor chip is mounted on the wiring board by pressing the semiconductor chip while heating it with the resin film (ACF) interposed.
  • An anisotropic conductive resin film is obtained by processing an insulating resin in which a large number of conductive particles are dispersed and mixed into a sheet shape.
  • the insulating resin for example, an epoxy-based thermosetting resin is used. Used.
  • a stud made of Au melts the tip of the Au wire to form a ball, and then heats the ball to an electrode pad arranged on the main surface of the semiconductor chip while applying ultrasonic vibration. It is formed by crimping and then cutting a portion of the ball from the Au wire.
  • the ACF mounting method is described in, for example, Japanese Patent Application Laid-Open No. 4-340501 and Japanese Patent Application Laid-Open No. 5-175280.
  • NCF mounting that uses an insulating resin film (NCF: Non Conductive Film) with no conductive particles mixed in is used as the bonding resin.
  • the present inventor studied MCM in which two types of semiconductor chips (semiconductor bump connection semiconductor chip and stud bump connection semiconductor chip) having different types of bumps were mixedly mounted on the same wiring board. I found a problem.
  • the solder bump connection semiconductor chip is mounted by melting the solder bumps based on the reflow method.Therefore, before mounting the solder bump connection semiconductor chip, the ACF mounting method must be used.
  • a semiconductor chip for connecting bumps is mounted, heat generated when mounting the semiconductor chip for connecting solder bumps is applied to the anisotropic conductive resin. Since the anisotropic conductive resin is mainly made of epoxy-based thermosetting insulating resin, it has high performance after thermosetting. When heated, the bond in the resin is broken and cracks are more likely to occur. According to the study of the present inventor, cracks were remarkably generated by applying heat higher than the curing temperature of the resin.
  • connection between the connection part of the wiring board and the bump is made by the heat shrinkage force of the anisotropic conductive resin interposed between the wiring board and the semiconductor chip for connecting the bump (from the heating state to the normal temperature state). Since it is maintained by the shrinkage force generated when returning, the thermosetting shrinkage force (shrinkage force generated when the thermosetting resin is cured), etc., if a crack occurs in the anisotropic conductive resin, the shrinkage force decreases and the connection This may cause a failure and reduce the reliability of the MCM. Therefore, when the semiconductor chip for solder bump connection and the semiconductor chip for solder bump connection mounted by the ACF mounting method are mixedly mounted, the anisotropic conductive resin should not be exposed to heat above the curing temperature as much as possible. is necessary.
  • the arrangement pitch of the electrode pads to which the bumps are connected is smaller than the electrode pad of the solder bump connecting semiconductor chip. Since the planar size of the electrode pad of the chip is determined by the arrangement pitch of the electrode pads, it becomes smaller as the arrangement pitch of the electrode pads becomes narrower. Further, since the size of the bump is determined by the plane size of the electrode pad, the size of the bump becomes smaller as the plane size of the electrode pad becomes smaller. That is, a pad with a narrow electrode pad arrangement pitch In the semiconductor chip for bump connection, since the solder bump is small, a connection failure due to a displacement during mounting is likely to occur.
  • the stud bumps are formed of Pb—Sn based solder, such as gold or aluminum, or a metal having a higher melting point than other solders. Therefore, when mounting the semiconductor chip on the wiring board, the solder bump cannot be melted. This is because if a semiconductor chip is subjected to a heat treatment that melts a metal with a high melting point, such as gold or aluminum, the electrical characteristics of the semiconductor chip change significantly before and after the heat treatment, and the desired characteristics cannot be obtained. This causes a problem. Therefore, when a semiconductor chip having gold or aluminum snow bumps is picked up and mounted using solder (joining material), only the touched solder is melted and mounted. In the case of mounting by the above method, the position correction force obtained by the surface tension of the molten solder is weaker than the CCB method of melting and mounting the solder bumps.
  • the semiconductor chip having the stud bump (the semiconductor chip for connecting the stump bump) has a reduced diameter of the stud bump so as to be formed on the small pad; and Since a strong correction force cannot be obtained by melting and mounting only the welcome solder, there is a problem that connection failures are likely to occur due to displacement during mounting.
  • An object of the present invention is to provide a technique capable of improving the reliability of an electronic device.
  • a wiring board having a first region and a second region which are different from each other on one main surface; a first electronic component having a plurality of first protruding electrodes on one main surface; Preparing a second electronic component having a plurality of second protruding electrodes having a high melting point;
  • the wiring substrate is formed.
  • the step of mounting the second electronic component is performed after the step of mounting the first electronic component.
  • the bonding resin is a thermosetting insulating resin
  • the plurality of first protruding electrodes are solder bumps
  • the plurality of second protruding electrodes are solid bumps.
  • the arrangement pitch of the plurality of second protrusion electrodes is smaller than the arrangement pitch of the plurality of first protrusion electrodes.
  • the first and second electronic components are semiconductor chips having a built-in circuit.
  • the first electronic component includes: a semiconductor substrate; a plurality of semiconductor elements formed on one main surface of the semiconductor substrate; and a plurality of first electrode pads formed on one main surface of the semiconductor substrate.
  • a plurality of second electrode pads formed in a layer higher than the plurality of first electrode pads and electrically connected to the plurality of first electrode pads, respectively;
  • the second electronic component includes: a semiconductor substrate; a plurality of semiconductor elements formed on one surface of the semiconductor substrate; a plurality of electrode pads formed on one main surface of the semiconductor substrate; And a plurality of said second protruding electrodes respectively connected to said electrode pads.
  • the first electronic component is a semiconductor device in which a semiconductor chip having a built-in circuit is packaged, and the second electronic component is a semiconductor chip having a built-in circuit.
  • a wiring board having a first region and a second region different from each other;
  • 5D port mounted in the first region with a plurality of first protruding electrodes interposed therebetween;
  • a second electronic component mounted in the second region with a plurality of second protruding electrodes having a melting point higher than that of the first protruding electrodes.
  • the first protruding electrodes are solder bumps, and the second protruding electrodes are solid bumps.
  • the arrangement pitch of the plurality of second protrusion electrodes is smaller than the arrangement pitch of the plurality of first protrusion electrodes.
  • the first and second electronic components are semiconductor chips having a built-in circuit.
  • the first electronic component includes: a semiconductor substrate; a plurality of semiconductor elements formed on one main surface of the semiconductor substrate; and a plurality of first electrode pads formed on one main surface of the semiconductor substrate.
  • a plurality of second electrode pads formed in a layer above the plurality of first electrode pads and electrically connected to the plurality of first electrode pads, respectively;
  • a plurality of second electrode pads arranged in an array bit wider than the pad; and a plurality of second electrode pads.
  • a semiconductor chip having the plurality of first protruding electrodes respectively connected thereto,
  • the second electronic component includes: a semiconductor substrate; a plurality of semiconductor elements formed on one main surface of the semiconductor substrate; a plurality of electrode pads formed on one main surface of the semiconductor substrate; A semiconductor chip having the plurality of second protruding electrodes respectively connected to a plurality of electrode pads.
  • the first electronic component is a semiconductor device in which a semiconductor chip having a built-in circuit is packaged, and the second electronic component is a semiconductor chip having a built-in circuit.
  • a wiring board having a first region and a second region different from each other on one main surface, a plurality of first connection portions being arranged in the first region, and a plurality of second connection portions being arranged in the second region;
  • a first electronic component having a plurality of first protruding electrodes on one main surface; and a second electronic component having a plurality of second protruding electrodes having a higher melting point than the first protruding electrode on one main surface.
  • a bonding material having a higher melting point than the first protruding electrode and a lower melting point than the second protruding electrode is melted to electrically connect the plurality of second connecting portions and the plurality of second protruding electrodes, respectively.
  • the plurality of first protruding electrodes are solder bumps, and the plurality of second protruding electrodes are solid bumps.
  • the arrangement pitch of the plurality of second protrusion electrodes is smaller than the arrangement pitch of the plurality of first protrusion electrodes.
  • the first and second electronic components are semiconductor chips having a built-in circuit.
  • the first electronic component includes: a semiconductor substrate; a plurality of semiconductor elements formed on one main surface of the semiconductor substrate; and a plurality of first electrode pads formed on one main surface of the semiconductor substrate.
  • a plurality of second electrode pads formed in a layer above the plurality of first electrode pads and electrically connected to the plurality of first electrode pads, respectively;
  • a semiconductor chip having a plurality of second electrode pads arranged at an arrangement pitch wider than the pads and the plurality of first protruding electrodes respectively connected to the plurality of second electrode pads.
  • the second electronic component includes: a semiconductor substrate; a plurality of semiconductor elements formed on one main surface of the semiconductor substrate; a plurality of electrode pads formed on one main surface of the semiconductor substrate; A semiconductor chip having the plurality of second protruding electrodes respectively connected to a plurality of electrode pads.
  • the first electronic component is a semiconductor device in which a semiconductor chip having a built-in circuit is packaged, and the second electronic component is a semiconductor chip having a built-in circuit.
  • a wiring board having a first region and a second region different from each other, a plurality of first connection portions being arranged in the first region, and a plurality of second connection portions being arranged in the second region;
  • a first electronic component having a plurality of first protruding electrodes on one main surface
  • a second electronic component having a plurality of second protruding electrodes having a melting point higher than the first protruding electrodes on one main surface
  • the plurality of first protruding electrodes are respectively connected to the plurality of first connecting portions, the plurality of second protruding electrodes have a higher melting point than the first protruding electrodes, and the second protruding electrodes
  • Each of the plurality of second connection portions is connected to each other via a bonding material having a lower melting point.
  • FIG. 1 is a plan view of an MCM that is Embodiment 1 of the present invention.
  • FIG. 2 is a bottom view of the MCM shown in FIG.
  • FIG. 3 is a cross-sectional view of the main part of the MCM shown in Fig. 1 ((a) is a cross-sectional view along the line A-A in Fig. 1, (b) is a cross-sectional view along the line BB in Fig. 1 ).
  • FIG. 4 is an enlarged sectional view of a part of FIG. 3 (a).
  • FIG. 5 is an enlarged sectional view of a part of FIG. 3 (b).
  • FIG. 6 is a plan view of the semiconductor chip (semiconductor bump connection semiconductor chip) shown in FIG.
  • FIG. 7 is a plan view of the semiconductor chip (semiconductor chip for solder bump connection) shown in FIG.
  • FIG. 8 is a sectional view of a principal part of the semiconductor chip shown in FIG.
  • FIG. 9 is a plan view of a multi-cavity wiring board used for manufacturing the MCM shown in FIG.
  • FIG. 10 is a cross-sectional view of a main part for explaining the manufacture of the MCM shown in FIG. 1 ((a) is a cross-sectional view taken along a line AA in FIG. 1, (b) is a cross-sectional view of FIG. (Cross-sectional view at the position along the line B-B in the figure).
  • FIG. 11 is a cross-sectional view of a main part for explaining the manufacture of the MCM shown in Fig. 1 ((a) is a cross-sectional view taken along a line AA in Fig. 1, and (b) is a cross-sectional view.
  • FIG. 1 is a cross-sectional view taken along a line B—] 3).
  • Fig. 12 is a cross-sectional view of a main part for explaining the manufacture of the MCM shown in Fig. 1 ((a) is a cross-sectional view taken along the line AA in Fig. 1, and (b) is FIG. 1B is a cross-sectional view taken along a line B).
  • FIG. 13 is a cross-sectional view of a main part for explaining the manufacture of the MCM shown in FIG. 1 ((a) is a cross-sectional view taken along a line AA in FIG. 1, and (b) is a cross-sectional view.
  • B in Figure 1 1 is a cross-sectional view taken along the line B).
  • Fig. 14 is a cross-sectional view of a main part for explaining the manufacture of the MCM shown in Fig. 1 ((a) is a cross-sectional view taken along a line AA in Fig. 1, and (b) is a cross-sectional view. 2 is a cross-sectional view taken along the line B-B in FIG. 1).
  • FIG. 15 is a cross-sectional view of a main part of the MCM according to the second embodiment of the present invention.
  • FIG. 16 is a plan view of an MCM which is Embodiment 3 of the present invention.
  • Fig. 17 is a cross-sectional view of the main part of the MCM shown in Fig. 16 ((a) is a cross-sectional view taken along the line C-C in Fig. 16, (b) is a line D-D in Fig. 16 FIG.
  • FIG. 18 is a cross-sectional view of a main part for explaining the manufacture of the MCM shown in FIG. 16 ((a) is a cross-sectional view taken along a line C-C in FIG. 16, and (b) is a cross-sectional view.
  • Fig. 16 is a sectional view taken along the line D-D in Fig. 16).
  • Fig. 19 is a cross-sectional view of the essential parts for explaining the manufacture of the MCM shown in Fig. 16 ((a) is a cross-sectional view taken along the line CC in Fig. 16, and (b) is a cross-sectional view. Fig. 16 is a sectional view taken along the line D-D in Fig. 16).
  • Fig. 20 is a cross-sectional view of a main part for explaining the manufacture of the MCM shown in Fig. 16 ((a) is a cross-sectional view taken along the line C-C in Fig. 16, (b) Fig. 16 is a sectional view taken along the line D-D in Fig. 16).
  • Fig. 21 is a cross-sectional view of a main part for explaining the manufacture of the MCM shown in Fig. 16 ((a) is a cross-sectional view taken along the line C-C in Fig. 16, and (b) is a cross-sectional view.
  • Fig. 16 is a sectional view taken along the line D-D in Fig. 16).
  • Fig. 22 is a cross-sectional view of a main part for explaining the manufacture of the MCM shown in Fig. 16 ((a) is a cross-sectional view taken along the line C-C in Fig. 16, (b) Fig. 16 is a sectional view taken along the line D-D in Fig. 16).
  • Fig. 23 is a cross-sectional view of a main part for explaining the manufacture of the MCM shown in Fig. 16
  • (a) is a cross-sectional view taken along the line C-C in Fig. 16,
  • (b) Is the first sixteen It is a cross-sectional view taken along the line D-D in the figure.
  • FIG. 24 is a cross-sectional view of a main part for explaining the manufacture of the MCM according to the fourth embodiment of the present invention ((a) is a cross-sectional view at the same position as line C-C in FIG. 16, (b) ) Is a cross-sectional view at the same position as line DD in FIG. 16).
  • FIG. 25 is a cross-sectional view of a main part for explaining the manufacture of the MCM according to the fourth embodiment of the present invention ((a) is a cross-sectional view at the same position as line C—C in FIG. 16, (b) ) Is a cross-sectional view at the same position as line DD in FIG. 16).
  • FIG. 24 is a cross-sectional view of a main part for explaining the manufacture of the MCM according to the fourth embodiment of the present invention ((a) is a cross-sectional view at the same position as line C—C in FIG. 16, (b) ) Is a cross-sectional view at the same position as line DD
  • FIG. 26 is a cross-sectional view of a main part for explaining the manufacture of the MCM according to the fifth embodiment of the present invention ((a) is a cross-sectional view at the same position as line C—C in FIG. b) is a cross-sectional view at the same position as the line DD in FIG. 16).
  • FIG. 27 is a cross-sectional view of a main part for explaining the manufacture of the MCM according to the fifth embodiment of the present invention ((a) is a cross-sectional view at the same position as line C—C in FIG. ) Is a cross-sectional view of FIG. 16 at the same position as line D).
  • FIG. 1 is a plan view of an MCM (electronic device) according to a first embodiment of the present invention
  • FIG. 2 is a bottom view of the MCM shown in FIG. 1,
  • FIG. 3 is a cross-sectional view of the main part of the MCM shown in Fig. 1 ((a) is a cross-sectional view taken along line A-A in Fig. 1, (b) is a cross-sectional view taken along line B-B in Fig. 1 )
  • FIG. 4 is an enlarged sectional view of a part of FIG. 3 (a)
  • FIG. 5 is an enlarged sectional view of a part of FIG. 3 (b);
  • FIG. 6 is a plan view of the semiconductor chip (semiconductor chip for connecting a bump) shown in FIG.
  • FIG. 7 is a plan view of the semiconductor chip (semiconductor chip for solder bump connection) shown in FIG.
  • FIG. 8 is a sectional view of a main part of the semiconductor chip (semiconductor chip for solder bump connection) shown in FIG.
  • the MCM-1A of the present embodiment has one semiconductor chip (semiconductor chip for connecting a stud bump) on one main surface 2X side of the wiring board 2 as an electronic component. 3 and two semiconductor chips (semiconductor chips for solder bump connection) 4 are mounted, and one main surface 2 of the wiring board 2 is connected to the other main surface (rear surface) 2 X. A plurality of external connection terminals are provided on the Y side. The configuration is such that solder bumps 11 are arranged.
  • the semiconductor chip 3 incorporates, for example, a control circuit
  • the semiconductor chip 4 incorporates, for example, a 64 megabit Synchronic Dynamic Dynamic Access Memory (SDRAM) as a storage circuit.
  • SDRAM Synchronic Dynamic Dynamic Access Memory
  • the wiring board 2 mainly includes a rigid board (core board) 20, and flexible layers 21, 21 B formed by a build-up method on both sides of the rigid board 20 facing each other, Protective films 24 and 26 are formed so as to cover the flexible layers 21 and 21B.
  • the rigid substrate 20 and the flexible layers 21 and 21B have, for example, a multilayer wiring structure.
  • Each insulating layer of the rigid substrate 20 is formed of, for example, a highly conductive resin substrate in which glass fiber is impregnated with an epoxy or polyimide resin, and each of the insulating layers of the flexible layers 21 and 21B is formed.
  • each wiring layer of the rigid substrate 20 and the flexible layers 21 and 21B is formed of a metal film made of, for example, copper (Cu). protection
  • the films 24 and 26 are formed of, for example, a polyimide resin.
  • the protective film 24 is formed mainly for the purpose of protecting the wiring formed on the uppermost wiring layer of the flexible layer 21, and has an adhesive force to the semiconductor chip 3 with an adhesive resin during mounting. It controls the spread of solder wetting during mounting on the semiconductor chip 4.
  • the protective film 26 is formed mainly for the purpose of protecting the wiring formed on the uppermost wiring layer of the flexible layer 21B, and controls the spread of solder wetting when forming the solder bump 11 with respect to the solder bump 11. .
  • the planar shapes of the semiconductor chip 3 and the semiconductor chip 4 are rectangular.
  • the semiconductor chip 3 is formed in a square shape of, for example, 6.8 mm ⁇ 6.8 mm
  • the semiconductor chip 4 is formed in a rectangular shape of, for example, 5.99 ⁇ 8.7 mm.
  • the semiconductor chip 3 and the semiconductor chip 4 are formed with a thickness of, for example, about 0.4 mm.
  • the semiconductor chip 3 includes, but is not limited to, a semiconductor substrate, a plurality of semiconductor elements formed on one main surface of the semiconductor substrate, an insulating layer and wiring on one main surface of the semiconductor substrate. It has a multilayer wiring layer in which each of the layers is stacked in a plurality of stages, and a surface protective film (final protective film) formed so as to cover the multilayer wiring layer.
  • the semiconductor substrate is formed of, for example, single crystal silicon
  • the insulating layer is formed of, for example, a silicon oxide film
  • the wiring layer is formed of, for example, a metal film such as aluminum (A 1) or an aluminum alloy.
  • the surface protective film is formed of, for example, an insulating film such as silicon oxide or silicon nitride and an organic insulating film.
  • a plurality of electrode pads 5 are formed on one main surface 3X of the semiconductor chip 3 and one main surface 3X of the other main surfaces (back surface) facing each other.
  • the plurality of electrode pads 5 are formed on the uppermost wiring layer of the multilayer wiring layers of the semiconductor chip 3, and are bonded to the bonding pads formed on the surface protection film of the semiconductor chip 3. Exposed by mouth.
  • the plurality of electrode pads 5 are arranged along each side of the semiconductor chip 3.
  • the planar shape of each of the plurality of electrode pads 5 is, for example, a square shape of 70 [ ⁇ m] ⁇ 70 [ ⁇ m]. Further, each of the plurality of electrode pads 5 is arranged at an arrangement pitch of, for example, about 85 [] m].
  • a slide bump made of, for example, gold (Au) is arranged as a protruding electrode.
  • the plurality of pad bumps 7 are respectively arranged on the plurality of electrode pads 5 arranged on one main surface 3X of the semiconductor chip 3 and are electrically and mechanically connected.
  • the stud bumps 7 are formed by, for example, a ball bonding method using an Au wire and using ultrasonic vibration in combination with thermocompression bonding. In the ball bonding method, a ball is formed at the tip of the Au wire, and then the ball is thermocompression-bonded to the electrode pad of the chip while applying ultrasonic vibration. Is cut to form bumps. Therefore, the thread bump formed on the electrode pad is firmly connected to the electrode pad.
  • the semiconductor chip 4 mainly includes a semiconductor chip layer 38 and a redistribution layer (pad rearrangement layer) 3 formed on one main surface of the semiconductor chip layer 38. 9 and a plurality of solder bumps 8 arranged on the rewiring layer 39.
  • the semiconductor chip layer 38 mainly includes a semiconductor substrate 30, a multilayer wiring layer 31 in which insulating layers and wiring layers are stacked in a plurality of stages on one main surface of the semiconductor substrate 30, and a multilayer wiring And a surface protective film 33 formed so as to cover the layer 31.
  • the semiconductor substrate 30 is formed of, for example, a single-crystal silicon
  • the insulating layer of the multilayer wiring layer 31 is formed of, for example, a silicon oxide film
  • the wiring layer of the multilayer wiring layer 31 is formed of, for example, an aluminum (A 1) film or the like.
  • the surface protective film 33 is formed of, for example, a silicon nitride film.
  • a plurality of electrode pads 32 arranged along the long side direction of the one main surface 4X of the semiconductor chip 4 are formed. 0 are arranged in a row along the input / output circuit semiconductor elements formed on one main surface.
  • Each of the plurality of electrode pads 32 is formed on the uppermost wiring layer of the multilayer wiring layer 31.
  • the uppermost wiring layer of the multilayer wiring layer 31 is covered with a surface protective film 33 formed thereon, and an opening for exposing the surface of the electrode pad 32 is formed in the surface protective film 33.
  • the planar shape of each of the plurality of electrode pads 32 is, for example, a square of 30 [ ⁇ m] ⁇ 30 [/ m]. Further, each of the plurality of electrode pads 32 is arranged at an arrangement pitch of about 40 [ ⁇ m], for example.
  • the rewiring layer 39 mainly includes an insulating layer 34 formed on the surface protective film 33, a plurality of wirings 35 extending on the insulating layer 34, and the plurality of wirings 35.
  • each of the plurality of wirings 35 is electrically and mechanically connected to the plurality of electrode pads 32 through an opening formed in the insulating layer 34 and an opening formed in the surface protection film 33. It is connected.
  • the other end of each of approximately half of the wirings 35 is drawn to one long side of two long sides of the semiconductor chip 4 facing each other on one main surface 4X. The other end of each of the remaining wirings 35 is drawn to the other long side.
  • Each of the plurality of inspection electrode pads 37 is electrically and mechanically connected to one end of each of the plurality of wirings 35 through an opening formed in the insulating layer 36.
  • Each of the plurality of electrode pads 6 has an opening formed on the insulating layer 36.
  • the plurality of wires 35 are electrically and mechanically connected to one end of each of the plurality of wires 35 through the port 36a.
  • a plurality of solder bumps 8 arranged on the rewiring layer 39 are electrically and mechanically connected to each of the plurality of electrode pads 6.
  • Each of the plurality of solder bumps 8 has, for example, a Sn—1 [wt%] Ag (silver) —0.5 [wt%] Cu (copper) composition having a melting point of about 230 ° C. It is made of metal material (Pb-free material).
  • the redistribution layer 39 is a layer for relocating the electrode pad 6 having a large pitch with respect to the electrode pad 32 of the semiconductor chip layer 38.
  • the electrode pad 6 of the redistribution layer 39 is The semiconductor chips 4 are arranged at the same arrangement pitch as the arrangement pitch of the connection portions of the wiring board on which the semiconductor chips 4 are mounted.
  • Each of the plurality of electrode pads 6 is not limited to this, but is arranged in two rows along two long sides of the semiconductor chip 4 along two long sides facing each other on one main surface 4X of the semiconductor chip 4. .
  • the electrode pads 6 in each row are arranged at an arrangement pitch of, for example, about 0.5 mm.
  • the planar shape of each of the plurality of electrode pads 6 is, for example, a circle having a diameter of about 0.25 mm.
  • each of the insulating layers 34 and 36 after the semiconductor chip 4 is mounted on the wiring board, the stress generated due to the difference in thermal expansion with the wiring board is applied to the solder bump 8.
  • the silicon nitride film is formed of a material having a lower elastic modulus than that of the silicon oxide film, and is formed with a thickness larger than that of the surface protective film 33.
  • the insulating layers 34 and 36 are formed of, for example, a polyimide resin.
  • the wiring 35 is formed of, for example, a copper (Cu) film having high conductivity, and the multilayer wiring layer 31
  • the insulating film 36 covering the wiring 35 be formed of a thicker conductor film than the electrode pad 32, which is a part of the electrode pad 32, and that the inorganic film formed between the multilayer wiring layers 31 be formed. It is desirable to use an organic insulating film having a lower dielectric constant than an interlayer insulating film.
  • the electrode pad 6 is not limited to this, but may be made of, for example, a chromium (Cr) film, nickel (Ni) —copper (Cu) alloy, in order to ensure wettability when the solder bump 8 is formed. It is formed of a laminated film in which a film and a gold (Au) film are sequentially laminated. '
  • a plurality of wirings 22, a plurality of wirings 23, and the like are formed on one main surface 2X of the wiring board 2, although not shown in detail.
  • the plurality of wirings 22 and 23 are formed on the uppermost wiring layer of the flexible layer 21.
  • Each of the plurality of wirings 22 has a connection portion 22 a formed of a part thereof, and each connection portion 22 a is exposed by an opening formed in the protective film 24.
  • Each connection part 22 a of the plurality of wirings 22 is arranged corresponding to the plurality of electrode pads 5 of the semiconductor chip 3.
  • Each of the plurality of wirings 23 has a connection part 23 a formed of a part thereof, and each connection part 23 a is exposed by an opening formed in the protective film 26.
  • Each connection part 23 a of the plurality of wirings 23 is arranged corresponding to the plurality of electrode pads 6 of the semiconductor chip 4.
  • a plurality of electrode pads 25 are formed on the other main surface (rear surface) opposite to one main surface 2 X of wiring board 2. This electrode pad 25 is formed on the uppermost wiring layer of the flexible layer 21B.
  • Each of the plurality of electrode pads 25 is electrically and mechanically connected to a plurality of solder bumps 11 arranged as external connection terminals on the back surface of the wiring board 2.
  • Each of the plurality of solder bumps 11 has a melting point of, for example, about 18 ° C., and has a melting point of about 37 [wt%] Pb (lead) — 63 [wt%] Sn (tin). Pb—Sn eutectic material).
  • the semiconductor chip 3 is mounted with one main surface 3X facing one main surface 2X of the wiring board 2.
  • an anisotropic conductive resin 9 is interposed between the semiconductor chip 3 and the wiring board 2 as an adhesive resin, and the semiconductor chip 3 is bonded and fixed to the wiring board 2 by the anisotropic conductive resin 9.
  • the anisotropic conductive resin 9 for example, a resin obtained by mixing a large number of conductive particles in an epoxy-based thermosetting insulating resin is used.
  • the plurality of stud bumps 7 are arranged between each electrode pad 5 of the semiconductor chip 3 and each connection part 22 a of the wiring board 2, and electrically connect each electrode pad 5 to each connection part 22 a.
  • the slide bump 7 is formed by a heat shrinkage force (shrinkage force generated when returning from a heated state to a normal temperature state) or a thermosetting shrinkage force of the anisotropic conductive resin 9 interposed between the wiring board 2 and the semiconductor chip 3. (The shrinkage force generated when the thermosetting resin is cured) and the like, and is pressed against the connection portion 22 a of the wiring board 2.
  • a part of the conductive particles mixed in the anisotropic conductive resin 9 is interposed.
  • a concave portion that is depressed in the depth direction of the wiring board 2 is formed in the connection portion 22 a of the wiring board 2. Inside the recess, the slide bump 7 and the connection portion 22a are connected. In this manner, by connecting the slide bumps and the connection portions 22a inside the recess, the one main surface 2X of the wiring board 2 and the semiconductor chip 3 correspond to the recess amount of the recess. The volume of the anisotropic conductive resin 9 between itself and one main surface 3X can be reduced.
  • the stud bump 7 is connected to a connection portion 22 a disposed at the bottom of the opening through an opening formed in the protective film 24. That is, the snow bump 7 is connected to the connection portion 2 2a located at a position deeper than the one main surface 2X in the depth direction from the one main surface 2X of the wiring board 2. .
  • the connection part 22 a is arranged at a position deeper than one main surface of the wiring board 2. Accordingly, the distance between the one main surface 2X of the wiring board 2 and the one main surface 3X of the semiconductor chip 3 corresponds to the depth from the one main surface 2X of the wiring board 2 to the connection portion 22a. In this case, the volume of the anisotropic conductive resin 9 can be reduced.
  • the concave portion of the connecting portion 22 a is formed by elastic deformation of the connecting portion 22 and the flexible layer 21.
  • the concave portion due to the elastic deformation of the connection portion 22 a and the flexible layer 21 can be formed by a pressing force when the semiconductor chip 3 is mounted on one main surface of the wiring board 2.
  • the concave portion is formed by the elastic deformation of the connecting portion 22 a and the flexible layer 21, the elastic force of the connecting portion 22 a and the flexible layer 21 acts on the flat bump 7.
  • the pressing force between 7 and the connecting part 2 2a increases.
  • the space between the one main surface 2X of the wiring board 2 and the one main surface 3X of the semiconductor chip 3 increases due to the expansion of the anisotropic conductive resin 9 in the thickness direction. Even if 7 moves upward, the amount of depression of the concave portion of the connection portion 22 a changes due to the elastic restoration of the flexible layer 21 following the movement of the land bump 7, so that the connection of the wiring board 2 is performed. The connection between the part 22a and the stud bump 7 can be secured.
  • the semiconductor chip 4 is mounted with one main surface 4X facing the one main surface 2X of the wiring board 2.
  • Each of the plurality of solder bumps 8 is disposed between each electrode pad 6 of the semiconductor chip 4 and each connection part 23 a of the wiring board 2, and each electrode pad 6 and each connection part 23 are electrically and mechanically connected to each other.
  • the gap region between the semiconductor chip 4 and the wiring board 2 is filled (injected) with an underfill resin 10 made of, for example, an epoxy-based thermosetting insulating resin.
  • an underfill resin 10 made of, for example, an epoxy-based thermosetting insulating resin.
  • the plurality of stud bumps 7 are arranged along each side of one main surface 3X of the semiconductor chip 3, as shown in FIG.
  • the arrangement pitch 7P of the bumps 7 is set to, for example, about 85 [ ⁇ m].
  • the plurality of solder bumps 8 are arranged in two rows along two long sides of the one main surface 4X of the semiconductor chip 4 facing each other along the long sides. I have.
  • the arrangement pitch 8P of the solder bumps 8 in each row is set to, for example, about 0.5 mm.
  • the multi-piece wiring board 40 has a configuration having a plurality of board formation areas (product formation areas) 41 arranged at predetermined intervals in the longitudinal direction.
  • the wiring substrate 40 has, for example, three substrate forming regions 41.
  • One chip mounting area 42 and two chip mounting areas 43 are provided in each substrate forming area 41.
  • a semiconductor chip (semiconductor chip for connecting a solder bump) 3 is mounted in the chip mounting area 42, and a semiconductor chip (semiconductor chip for connecting a solder bump) 4 is mounted in the chip mounting area 43.
  • Each substrate forming region 41 is surrounded by an isolation region and is separated from each other.
  • the above-described wiring board 2 is formed by cutting the substrate forming area 41 by cutting a separation area of the plurality of wiring boards 40 using, for example, a cutting tool called a bit.
  • the substrate formation region 41 has the same configuration as the wiring substrate 2.
  • FIGS. 10 to 14 are diagrams for explaining the production of MCM-1A.
  • A is a cross-sectional view taken along the line AA in FIG. 1
  • (b) is a cross-sectional view taken along the line BB in FIG.
  • a plurality of wiring boards 40 shown in FIG. 9 are prepared, and a semiconductor chip (semiconductor chip for connecting a bump) 3 shown in FIG. 6 and a semiconductor chip (semiconductor chip for connecting a solder bump) shown in FIG. Prepare tip 4).
  • the semiconductors are collectively placed in each of the chip mounting areas 43 of the plurality of substrate forming areas 41 on one main surface of the wiring board 40.
  • Chip 4 is mounted.
  • the mounting of the semiconductor chip 4 is performed by supplying a flux to the connection portion 23 a disposed in the chip mounting region 43 by, for example, a screen printing method, and then placing the solder bumps 8 on the connection portion 23 a.
  • the semiconductor chip 4 is arranged on each of the chip mounting areas 4 3 of the plurality of substrate forming areas 4 1, and then the wiring board 40 is transported to, for example, an infrared reflex opening furnace to melt the solder bumps 8, Then, it is performed by solidifying the melted solder bumps 8.
  • solder bump 8 of the present embodiment is formed of a metal material having a melting point of about 230 ° C. and having a composition of Sn-1% Ag-0.5% Cu, the solder bump 8 Melting is performed under a reflow temperature condition where the package surface temperature (substrate surface temperature) is about 260 ° C.
  • the flux contains rosin, an activator and an organic solvent.
  • the chip mounting area 42 of the substrate forming area 41 on one main surface of the wiring board 40 is processed into a film shape (sheet shape) as an adhesive resin.
  • the obtained anisotropic conductive resin 9 is attached.
  • the anisotropic conductive resin 9 for example, a resin obtained by mixing a large number of conductive particles into an epoxy-based thermosetting insulating resin is used. Further, as the anisotropic conductive resin 9, a resin having a thermosetting temperature of about 160 ° C. is used.
  • a substrate formation area on one main surface of the wiring board 40 is provided.
  • the semiconductor chip 3 is arranged as a collet 49 on the chip mounting area 42 of FIG. 1 with the anisotropic conductive resin 9 interposed therebetween.
  • the semiconductor chip 3 is arranged such that the thread bump 7 is located on the connection part 22a.
  • the semiconductor chip 3 is arranged in a state where the wiring board 40 is arranged on the heat stage 51 shown in FIG. 13.
  • the semiconductor chip 3 is crimped while the wiring board 40 is heated by the heat stage 51 and the semiconductor chip 3 is heated by the crimping tool 50. Then, the solder bump 7 is connected to the connection part 22 a of the wiring board 40, and then the crimped state is maintained until the anisotropic conductive resin 9 is cured. At this time, the stud bump '7 is pressed against the connecting portion 22a. Curing of the anisotropic conductive resin 9 is performed under the condition of 180 ° C; for 20 seconds. The heating at this time is performed with the crimping tool 50 heated to about 235 ° C. after the temperature of the wiring board 40 is previously set to about 65 ° C.
  • One cycle consists of attaching the anisotropic conductive resin 9, placing the semiconductor chip 3 with the collet 49, and crimping the semiconductor chip 3 with the crimping tool 50, and repeating this cycle for each substrate forming area 41. Apply.
  • the depth from one main surface of the wiring board 40 to the connection part 22a is made shallower than the height of the screw bump 7, so that the connection with the screw bump 7 is connected.
  • a concave portion is formed in the portion 22 a by crimping of the semiconductor chip 3. Further, inside the recess, the connection portion 22 a of the wiring board 40 and the slide bump 7 are connected. Further, since the concave portion is formed by the elastic deformation of the connection portion 22 a and the flexible layer 21, the elastic force of the connection portion 22 a and the flexible layer 21 acts on the slide bump 7.
  • the anisotropic conductive resin 9 when the semiconductor chip (semiconductor chip for connecting the solder bumps) 3 is mounted before the semiconductor chip (semiconductor chip for connecting the solder bumps) 4, the anisotropic conductive The curing temperature of resin 9 Higher heat is applied to the anisotropic conductive resin 9, so that the bond of the anisotropic conductive resin 9 is broken, and the anisotropic conductive resin 9 is easily cracked.
  • a gap region between the chip mounting area 43 on one main surface of the wiring board 40 and the semiconductor chip 4 is made of, for example, an epoxy-based thermosetting insulating resin.
  • a liquid underfill resin 10 is filled, and then heated to cure the underfill resin 10. The curing of the underfill resin 10 is performed under the conditions of an ambient temperature of 160 ° C .; and 2 hours.
  • the underfill resin 10 for example, a resin having a thermosetting temperature of about 120 ° C. is used.
  • the heat at the time of curing the underfill resin 10 is applied to the anisotropic conductive resin 9. Since the temperature at this time is almost the same as the curing temperature of the anisotropic conductive resin 9, Does not break.
  • the underfill resin 10 is filled after the semiconductor chip 4 is mounted and before the semiconductor chip 3 is mounted, the connection of the chip mounting area 4 2 due to the wetting and spreading of the underfill resin 10. Since there is a possibility that 22a may be covered, it is necessary to increase the space between the chip mounting areas 42 and 43. By filling the filling resin 10, there is no possibility that the connection portion 22 a of the chip mounting region 42 is covered by the wetting and spreading of the underfill resin 10. The distance between 4 and 3 can be narrowed.
  • solder bumps 11 are supplied by, for example, a ball supply method, and then the solder bumps 11 are melted to electrically and mechanically connect the electrode pads 25 and the solder bumps 11. Since the solder bump 11 of the present embodiment is formed of a metal material having a melting point of about 183 ° C. and having a Pb—Sn composition, the melting of the solder bump 11 depends on the package surface temperature. Is performed under reflow temperature conditions of about 230 ° C.
  • the heat at the time of melting the solder bumps 11 is applied to the anisotropic conductive resin 9, and the heat treatment at this time is lower in temperature and time than the heat treatment applied when mounting the semiconductor chip 4.
  • the effect of the anisotropic conductive resin 9 breaking the joint is relatively small.
  • the separation area of the plurality of wiring boards 40 is cut with a cutting tool to cut out the substrate formation area 41, whereby the wiring board 2 is formed and MCM-1A is almost completed.
  • a cutting tool to cut out the substrate formation area 41, whereby the wiring board 2 is formed and MCM-1A is almost completed.
  • the substrate formation region 41 was cut out after the solder bumps 11 were formed, but the solder bumps 11 were formed after the substrate formation region 41 was cut out. You may use it.
  • a semiconductor chip (semiconductor chip for solder bump connection) 3 and a semiconductor chip (semiconductor chip for solder bump connection) 4 are mixed on the same wiring board 2.
  • the semiconductor chip 4 is used. After mounting, the semiconductor chip 3 is mounted. As a result, it is possible to prevent heat generated during mounting of the semiconductor chip 4 from being applied to the anisotropic conductive resin 9, so that cracks generated in the anisotropic conductive resin 9 due to a bond breakage in the resin can be prevented. Can be suppressed.
  • the semiconductor chip 3 and the semiconductor chip 4 can be mixedly mounted on the same wiring board 2 while ensuring the connection reliability by the anisotropic conductive resin 9.
  • thermosetting insulating resin used as the underfill resin 10
  • ultraviolet-curing insulating resin may be used as the underfill resin 10.
  • the underfill resin 10 can be cured without applying heat to 9, the reliability of the MCM-1A can be further improved.
  • a film-like anisotropic conductive resin 9 was used as the bonding resin.
  • the bonding resin for example, an insulating resin film in which conductive particles are not mixed is used. (NCF) or pasty anisotropic conductive resin (ACP) may be used.
  • solder bump 8 an example in which a metal material (Pb-free material) having a Sn—l% Ag—0.5% Cu composition is used as the solder bump 8 has been described.
  • a metal material having the same composition as the solder bump 11 may be used.
  • FIG. 15 is a cross-sectional view of a main part of the MCM according to the second embodiment of the present invention.
  • the MCM-1B of the present embodiment has basically the same configuration as the above-described MCM of the first embodiment, and differs from the following configuration. That is, instead of the semiconductor chip (semiconductor chip for solder bump connection) 4, a CSP type semiconductor device 60 in which a semiconductor chip is packaged is mounted on the wiring board 2.
  • the CSP type semiconductor device 60 includes a wiring board 61, a semiconductor chip 64 disposed on one main surface side of the wiring board 61, and an electrode pad 65 disposed on one main surface of the semiconductor chip.
  • a bonding wire 66 electrically connecting the electrode pad 62 arranged on one main surface of the substrate 61; and a resin sealing body 67 sealing the semiconductor chip 64 and the bonding wire 66.
  • the CSP type semiconductor device 60 is mounted on the wiring board 2 by melting the solder bumps 68, similarly to the semiconductor chip 4.
  • the CSP type semiconductor device 60 is mounted first before mounting the semiconductor chip (semiconductor bump connection semiconductor chip) 3, thereby achieving the above-described configuration.
  • the same effects as in the embodiment can be obtained.
  • FIG. 16 is a plan view of the MCM according to the third embodiment of the present invention
  • FIG. 17 is a cross-sectional view of a main part of the MCM shown in FIG. (B) is a cross-sectional view taken along the line D-D in Fig. 16).
  • the MCM-1C of the present embodiment has basically the same configuration as the MCM of the first embodiment described above, and the following configuration is different. I'm wearing
  • the slide bump 7 is electrically and mechanically connected to the connection portion 22 a of the wiring board 2 via the bonding material 52.
  • semiconductor chip In the gap region between the bump (semiconductor chip for connecting a bump) 3 and the wiring board 2, the semiconductor chip 3 generated by the concentration of thermal stress caused by the difference in the thermal expansion coefficient between the wiring board 2 and the semiconductor chip 3 is formed.
  • Underfill resin 10 is filled like semiconductor chip (semiconductor chip for solder bump connection) 4 to suppress damage.
  • the manufacture of the MCM-1C will be described with reference to FIGS. 18 to 23.
  • 18 to 23 are cross-sectional views of main parts for explaining the manufacture of MCM-1C ((a) is a cross-sectional view taken along a line C-C in FIG. 16, (b) ) Is a cross-sectional view taken along the line DD in FIG. 16).
  • a plurality of wiring boards 40 shown in FIG. 9 are prepared, and the semiconductor chip (semiconductor bump connection semiconductor chip) 3 shown in FIG. 6 and the semiconductor chip (solder bump connection) shown in FIG. Prepare 4).
  • the paste-like joining material 52 is supplied by the method.
  • a solder paste material having a lower melting point than the stud bumps 7 of the semiconductor chip 3 and a higher melting point than the solder bumps 8 of the semiconductor chip 4 is used ( at least a minute solder paste material is used ).
  • solder paste material in which solder particles having a composition of (tin) were kneaded was used.
  • the solder bump 7 and the solder bump 8 of the present embodiment are formed of the same material as that of the above-described first embodiment.
  • the method is a method in which a solder paste material is applied by projecting from a thin nozzle.
  • the wiring board 40 is placed on the heat stage 51, and then the stud bump 7 is positioned on the connection part 22a. Then, the semiconductor chip 3 is transferred onto the chip mounting area 42 by the collet 53, and thereafter, the wiring board 40 is heated by the heat stage 51, and the semiconductor chip 3 is collected by the collet 53. Then, the joining material 52 is melted as shown in FIG. 20, and then the melted joining material 52 is solidified. As a result, the semiconductor chip 3 is mounted on the chip mounting area 42 on one main surface of the wiring board 40. The mounting of the semiconductor chip 3 is performed for each of the chip mounting areas 42 of the plurality of substrate forming areas 41 on one main surface of the wiring board 40. .
  • connection portions 23a arranged in the respective chip mounting regions 43 of the plurality of substrate formation regions 41 on one main surface of the wiring substrate 40.
  • the semiconductor chips 4 are arranged on the respective chip mounting areas 43 of the plurality of substrate forming areas 41 so that the solder bumps 8 are located on the connection parts 23a. I do.
  • the wiring board 40 is conveyed to, for example, an infrared reflow furnace to melt the solder bumps 8, and thereafter, the melted solder bumps 8 are solidified.
  • the semiconductor chip 4 is mounted on each of the chip mounting areas 43 of the plurality of substrate forming areas 41 on one main surface of the wiring board 40.
  • solder bump 7 and the bonding material 52 are formed of a material having a higher melting point than the solder bump 8, the solder bump 7 and the bonding material 52 are not melted when the solder bump 8 is melted. .
  • the solder bump 7 is smaller than the solder bump 8, so that when the wiring board 40 is transported to a reflow furnace and reflowed, although displacement such as removal of the solder bump 7 from the connection part 22 a was likely to occur, as in the present embodiment, the wiring board .40 was transported to a furnace with a riff opening to mount the semiconductor chip 4. Before mounting, the semiconductor chip 3 is mounted using a bonding material 52 made of a material higher than the melting point of the solder bump 8, so that the wiring board 40 can be reflowed.
  • connection portions 22 a of the wiring board 40 and the bumps 7 are not connected. Connection failure can be suppressed.
  • the gap area between the chip mounting area 42 on one main surface of the wiring board 40 and the semiconductor chip 3 and the chip mounting area on one main surface of the wiring board 40 A gap region between the region 43 and the semiconductor chip 4 is filled with the underfill resin 10.
  • the underfill resin 10 is filled in a gap region between the wiring board 40 and the semiconductor chip 3.
  • the connection part 23a of the chip mounting area 43 may be covered by the spreading of the underfill resin 10.
  • the connection portion of the chip mounting area 43 is wetted and spread by the underfill resin 10. Since there is no possibility that 23a is covered, the space between the chip mounting areas 42 and 43 can be narrowed.
  • the gap region between the wiring board 40 and the semiconductor chip 3 is filled with the underfill resin 10, and after mounting the semiconductor chip 4, the wiring board 40 and the semiconductor chip are mounted.
  • the underfill resin 10 is filled in the gap region between the underfill resin 10 and the substrate 4
  • heat generated during the mounting of the semiconductor chip 4 is applied to the previously filled underfill resin 10;
  • the underfill resin 10 is filled in the gap region of the semiconductor chip 3 and the semiconductor chip 4 after the semiconductor chip 3 and the semiconductor chip 4 are mounted. Since it is possible to prevent the applied heat from being applied to the previously filled underfill resin 10, it is possible to suppress cracks generated in the underfill resin 10 due to bond breaking in the resin. Also, by filling in the same step, the number of manufacturing steps can be simplified.
  • the underfill resin 10 is filled after the semiconductor chips 3 and 4 are mounted, so that the underfill resin 10 spreads over the chip mounting areas 42 and 43. Since there is no possibility that the connection portion 23a is covered, the space between the chip mounting regions 42 and 43 can be narrowed. As a result, the size of MCM-1C can be reduced.
  • the example in which the paste-like joining material 52 is supplied to the connecting portion 22 a by the dispensing method has been described. May be manufactured using a wiring board on which is formed.
  • FIGS. 24 and 25 are cross-sectional views of a main part for explaining the manufacture of the MCM according to the fourth embodiment of the present invention ((a) is at the same position as the line CC in FIG. 16). (B) is a cross-sectional view at the same position as the line DD in FIG. 16).
  • the manufacture of the MCM of the present embodiment will be described with reference to FIGS. 24 and 25.
  • a plurality of wiring boards 40 shown in FIG. 9 are prepared, and a semiconductor chip (a semiconductor chip for stud bump connection) 3 shown in FIG. 6 and a semiconductor chip (for a solder bump connection) shown in FIG. Prepare semiconductor chip) 4.
  • the respective chip mounting areas of the plurality of substrate forming areas 41 on one main surface of the wiring board 40 are mounted.
  • the semiconductor chip 3 is mounted on 4 2.
  • the mounting of the semiconductor chip 3 is performed in the same manner as in the third embodiment.
  • the bonding material 52 for example, a solder having a composition of 63 [wt%] Pb (lead) — 37 [wt%] Sn (tin) having a melting point of about 18 ° C.
  • a solder paste material kneaded with particles was used.
  • the semiconductor chips 4 are mounted on the respective chip mounting areas 4 3 of the plurality of substrate forming areas 41 on one main surface of the wiring board 40.
  • a flux is supplied to the connection part 23 a by, for example, the dispensing method, and then the semiconductor chip 4 is collected on the chip mounting area 43 so that the solder bump 8 is located on the connection part 23 a 54.
  • the wiring board 40 is heated by the heat stage 51, and the semiconductor chip 4 is heated by the collector 54 to melt the solder bumps 8, and then melt the solder bumps. 8 by coagulation.
  • the mounting of the semiconductor chip 4 is performed for each of the chip mounting areas 43 of the plurality of substrate forming areas 41 on one main surface of the wiring board 40.
  • the semiconductor chip semiconductor chip for mounting a bump
  • the semiconductor chip is held by the collet 53, so that the arrangement pitch of the electrode pads is narrow. Even the semiconductor chip 3 can be mounted without any displacement.
  • the temperature of the semiconductor chip 4 is higher than the temperature of the semiconductor chip 3.
  • the semiconductor chip 4 Since the semiconductor chip 4 is selectively heated with the collet 54 so as not to be higher than the melting point of 52, the semiconductor chip 4 can be mounted without melting the bonding material 52. . As a result, the yield of MCM can be improved. In addition, by doing so, as the bonding material 52, It is also possible to adopt a material having the same melting point as the solder bump 8 or a melting point lower than the solder bump 8.
  • FIG. 26 and FIG. 27 are cross-sectional views of main parts for explaining the manufacture of the MCM according to the fifth embodiment of the present invention ((a) is at the same position as line C--C in FIG. (B) is a cross-sectional view at the same position as the line DD in FIG. 16).
  • the manufacture of the MCM according to the present embodiment will be described with reference to FIGS. 26 and 27.
  • a plurality of wiring boards 40 shown in FIG. 9 are prepared, and a semiconductor chip (semiconductor chip for connecting a bump) 3 shown in FIG. 6 and a semiconductor chip (semiconductor chip for connecting a solder bump) shown in FIG. Prepare tip 4).
  • the semiconductor chip 4 is mounted on each of the chip mounting areas 43 of the plurality of substrate forming areas 41 on one main surface of the wiring board 40.
  • the mounting of the semiconductor chip 4 is performed by applying a flux to, for example, a screen printing method on the connection portions 23 a arranged in the respective chip mounting regions 43 of the plurality of substrate forming regions 41 on one main surface of the wiring board 40.
  • the semiconductor chips 4 are arranged on the respective chip mounting areas 43 of the plurality of substrate forming areas 41 so that the solder bumps 8 are located on the connection parts 23a.
  • the solder bumps 8 are melted by transporting 40 to an infrared reflow furnace, and thereafter, the melted solder bumps 8 are solidified.
  • the semiconductor chip 3 is mounted on each of the chip mounting areas 42 of the plurality of substrate forming areas 41 on one main surface of the wiring board 40.
  • the semiconductor chip 3 is mounted on the connection portions 22 a arranged in the respective chip mounting regions 42 of the plurality of substrate forming regions 41 on one main surface of the wiring substrate 40 by, for example, a paste method.
  • the bonding material 52 is supplied in a shape, and then, as shown in FIG. 27, the wiring board 40 is placed on the heat stage 51, and then the solder bumps 7 are formed on the connecting portions 22a.
  • the semiconductor chip 3 is conveyed by the collet 53 onto the chip mounting area 42 so that it is positioned, and then the wiring board 40 is heated by the heat stage 51 and the semiconductor chip 3 is heated by the collet 53. Heating is performed to melt the bonding material 52 as shown in FIG. 27, and then to solidify the melted bonding material 52.
  • the mounting of the semiconductor chip 3 is performed for each chip mounting area 42 of the plurality of substrate forming areas 41.
  • the semiconductor chip (semiconductor chip for solder bump connection) 4 after mounting the semiconductor chip (semiconductor chip for solder bump connection) 4, the semiconductor chip (semiconductor chip for stud bump connection) 3 is mounted while holding it with the collet 53, so that the electrode pad Even a semiconductor chip 3 having a narrow arrangement pitch can be mounted without causing displacement. Also, when mounting the semiconductor chip 3, the semiconductor chip 3 is selectively heated by the collet 53 so that the temperature of the semiconductor chip 3 becomes higher than the temperature of the semiconductor chip 4. Thus, the semiconductor chip 3 can be mounted without melting the solder bumps 8. As a result, the yield of MCM can be improved.
  • connection portion 23a having a larger pitch than the connection portion 22a by a screen printing method.
  • supply of flux to the multiple connections 23a By performing the batch printing by the screen printing method, the process can be shortened as compared with the case where the flux is supplied to each connection portion 23a by the dispense method.
  • the flux supply step by screen printing is performed before the mounting of the semiconductor chip 3 so that the distance between the chip mounting area 42 and the chip mounting area 43 in each substrate forming area 41 is reduced. As a result, the size of the MCM can be reduced.
  • the invention made by the inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and can be variously modified without departing from the gist of the invention. Of course.
  • the electronic device according to the present invention is useful as an electronic device in which electronic components having different types of protruding electrodes are mixedly mounted on the same substrate.
  • the chip for solder bump connection and the solder bump connection are useful. It is useful as an MCM that mixes chips for use on the same substrate.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Wire Bonding (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
PCT/JP2002/002187 2001-06-22 2002-03-08 Dispositif electronique et son procede de fabrication Ceased WO2003001596A1 (fr)

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JP2001189893A JP4105409B2 (ja) 2001-06-22 2001-06-22 マルチチップモジュールの製造方法

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JPH0983128A (ja) * 1995-09-08 1997-03-28 Toshiba Corp 半導体モジュールの接合構造
JPH11145613A (ja) * 1997-11-07 1999-05-28 Hitachi Ltd 半導体装置およびその製造方法ならびに電子装置

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US9240877B2 (en) 2005-08-22 2016-01-19 Qualcomm Incorporated Segment sensitive scheduling

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US20040235221A1 (en) 2004-11-25
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TW594892B (en) 2004-06-21
JP4105409B2 (ja) 2008-06-25

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