CN103797901B - 部件安装基板的制造方法及制造系统 - Google Patents

部件安装基板的制造方法及制造系统 Download PDF

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Publication number
CN103797901B
CN103797901B CN201380001276.5A CN201380001276A CN103797901B CN 103797901 B CN103797901 B CN 103797901B CN 201380001276 A CN201380001276 A CN 201380001276A CN 103797901 B CN103797901 B CN 103797901B
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solder
electronic unit
thermosetting resin
space
circuit board
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CN103797901A (zh
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本村耕治
岸新
圆尾弘树
铃木康宽
宗像宏典
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Panasonic Intellectual Property Management Co Ltd
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Panasonic Intellectual Property Management Co Ltd
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    • H05K13/00Apparatus or processes specially adapted for manufacturing or adjusting assemblages of electric components
    • H05K13/04Mounting of components, e.g. of leadless components
    • H05K13/046Surface mounting
    • H05K13/0465Surface mounting by soldering
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    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components
    • H05K3/3442Leadless components having edge contacts, e.g. leadless chip capacitors, chip carriers
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Abstract

本发明提供制造布线基板与电子部件的接合强度较高并且在进行了修复处理时在布线基板与电子部件之间不易产生接合不良的部件安装基板的方法及系统。在安装电子部件的布线基板上,在保护层上,形成有使布线层的表面中的、接合电子部件的端子的接合面露出的开口。在电子部件的搭载工序中,以端子覆盖开口的整体并且与被赋予至接合面的焊料膏抵接的方式将电子部件搭载于布线基板。接着,在加热工序,对被赋予至接合面的焊料膏加热,使焊料熔融,并且使热硬化性树脂软化。由此,焊料聚集于以布线层和电子部件封闭的开口内的第1空间,并且热硬化性树脂聚集于以保护层的上表面和电子部件的侧面形成的第2空间。

Description

部件安装基板的制造方法及制造系统
技术领域
本发明涉及部件安装基板的制造方法及制造系统,尤其涉及对布线基板安装电子部件的技术。
背景技术
作为用于将电子部件电接合在布线基板上的接合材料,以往使用低熔点焊料。以往,为了提高布线基板和电子部件的接合强度,承担接合的焊料形成为焊脚(fillet)状。此外,形成为焊脚状的焊料被称为焊料焊脚。然而,为了提高接合强度,仅仅焊料焊脚是不够的,在部件安装基板受到外部冲击的情况下,布线基板与电子部件的电接合有时会被破坏。
因此,为了进一步提高接合强度,提出了使用包含低熔点焊料和热硬化性树脂的焊料膏作为接合材料(例如,参照专利文献1)。在使用该焊料膏在安装时形成了焊料焊脚的情况下,如图9所示的焊料焊脚103上形成树脂硬化膜104(例如,参照专利文献2)。具体而言,对电子部件102与布线基板101的接合面提供焊料膏后,对焊料膏进行加热,由此使焊料熔融,并且使热硬化性树脂软化。其结果是,焊料与热硬化性树脂分离,由此,比重大的焊料向下方移动并形成焊料焊脚103,比重小的热硬化性树脂向上方移动并形成树脂硬化膜104。因此,焊料焊脚103通过树脂硬化膜104被加强,其结果是,接合强度提高。
当在制作出的部件安装基板上判明电子部件的安装不良(例如接合不良)、电子部件本身的不良的情况下,对部件安装基板实施修复处理。在此,修复处理是指,从布线基板上拆下所安装的电子部件,之后,重新将新的电子部件安装于布线基板这一处理。电子部件的拆下是对接合部分(焊料焊脚及树脂硬化膜)进行加热,同时在焊料焊脚熔融并且树脂硬化膜软化了的状态下,例如使用吸附嘴等装置来进行。
现有技术文献
专利文献
专利文献1:日本特开2011-56527号公报
专利文献2:日本特开2006-287060号公报
发明内容
发明要解决的课题
然而,在对图9所示的以往的部件安装基板的修复处理中,在从布线基板101拆下电子部件102的情况下,如图10所示,在布线基板101的表面,焊料105和热硬化性树脂106以彼此相接的状态残存。或者,在布线基板101的表面,焊料105和热硬化性树脂106以彼此混合的状态残存。因此,在重新安装了新的电子部件的情况下,在新形成的焊料焊脚内混入热硬化性树脂,其结果是,在布线基板101与新的电子部件之间可能产生接合不良。
因此,本发明的目的在于,制造布线基板与电子部件的接合强度较高并且在进行了修复处理时在布线基板与电子部件之间不易产生接合不良的部件安装基板的方法及系统。
用于解决课题的手段
本发明涉及的制造方法及制造系统分别是制造在布线基板上安装有电子部件的部件安装基板的方法及系统。在此,布线基板具备:绝缘基板;布线层,形成于绝缘基板的表面;以及保护层,覆盖布线层。并且,在保护层上形成有开口,该开口使布线层的表面中的、成为电接合电子部件的端子的接合面露出。
本发明涉及的制造方法具有赋予焊料膏的赋予工序、搭载电子部件的搭载工序以及对于焊料膏进行加热的加热工序。在赋予工序中,对接合面赋予包含焊料和热硬化性树脂的焊料膏。在搭载工序中,以电子部件的端子与覆盖开口整体并且赋予到接合面的焊料膏抵接的方式将电子部件搭载于布线基板。搭载工序的执行后,在加热工序中,对赋予到接合面的焊料膏进行加热,由此使焊料熔融,并且使热硬化性树脂软化,之后,使热硬化性树脂硬化。在加热工序中,通过焊料的熔融及热硬化性树脂的软化,由此电子部件与保护层的表面接近并且焊料与热硬化性树脂分离。由此,焊料聚集在以布线层和电子部件封闭的开口内的第1空间,并且热硬化性树脂聚集在以保护层的上表面和电子部件的侧面形成的第2空间。
本发明涉及的制造系统具备:赋予焊料膏的赋予装置、搭载电子部件的搭载装置以及对焊料膏进行加热的加热装置。赋予装置对接合面赋予包含焊料和热硬化性树脂的焊料膏。搭载装置以电子部件的端子与覆盖开口整体并且赋予到接合面的焊料膏抵接的方式将电子部件搭载于布线基板。加热装置对赋予到接合面的焊料膏进行加热,由此使焊料熔融,并且使热硬化性树脂软化,之后,使热硬化性树脂硬化。通过加热装置进行的焊料的熔融及热硬化性树脂的软化,由此电子部件接近保护层的表面并且焊料和热硬化性树脂分离。由此,焊料聚集于以布线层和电子部件封闭的开口内的第1空间,并且热硬化性树脂聚集于以保护层的上表面和电子部件的侧面形成的第2空间。
发明的效果
根据本发明涉及的部件安装基板的制造方法及制造系统,能够制造布线基板与电子部件的接合强度较高并且在进行了修复处理时在布线基板与电子部件之间不易产生接合不良的部件安装基板。
将本发明的新的特征记述于所附的权利要求书中,但本发明涉及结构及内容这两方,并且通过对照附图的以下的详细的说明进一步更好地了解本发明的其他的目的及特征。
附图说明
图1是对通过本发明涉及的制造方法及制造系统制作的部件安装基板的一例进行表示的剖视图。
图2是对通过本发明涉及的制造方法及制造系统制作的部件安装基板的其他的例子进行表示的剖视图。
图3是图2所示的III区域的放大图。
图4是对构成本发明的一实施方式涉及的制造系统的制造线进行表示的框图。
图5是对制造线的具体的结构进行表示的剖视图。
图6是用于对通过制造线具备的搭载装置来搭载电子部件的布线基板上的位置(搭载位置)进行说明的剖视图。
图7是用于对通过制造线具备的加热装置来加热焊料膏时的、该焊料膏的状态进行说明的剖视图。
图8是用于对在对图1所示的部件安装基板的修复处理中拆下了电子部件时的布线基板的状态进行说明的剖视图。
图9是对以往的部件安装基板进行表示的剖视图。
图10是用于对在以往的对部件安装基板的修复处理中拆下了电子部件时的布线基板的状态进行说明的剖视图。
具体实施方式
首先,对通过本发明涉及的制造方法及制造系统制作的部件安装基板进行说明。
制作的部件安装基板具备:布线基板、以及安装于布线基板的电子部件。布线基板具备:绝缘基板;布线层,形成于绝缘基板的表面;以及保护层,覆盖布线层。在保护层上形成有开口,该开口使布线层的表面中的、电接合电子部件的端子的接合面从保护层露出,另一方面,开口的整体被端子所覆盖。
并且,以布线层和电子部件封闭的开口内的第1空间被焊料充满,通过该焊料,端子与接合面彼此电接合。另一方面,在第1空间不存在热硬化性树脂。或者,即使在第1空间存在热硬化性树脂,其量也为5vol%左右。或者,在以保护层的上表面和电子部件的侧面形成的第2空间,热硬化性树脂的硬化物将保护层和电子部件彼此机械接合。另一方面,在第2空间不存在焊料。或者,即使在第2空间存在焊料,其量也为5vol%左右。
并且,在以保护层的上表面和电子部件的下表面形成的第3空间,热硬化性树脂的硬化物将保护层和电子部件彼此机械地接合。另一方面,在第3空间不存在焊料。或者,即使在第3空间存在焊料,其量也为5vol%左右。
以下,参照附图对上述部件安装基板的具体例进行说明。
图1是对部件安装基板的一例进行表示的剖视图。如图1所示,部件安装基板10具备:布线基板1、安装于布线基板1的电子部件2。布线基板1具备:绝缘基板11、在绝缘基板11的表面11a形成的布线层12(布线图案)、以及覆盖布线层12的焊料保护层13。
电子部件2具有:部件主体20,由电容元件等无源元件构成;以及两个电极层21,形成于部件主体20的两端部(在图1的纸面的右端部及左端部)。各电极层21的一部分在部件主体20的下表面蔓延。因此,在电子部件2上,通过电极层21,构成在电子部件2的下表面露出的两个端子。
如图1所示,焊料保护层13上形成有与电极层21一个一个对应的两个开口14。开口14使第1布线层12的表面中的、电接合电极层21的接合面12a从焊料保护层13露出。另一方面,各开口14的整体被与该开口14对应的电极层21覆盖。由此,开口14内的空间成为以布线层12和电子部件2封闭的空间(第1空间31)。
并且,第1空间31被焊料41填满,通过该焊料41,电极层21与接合面12a彼此电接合。另一方面,在第1空间31,不存在热硬化性树脂。或者,即使设为在第1空间31存在热硬化性树脂,其量也为5vol%左右。此外,焊料41使用例如Sn-Bi类、Sn-Bi-Ag类的低熔点焊料。
另外,如图1所示,在以焊料保护层13的上表面和电子部件2的侧面形成的第2空间32,存在热硬化性树脂的硬化物42。另一方面,在第2空间32,不存在焊料。或者,即使在第2空间32存在焊料,其量也为5vol%左右。具体而言,硬化物42在第2空间32中,掩埋以焊料保护层13和电子部件2形成的角落,并且向该角落的周围扩展成焊脚状。因此,硬化物42在第2空间32,将焊料保护层13和电子部件2彼此机械地接合。此外,在构成硬化物42的热硬化性树脂中,使用例如环氧树脂。
并且,在以焊料保护层13的上表面和部件主体20的下表面形成的第3空间33,存在热硬化性树脂的硬化物43。因此,硬化物43存在于焊料保护层13的上表面与部件主体20的下表面之间。另一方面,在第3空间33,不存在焊料。或者,即使在第3空间33存在焊料,其量也为5vol%左右。因此,硬化物43在第3空间33中,将焊料保护层13和电子部件2彼此机械地接合。此外,在本实施方式中,第3空间33形成在两个电极层21之间。另外,构成硬化物43的热硬化性树脂是与构成硬化物42的热硬化性树脂相同的树脂。
在上述部件安装基板10上,各开口14整体被与该开口14对应的电极层21覆盖。因此,各开口14的大小比与该开口14相当的以往的部件安装基板的开口107(参照图9)的大小要小。具体而言,各开口14的面积相对于与该开口14对应的电极层21的下表面的面积的比例为50~100%。此外,如图9所示,在以往的部件安装基板中,只不过是各开口107的一部分被电子部件102覆盖。
图2是对部件安装基板的其他的例子进行表示的剖视图。图3是图2所示的III区域的放大图。如图2所示,部件安装基板310具备:布线基板301、以及安装于布线基板301的触点阵列封装(LGA)型的电子部件302。电子部件302具有:基板320、搭载于基板320上的半导体元件321、以及在基板320上覆盖半导体元件321的外装体322。
在基板320上,上表面上形成有多个第1平面电极323(焊盘),并且下表面上形成有多个第2平面电极324(焊盘)。此外,第2平面电极324排列成格子(栅格)状。并且,第1平面电极323上电连接有半导体元件321的端子(未图示)。另外,如图3所示,各第1平面电极323及与其对应的第2平面电极324通过将基板320从其上表面到下表面贯通的导电柱325彼此电连接。因此,在电子部件302中,通过第2平面电极324,构成从电子部件302的下表面露出的多个端子。
如图2及图3所示,布线基板301具备:绝缘基板311、在绝缘基板311的表面311a上形成的布线层312、以及覆盖布线层312的焊料保护层313。在焊料保护层313上,形成有与第2平面电极324一个一个对应的多个开口314。如图3所示,开口314使布线层312的表面中的、电接合第2平面电极324的接合面312a从焊料保护层313露出。另一方面,各开口314整体被与该开口314对应的第2平面电极324覆盖。由此,开口314内的空间成为以布线层312和电子部件302封闭的空间(第1空间331)。
并且,第1空间331被焊料341充满,通过该焊料341,第2平面电极324与接合面312a彼此电接合。另一方面,在第1空间331中,不存在热硬化性树脂。或者,即使第1空间331中存在热硬化性树脂,其量也为5vol%左右。此外,焊料341使用例如Sn-Bi类、Sn-Bi-Ag类的低熔点焊料。
另外,如图3所示,在以焊料保护层313的上表面和电子部件302的侧面形成的第2空间332中,存在热硬化性树脂的硬化物342。另一方面,在第2空间332中,不存在焊料。或者,即使第2空间332中存在焊料,其量也为5vol%左右。具体而言,硬化物342在第2空间332中将以焊料保护层313和电子部件302形成的角落掩埋,并且向该角落的周围扩展成焊脚状。因此,硬化物342在第2空间332中,将焊料保护层313和电子部件302彼此机械接合。此外,在构成硬化物342的热硬化性树脂中,使用例如环氧树脂。
并且,在以焊料保护层313的上表面和基板320的下表面形成的第3空间333中,存在热硬化性树脂的硬化物343。因此,硬化物343存在于焊料保护层313的上表面与电子部件302的下表面之间。另一方面,在第3空间333中,不存在焊料。或者,即使在第3空间333中存在焊料,其量也为5vol%左右。因此,硬化物343在第3空间333中,将焊料保护层313和电子部件302彼此机械接合。此外,构成硬化物343的热硬化性树脂是与构成硬化物342的热硬化性树脂相同的树脂。
与部件安装基板10同样地,在上述部件安装基板310上,各开口314整体也被与该开口314对应的第2平面电极324覆盖。因此,与具备LGA型的电子部件的以往的部件安装基板的开口的大小相比,各开口314的大小较小。具体而言,各开口314的面积相对于与该开口314对应的第2平面电极324的下表面的面积的比例是50~100%。
接着,对本发明涉及的部件安装基板的制造方法及制造系统进行说明。
本发明涉及的制造方法及制造系统分别是制造在布线基板上安装有电子部件的部件安装基板的方法及系统。在此,布线基板具备:绝缘基板;布线层,形成于绝缘基板的表面;以及覆盖布线层的保护层。并且,在保护层上形成有开口,该开口使布线层的表面中的、电接合电子部件的端子的接合面露出。
本发明涉及的制造方法具有:赋予焊料膏的赋予工序、搭载电子部件的搭载工序、以及加热焊料膏的加热工序。在赋予工序中,对接合面赋予包含焊料和热硬化性树脂的焊料膏。在搭载工序中,以电子部件的端子覆盖开口的整体并且与被赋予到接合面的焊料膏抵接的方式,将电子部件搭载于布线基板。此时,通常,以使该下表面从保护层的表面离开的状态将电子部件搭载于布线基板。搭载工序的执行后,在加热工序中,通过对被赋予到接合面的焊料膏加热,使焊料熔融,并且使热硬化性树脂软化,之后,使热硬化性树脂硬化。
此外,上述的赋予工序、搭载工序、及加热工序的分别由以下说明的制造系统所具备的赋予装置、搭载装置、及加热装置来执行的工序。
本发明涉及的制造系统具备:赋予焊料膏的赋予装置、搭载电子部件的搭载装置、以及加热焊料膏的加热装置。赋予装置对接合面赋予包含焊料和热硬化性树脂的焊料膏。搭载装置以电子部件的端子覆盖开口的整体并且与被赋予到接合面的焊料膏抵接的方式,将电子部件搭载于布线基板。此时,搭载装置通常以使该下表面从保护层的表面离开的状态将电子部件搭载于布线基板。加热装置通过对被赋予到接合面的焊料膏加热,使焊料熔融,并且使热硬化性树脂软化,之后,使热硬化性树脂硬化。
通过上述制造方法及制造系统,通过对焊料膏的加热引起的焊料的熔融及热硬化性树脂的软化,从而电子部件接近保护层的表面并且焊料与热硬化性树脂分离。由此,焊料聚集于以布线层和电子部件封闭的开口内的第1空间,并且热硬化性树脂聚集于以保护层的上表面和电子部件的侧面形成的第2空间。并且,热硬化性树脂聚集在以保护层的上表面和电子部件的下表面形成的第3空间。
之后,通过对焊料膏的进一步的加热,热硬化性树脂硬化。之后,在冷却过程中,焊料固化。其结果是,通过固化了的焊料,布线基板和电子部件在第1空间中彼此电接合。另外,通过热硬化性树脂硬化,从而在第2空间及第3空间中形成硬化物。并且,通过该硬化物,布线基板和电子部件在第2空间及第3空间中彼此机械接合。
在这样制造出的部件安装基板中,第1空间与第2空间之间、以及第1空间与第3空间之间被电子部件遮蔽。因此,第2空间及第3空间形成于沿着保护层的上表面从第1空间离开的位置。因此,第2空间内的硬化物及第3空间内的硬化物不会与第1空间内的焊料相接。
因此,在对部件安装基板的修复处理中,在从布线基板拆下了电子部件时,虽然在布线基板上残存焊料及热硬化性树脂,但是焊料位于开口内,并且热硬化性树脂在不与焊料相接的情况下位于保护层的上表面。因此,即使在重新安装新的电子部件的情况下,热硬化性树脂也几乎不会混入到焊料内。因此,即使对部件安装基板实施过修复处理的情况下,在布线基板与新的电子部件之间也不易发生接合不良。
另外,在上述部件安装基板中,通过焊料,布线基板和电子部件在第1空间中彼此接合。除此之外,布线基板与电子部件在第2空间及第3空间中通过热硬化性树脂的硬化物彼此接合。因此,在上述部件安装基板中,布线基板与电子部件的接合强度较高。
在上述制造方法及制造系统的较为理想的具体的结构中,以接合面上的焊料膏中包含的焊料的总体积与第1空间的容积大致相同的方式,对接合面赋予焊料膏(赋予工序及赋予装置)。此外,焊料的总体积相对于第1空间的容积的比例为95~100%的较为理想的。由此,防止热硬化性树脂混入第1空间内的焊料,其结果是,防止接合不良的产生。另外,防止焊料从开口溢出并且焊料混入到第2空间内的硬化物中,其结果是,防止接合强度的降低。
以下,作为本发明的一实施方式,参照附图对制造图1所示的部件安装基板10的制造系统进行具体地说明。此外,以下说明的制造系统也能够应用于图2所示的部件安装基板310的制造中。
图4是对构成本实施方式涉及的制造系统的制造线进行表示的框图。如图4所示,制造线具备:供给布线基板1的基板供给装置201、焊料膏赋予装置202、将电子部件2搭载于布线基板1的搭载装置203、加热装置204、回收制造出的部件安装基板10的回收装置205、以及在这些装置之间输送布线基板1的输送装置206。
图5是对上述制造线的具体的结构进行表示的剖视图。如图5所示,输送装置206由具有输送带6的输送设备构成。此外,输送装置206不限于输送设备,能够使用具有输送功能的各种装置。并且,输送带6上载有从基板供给装置201供给的布线基板1。基板供给装置201例如使用料斗式的基板装载机。
焊料膏赋予装置202对于布线基板1赋予包含焊料和热硬化性树脂的焊料膏4。具体而言,焊料膏赋予装置202对开口14供给焊料膏4,由此对接合面12a赋予焊料膏4。此时,焊料膏赋予装置202以在各接合面12a上的焊料膏4上包含的焊料的总体积和与该接合面12a对应的第1空间31(参照图1)的容积大致相同的方式,对开口14供给焊料膏4。此外,焊料的总体积相对于第1空间31的容积的比例为95~100%的较为理想的。
在本实施方式中,如上所述,开口14的大小比以往的部件安装基板的开口107(参照图9)的大小要小。因此,如果设为焊料保护层13的厚度与以往的部件安装基板的焊料保护层110(参照图9)的厚度相同,则产生如下问题。即,在对各开口14赋予了与在以往的部件安装基板的制造过程中对各开口107赋予的量相同的量的焊料膏4的情况下,所赋予的焊料膏4中包含的焊料的总体积比与该开口14对应的第1空间31的容积大。因此,在制造的部件安装基板中,焊料从第1空间31溢出,从而焊料与热硬化性树脂相接。
因此,在本实施方式中,为了使各第1空间31的容积与上述焊料的总体积一致,焊料保护层13的厚度被设定得较大。具体而言,其厚度为30~70μm。或者,为了使上述焊料的总体积与各第1空间31的容积一致,通过焊料膏赋予装置202,对各开口14的焊料膏4的赋予量被调整得较小。此外,为了使上述焊料的总体积与各第1空间31的容积一致,也可以以使焊料膏4中的焊料的含有率变小的方式来制备焊料膏4。
构成焊料膏4的焊料及热硬化性树脂分别使用例如Sn-Bi类、Sn-Bi-Ag类的低熔点焊料及环氧树脂。另外,焊料膏4中也可以根据需要包含活性剂、触变剂。此外,焊料及热硬化性树脂并不限于这些材料。但是,因为容易处理、硬化物的强度较高、及硬化特性良好,环氧树脂作为使用的热硬化性树脂是恰当的。
在本实施方式中,使用网板印刷装置作为焊料膏赋予装置202。图5中示出了网板印刷用的掩模7。在焊料膏赋予装置202中,基于布线基板1的位置及姿态调整掩模7的位置,由此来调整赋予焊料膏4的位置。此外,焊料膏赋予装置202也可以使用具有印刷用的喷嘴的印刷装置(例如,喷墨打印机等)、带有涂敷头(针或喷嘴)和分配器的涂敷装置。
搭载装置203在布线基板1上的搭载位置搭载电子部件2。如图6所示,搭载位置是如下位置,即电子部件2的各电极层21覆盖与该电极层21对应的开口14整体,并且与被赋予到与该电极层21对应的接合面12a的焊料膏4抵接的位置。另外,搭载装置203在使电极层21的下表面从焊料保护层13的表面离开了规定的距离L的状态下将电子部件2搭载于布线基板1。作为一例,搭载装置203具有电子部件供给装置、以及将从该电子部件供给装置供给的电子部件2配置于上述搭载位置的贴片机。电子部件供给装置能够使用带式供料器、散装式供料器、及盘式供料器等装置。另外,贴片机能够使用吸附嘴等装置。
如图6所示,当在布线基板1上的搭载位置刚刚搭载了电子部件2之后,焊料41分散于焊料膏4整体。另外,间隙8存在于电极层21与焊料保护层13之间。
加热装置204对被赋予到接合面12a的焊料膏4加热,从而使焊料膏4中的焊料41熔融,并且使焊料膏4中的热硬化性树脂44(参照图6)软化。在此,焊料保护层13具有熔融了的焊料41难以附着于表面这一性质,换言之具有容易拉下(日语:弾きやすい;repelling)熔融了的焊料41的性质。因此,熔融了的焊料41如图7所示,穿过间隙8,向不存在焊料保护层13的地方(具体而言开口14内)移动。此外,在图7中,通过实线箭头表示焊料41移动的样子。
另外,焊料41的比重比热硬化性树脂44大。因此,如图7所示,焊料41在开口14内向下方移动,由此焊料41蓄积于接合面12a。另一方面,伴随着焊料41的向开口14内的移动,开口14内的热硬化性树脂44向开口14外驱出(日语:追い出す;forced)。然后,热硬化性树脂44穿过间隙8向焊料保护层13上移动。此外,在图7中,通过虚线箭头表示热硬化性树脂44移动的样子。
并且,伴随着焊料41及热硬化性树脂44的移动,电子部件2接近焊料保护层13的表面。并且,各开口14被与该开口14对应的电极层21堵住,由此形成第1空间31(参照图1)。伴随于此,在焊料保护层13上形成第2空间32及第3空间33(参照图1)。因此,第1空间31与第2空间32之间、以及第1空间31与第3空间33之间被电子部件2遮蔽。
因此,在第1空间31中,焊料41聚集,另一方面,不包含热硬化性树脂44。或者,即使第1空间31中包含热硬化性树脂44,其量也为5vol%左右。另外,在第2空间32及第3空间33中,热硬化性树脂44聚集,另一方面,不包含焊料41。或者,即使在第2空间32及第3空间33中包含焊料41,其量也为5vol%左右。
之后,加热装置204进一步对焊料膏4加热,由此使热硬化性树脂44硬化。之后,在冷却过程中,焊料41固化。其结果是,通过固化了的焊料41,布线基板1和电子部件2在第1空间31中彼此电接合。另外,通过热硬化性树脂44硬化,在第2空间32及第3空间33中分别形成硬化物42及43。并且,通过硬化物42及43,布线基板1和电子部件2在第2空间32及第3空间33中彼此机械接合。
这样,制作出图1所示的部件安装基板10。
回收装置205从输送带6上回收制作出的部件安装基板10。此外,回收装置205使用例如料斗式的基板卸载机。
在上述部件安装基板10上,第1空间31与第2空间32之间、以及第1空间31与第3空间33之间被电子部件2遮蔽。因此,第2空间32及第3空间33形成于沿焊料保护层13的上表面从第1空间31离开的位置。因此,第2空间32内的硬化物42及第3空间33内的硬化物43不会与第1空间31内的焊料41相接。
因此,在对部件安装基板10的修复处理中,在如图8所示那样从布线基板1拆下了电子部件2时,虽然布线基板1上残存焊料41及热硬化性树脂44,但焊料41位于第1开口14内,并且热硬化性树脂44在不与焊料41相接的情况下位于焊料保护层13的上表面。因此,即使重新安装了新的电子部件2的情况下,热硬化性树脂也几乎不会混入到焊料内。因此,即使在对部件安装基板10实施了修复处理的情况下,在布线基板1与新的电子部件2之间也难以产生接合不良。
另外,在上述部件安装基板10上,通过焊料41,布线基板1与电子部件2在第1空间31中彼此接合。除此之外,布线基板1与电子部件2在第2空间32中通过硬化物42而彼此接合,并且在第3空间33中通过硬化物43而彼此接合。因此,在上述部件安装基板10上,布线基板1与电子部件2的接合强度较高。
在图9所示的以往的部件安装基板中,开口107使布线层108的表面中的、电接合电子部件102的接合面109从焊料保护层110露出。并且,电子部件102在其两端从接合面109浮起的状态下,经由焊料焊脚103与接合面109电接合。因此,在以往的部件安装基板的制造过程中,将用于形成焊料焊脚103的焊料膏赋予两个接合面109时,对两个接合面109的焊料膏的赋予量互不相同时,容易产生如下现象。即,焊料由于对焊料膏的加热而熔融了之后,焊料固化时,由于赋予量不同成为原因而产生的固化速度的差异,电子部件102的一端被向接合面109一方牵拉,其结果是,电子部件102倾斜。
另一方面,在上述部件安装基板10上,电子部件2的两端位于焊料保护层13的表面上。因此,即使电子部件2的一端被向下方牵拉,其一端的向下方的移动也被焊料保护层13阻止。因此,电子部件2不易倾斜。
此外,本发明的各部结构不限于上述实施方式,能够在权利要求书记载的技术范围内进行各种变形。在上述实施方式中,基板供给装置201、焊料膏赋予装置202、搭载装置203、加热装置204及回收装置205分别独立地构成。然而,本发明并不限定于此。例如,也可以使用具有它们的功能的复合型的装置代替这些装置中的几个或全部。
另外,上述的制造方法及制造系统也能够应用于将球栅阵列(BGA)型的电子部件安装于布线基板的情况。并且,上述的制造方法及制造系统也能够应用于各种部件安装基板的制造,各种部件安装基板不限定于具备图1所示的部件安装基板10或图2所示的LGA型的电子部件的部件安装基板310。
关于当前的较为理想的实施方式本发明进行了说明,但这种公开不能解释为限定性的。通过阅读上述公开,本发明所属技术领域的本领域技术人员当然能够知晓各种变形以及改变。因此,所附的权利要求书应当解释为包含在不脱离本发明的真正的精神及范围的情况下的全部变形及改变。
工业实用性
本发明涉及的制造系统及制造方法能够应用于液晶显示模块等电子设备具备的部件安装基板的制造。
符号说明
1 布线基板
2 电子部件
4 焊料膏
10 部件安装基板
11 绝缘基板
11a 表面
12 布线层
12a 接合面
13 焊料保护层
14 开口
21 电极层(端子)
31 第1空间
32 第2空间
33 第3空间
41 焊料
42,43 硬化物
44 热硬化性树脂
201 基板供给装置
202 焊料膏赋予装置
203 搭载装置
204 加热装置
205 回收装置
301 布线基板
302 电子部件
310 部件安装基板
311 绝缘基板
311a 表面
312 布线层
312a 接合面
313 焊料保护层
314 开口
324 第2平面电极(端子)
331 第1空间
332 第2空间
333 第3空间
341 焊料
342,343 硬化物
L 规定的距离

Claims (6)

1.一种部件安装基板的制造方法,是制造在布线基板上安装有电子部件的部件安装基板的方法,所述布线基板具备:绝缘基板;布线层,形成于所述绝缘基板的表面;以及保护层,覆盖所述布线层,在所述保护层上,形成有使所述布线层的表面中的、电接合所述电子部件的端子的接合面露出的开口,
该部件安装基板的制造方法包括以下步骤:
(a)对所述接合面赋予包含焊料和热硬化性树脂的焊料膏的工序;
(b)以所述电子部件的端子覆盖所述开口的整体并且与被赋予至所述接合面的焊料膏抵接的方式,将所述电子部件搭载于所述布线基板的工序;以及
(c)所述工序(b)执行后,对被赋予至所述接合面的焊料膏加热,从而使所述焊料熔融,并且使所述热硬化性树脂软化,之后,使所述热硬化性树脂硬化的工序,
在所述工序(c)中,通过所述焊料的熔融及所述热硬化性树脂的软化,从而所述电子部件接近所述保护层的表面,并且所述焊料和所述热硬化性树脂分离,由此,所述焊料聚集在以所述布线层和所述电子部件封闭的所述开口内的第1空间,并且所述热硬化性树脂聚集在由所述保护层的上表面和所述电子部件的侧面形成的第2空间。
2.如权利要求1所述的部件安装基板的制造方法,
在所述工序(a)中,以所述接合面上的所述焊料膏中包含的焊料的总体积与所述第1空间的容积相同的方式,赋予所述焊料膏。
3.如权利要求1或2所述的部件安装基板的制造方法,
在所述工序(b)中,以使所述电子部件的下表面从所述保护层的表面离开的状态将所述电子部件搭载于所述布线基板。
4.一种部件安装基板的制造系统,是制造在布线基板上安装有电子部件的部件安装基板的系统,所述布线基板具备:绝缘基板;布线层,形成于所述绝缘基板的表面;以及保护层,覆盖所述布线层,在所述保护层上,形成有使所述布线层的表面中的、电接合所述电子部件的端子的接合面露出的开口,
该部件安装基板的制造系统包括:
赋予装置,对所述接合面赋予包含焊料和热硬化性树脂的焊料膏;
搭载装置,以所述电子部件的端子覆盖所述开口的整体并且与被赋予至所述接合面的焊料膏抵接的方式,将所述电子部件搭载于所述布线基板;以及
加热装置,对被赋予至所述接合面的焊料膏加热,从而使所述焊料熔融,并且使所述热硬化性树脂软化,之后,使所述热硬化性树脂硬化;
通过所述加热装置引起的所述焊料的熔融及所述热硬化性树脂的软化,从而所述电子部件接近所述保护层的表面,并且所述焊料和所述热硬化性树脂分离,由此,所述焊料聚集在以所述布线层和所述电子部件封闭的所述开口内的第1空间,并且所述热硬化性树脂聚集在由所述保护层的上表面和所述电子部件的侧面形成的第2空间。
5.如权利要求4所述的部件安装基板的制造系统,
所述赋予装置以所述接合面上的所述焊料膏中包含的焊料的总体积与所述第1空间的容积相同的方式,赋予所述焊料膏。
6.如权利要求4或5所述的部件安装基板的制造系统,
所述搭载装置以使所述电子部件的下表面从所述保护层的表面离开的状态将所述电子部件搭载于所述布线基板。
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Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9615495B2 (en) * 2012-11-19 2017-04-04 Panasonic Intellectual Property Management Co., Ltd. Electronic component mounting system and electronic component mounting method
JP5945697B2 (ja) * 2012-11-19 2016-07-05 パナソニックIpマネジメント株式会社 電子部品実装システムおよび電子部品実装方法
CN104996005B (zh) * 2012-11-19 2018-08-10 松下知识产权经营株式会社 电子元件安装系统及电子元件安装方法
US9791470B2 (en) * 2013-12-27 2017-10-17 Intel Corporation Magnet placement for integrated sensor packages
JP6576108B2 (ja) * 2015-06-08 2019-09-18 三菱電機株式会社 電力用半導体装置
US10512168B2 (en) * 2016-02-18 2019-12-17 Mitsubishi Electric Corporation Electronic device and method of manufacturing the same
JP6956475B2 (ja) 2016-09-28 2021-11-02 エルジー ディスプレイ カンパニー リミテッド 電子部品の実装方法、電子部品の接合構造、基板装置、ディスプレイ装置、ディスプレイシステム
JP6726070B2 (ja) * 2016-09-28 2020-07-22 エルジー ディスプレイ カンパニー リミテッド 電子部品の実装方法、電子部品の接合構造、基板装置、ディスプレイ装置、ディスプレイシステム
JP2018098302A (ja) * 2016-12-09 2018-06-21 株式会社デンソー 電子装置
US10980160B2 (en) 2018-09-26 2021-04-13 Canon Kabushiki Kaisha Image pickup module, method for manufacturing image pickup module, and electronic device
JP7512027B2 (ja) 2019-11-06 2024-07-08 キヤノン株式会社 電子モジュールの製造方法、電子モジュール、及び電子機器
JP7511180B2 (ja) * 2020-07-27 2024-07-05 パナソニックIpマネジメント株式会社 実装方法およびそれにより形成される実装構造体

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1362983A (zh) * 2000-02-29 2002-08-07 松下电器产业株式会社 导电性黏合剂和电子部件的装配体及其装配方法
CN1692685A (zh) * 2002-12-24 2005-11-02 松下电器产业株式会社 内装电子部件的组件
CN1926929A (zh) * 2004-12-27 2007-03-07 松下电器产业株式会社 电子部件安装方法及电子部件安装结构
CN100356536C (zh) * 2003-01-08 2007-12-19 Lg电线株式会社 微电极连接方法及基于其的连接结构

Family Cites Families (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3152834B2 (ja) * 1993-06-24 2001-04-03 株式会社東芝 電子回路装置
US6316735B1 (en) * 1996-11-08 2001-11-13 Ricoh Company, Ltd. Semiconductor chip mounting board and a semiconductor device using same board
JPH10163261A (ja) * 1996-11-29 1998-06-19 Kyocera Corp 電子部品搭載用配線基板の製造方法
DE19750073A1 (de) * 1997-11-12 1999-05-20 Bosch Gmbh Robert Schaltungsträgerplatte
US6326239B1 (en) * 1998-04-07 2001-12-04 Denso Corporation Mounting structure of electronic parts and mounting method of electronic parts
DE19839760A1 (de) * 1998-09-01 2000-03-02 Bosch Gmbh Robert Verfahren zur Verbindung von elektronischen Bauelementen mit einem Trägersubstrat sowie Verfahren zur Überprüfung einer derartigen Verbindung
JP4105409B2 (ja) * 2001-06-22 2008-06-25 株式会社ルネサステクノロジ マルチチップモジュールの製造方法
JP3595283B2 (ja) * 2001-06-27 2004-12-02 日本特殊陶業株式会社 配線基板及びその製造方法
TW523857B (en) * 2001-12-06 2003-03-11 Siliconware Precision Industries Co Ltd Chip carrier configurable with passive components
US6742247B2 (en) * 2002-03-14 2004-06-01 General Dynamics Advanced Information Systems, Inc. Process for manufacturing laminated high layer count printed circuit boards
WO2005005088A2 (en) * 2003-07-01 2005-01-20 Chippac, Inc. Method and apparatus for flip chip attachment by post-collapse re-melt and re-solidification of bumps
US8216930B2 (en) * 2006-12-14 2012-07-10 Stats Chippac, Ltd. Solder joint flip chip interconnection having relief structure
CN100446205C (zh) * 2004-03-29 2008-12-24 日本电气株式会社 半导体装置和其制造方法
US7420282B2 (en) * 2004-10-18 2008-09-02 Sharp Kabushiki Kaisha Connection structure for connecting semiconductor element and wiring board, and semiconductor device
JP4401411B2 (ja) * 2005-03-17 2010-01-20 パナソニック株式会社 半導体チップを備えた実装体およびその製造方法
JP2006287060A (ja) 2005-04-01 2006-10-19 Sony Corp 回路基板、およびチップ部品の半田付け構造
JP4522939B2 (ja) * 2005-10-31 2010-08-11 アルプス電気株式会社 基板と部品間の接合構造及びその製造方法
JP4555211B2 (ja) * 2005-11-08 2010-09-29 アルプス電気株式会社 電子部品実装構造及びその製造方法
KR100718169B1 (ko) * 2006-01-12 2007-05-15 한국과학기술원 니켈 표면 처리된 전자부품과 무전해 니켈 표면 처리된전자부품의 접합방법
TWI286830B (en) * 2006-01-16 2007-09-11 Siliconware Precision Industries Co Ltd Electronic carrier board
US7537961B2 (en) * 2006-03-17 2009-05-26 Panasonic Corporation Conductive resin composition, connection method between electrodes using the same, and electric connection method between electronic component and circuit substrate using the same
JP5160813B2 (ja) 2007-05-25 2013-03-13 パナソニック株式会社 導電性ペーストおよび基板
JP5243735B2 (ja) * 2007-06-18 2013-07-24 ローム株式会社 回路基板及び半導体装置
JP2009272529A (ja) * 2008-05-09 2009-11-19 Ngk Spark Plug Co Ltd 半田ボール搭載装置及び配線基板の製造方法
JPWO2009144846A1 (ja) * 2008-05-30 2011-10-06 イビデン株式会社 半田ボール搭載方法
JP5698447B2 (ja) 2009-09-08 2015-04-08 株式会社タムラ製作所 はんだ接合剤組成物
JP5619439B2 (ja) * 2010-03-16 2014-11-05 株式会社ジャパンディスプレイ 実装構造体、電気光学装置、実装部品および実装構造体の製造方法
JP5559023B2 (ja) * 2010-12-15 2014-07-23 日本特殊陶業株式会社 配線基板及びその製造方法
JP5382010B2 (ja) * 2011-01-24 2014-01-08 ブラザー工業株式会社 配線基板、及び、配線基板の製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1362983A (zh) * 2000-02-29 2002-08-07 松下电器产业株式会社 导电性黏合剂和电子部件的装配体及其装配方法
CN1692685A (zh) * 2002-12-24 2005-11-02 松下电器产业株式会社 内装电子部件的组件
CN100356536C (zh) * 2003-01-08 2007-12-19 Lg电线株式会社 微电极连接方法及基于其的连接结构
CN1926929A (zh) * 2004-12-27 2007-03-07 松下电器产业株式会社 电子部件安装方法及电子部件安装结构

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