Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W42/00—Arrangements for protection of devices
  • H10W42/40—Arrangements for protection of devices protecting against tampering, e.g. unauthorised inspection or reverse engineering
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/117—Shapes of semiconductor bodies
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
  • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
  • H10W70/68—Shapes or dispositions thereof

Definitions

• Integrated circuit arrangement made of a flat substrate
• the invention relates to an integrated circuit arrangement made of a flat substrate.
• the substrate is brought from the flat shape into a non-planar shape by the carrier at least in one direction of propagation, it cannot be machined by means of grinding processes with reasonable effort such that the surface can be removed in layers in a completely analyzable manner.
• the desired deformation can also be generated by mechanical stresses that arise in the substrate itself, for example by changing the chemical or physical structure of the substrate. For example, implantation processes, diffusion processes or thermal processes can be used for this. With suitable technology, soldering and connection methods, for example between a plurality of substrates which are arranged one above the other, can also be used to specifically generate mechanical stresses in the substrate.
• a deformed substrate usually retains its deformed shape after some time.
• partial areas can also be removed at least on one surface.
• FIG. 1 shows the basic structure of an integrated circuit arrangement on a semiconductor chip
• FIG. 2 shows a first exemplary embodiment of an integrated circuit arrangement according to the invention on a semiconductor chip
• FIG. 3 shows the surface in a modification of the first exemplary embodiment
• FIG. 4 shows a second exemplary embodiment according to the invention
• FIG. 5 shows a modification of the second exemplary embodiment
• FIG. 6 shows a second modification of the second exemplary embodiment
• Figure 7 shows a possible surface design.
• FIG. 1 the basic structure of an integrated circuit arrangement is shown.
• An integrated circuit is built up in a known manner on a substrate 1 in several layers, which are shown here as layers 2 and 3 as a minimal solution.
• layers 2 and 3 are shown here as layers 2 and 3 as a minimal solution.
• Well over two shifts are currently common.
• At least the invention can only be meaningfully applied from two layers, since only then is there a layer that can be removed in order to analyze the layer underneath.
• FIG. 2 it is shown that on the side used for layers 2 and 3, a material 4 is applied, which during
• Hardening leads to a tension of the substrate 1, so that there is a surface that is curved at least in one direction forms.
• Commercial epoxy-based adhesives can be used for this.
• curvature in two directions is also possible.
• deformations of at least 1 ⁇ m can easily be achieved over the entire chip area. It should be noted that the chip could possibly be thinned more in order to achieve greater deformation.
• a torsion-like deformation, as shown in FIG. 7, should also be considered. For example, as indicated by the arrows shown, it is possible to twist opposite sides in opposite directions.
• parts A can be removed from the substrate surface, as indicated by dashed lines in FIG , This is done either by obliquely etching or grinding edge regions of the substrate as shown on the left side of FIG. 2 or by etching out or grinding individual parts A as shown on the right side of FIG. In this way it is ensured that it is not possible, or at least very expensive, to bring the substrate 1 back into a flat shape after deformation.
• the integrated circuit arrangement is constructed such that the substrate is applied to a carrier 5, the carrier 5 forming the substrate.
• Recesses could also be provided here, which are not shown in connection with FIG. 4.
• the carrier 5 is not only deformed on one surface as shown in FIG. 4, but is also made overall from a flat shape to a curved or twisted shape.
• elevations 6 are formed on the surface of the carrier, which, when brought together with the substrate 1, deforms the substrate 1 together with its applied layers. This can take place in particular in that a material 4 similar to that in the exemplary embodiment shown in FIG. 2 is introduced into the spaces between the elevations, the substrate and the carrier, which leads to the bracing of the substrate when drying.
• the basic idea of the invention resides in permanently deforming the substrate carrying an integrated circuit in such a way that the layers applied to the substrate cannot be selectively removed by means of a grinding process.

Landscapes

• Semiconductor Integrated Circuits (AREA)
• Wire Bonding (AREA)
• Die Bonding (AREA)
• Mechanical Treatment Of Semiconductor (AREA)
• Structure Of Printed Boards (AREA)
• Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Priority Applications (3)

Applications Claiming Priority (2)

Related Child Applications (1)

Publications (2)

Family

ID=7674011

Family Applications (1)

Country Status (7)

Cited By (1)

Families Citing this family (3)

Family Cites Families (17)

• 2001
  • 2001-02-14 DE DE10106836A patent/DE10106836B4/de not_active Expired - Fee Related
• 2002
  • 2002-01-22 JP JP2002564764A patent/JP3979942B2/ja not_active Expired - Fee Related
  • 2002-01-22 EP EP02703497A patent/EP1360718A2/de not_active Withdrawn
  • 2002-01-22 CN CNB028049780A patent/CN100392846C/zh not_active Expired - Fee Related
  • 2002-01-22 WO PCT/DE2002/000191 patent/WO2002065548A2/de not_active Ceased
  • 2002-01-31 TW TW091101654A patent/TW519759B/zh not_active IP Right Cessation
• 2003
  • 2003-08-14 US US10/641,264 patent/US7199448B2/en not_active Expired - Fee Related

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