WO2005078794A1 - Nicht planar ausgebildete integrierte schaltungsanordnung - Google Patents
Nicht planar ausgebildete integrierte schaltungsanordnung Download PDFInfo
- Publication number
- WO2005078794A1 WO2005078794A1 PCT/DE2005/000248 DE2005000248W WO2005078794A1 WO 2005078794 A1 WO2005078794 A1 WO 2005078794A1 DE 2005000248 W DE2005000248 W DE 2005000248W WO 2005078794 A1 WO2005078794 A1 WO 2005078794A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- integrated circuit
- substrate
- carrier
- circuit arrangement
- circuit system
- Prior art date
Links
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 239000003251 chemically resistant material Substances 0.000 claims abstract description 5
- 239000000919 ceramic Substances 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 9
- 238000004458 analytical method Methods 0.000 description 8
- 238000000034 method Methods 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 6
- 238000005530 etching Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 238000010884 ion-beam technique Methods 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010137 moulding (plastic) Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/57—Protection from inspection, reverse engineering or tampering
- H01L23/573—Protection from inspection, reverse engineering or tampering using passive means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Definitions
- the present invention relates to an integrated circuit arrangement which has effective protection against attacks on a circuit integrated in the circuit arrangement.
- the material that covers the surface of the chip is dissolved.
- This material can either be a plastic molding compound, which forms the housing of the semiconductor component, or a so-called “globe top", which only serves to protect the chip surface and the electrical connections against mechanical ones To protect damage.
- the passivation layer of the semiconductor chip is generally accessible. This can be selectively removed using etching, laser or FIB (Focused Ion Beam) methods.
- the structure of the integrated circuit can be subsequently analyzed by removing and photographing the exposed layer in layers.
- the applicant is aware of methods for producing integrated circuit arrangements in which the substrate on which an integrated circuit is formed is not planar, at least in one direction of propagation.
- the protective layer covering the integrated circuit arrangement can still be removed by means of an etching process, so that access to the layers of the substrate having the integrated circuit is made possible.
- the object of the present invention is therefore to propose an integrated circuit arrangement with an integrated circuit formed in a substrate, in which exposure of the substrate is made more difficult and thus improved protection against analysis is provided.
- the integrated circuit arrangement according to the invention comprises a curved substrate on which an integrated circuit is formed in, for example, several layers.
- the substrate with the side having the integrated circuit is arranged on a chemically resistant carrier.
- the carrier consists of ceramic and has a high chemical resistance, so that the carrier cannot be detached by the conventional etching processes.
- a surface of the carrier facing the substrate is adapted to the curvature of the substrate and can be connected to the substrate in a simple manner in terms of process technology.
- the curved support additionally fixes the curvature of the substrate, so that the substrate can no longer be brought into a planar shape by, for example, exerting pressure.
- This figure shows in cross section an integrated circuit arrangement with a substrate arranged on a carrier.
- a substrate 2 which is generally composed of several layers, has an integrated circuit constructed in a known manner.
- the substrate 2 is curved at least in one direction of propagation.
- the side 3 of the substrate 2 which has the integrated circuit and on which, for example, semiconductor components of the integrated circuit are formed and which is convex due to the curvature of the substrate 2 is connected to a carrier 4.
- the carrier 4 has a cavity 5 corresponding to the dimensions of the convex surface of the substrate, so that a connection can be achieved in a simple manner, for example by using an adhesive.
- the cavity 5 formed in the carrier 4 is dimensioned such that the substrate 2 is completely accommodated in the cavity 5 of the carrier 4.
- the carrier 4 is also planar on a side 6 facing away from the substrate 2.
- the carrier 4 is made of a chemically resistant material, it cannot be removed by etching.
- the curved carrier 4 fixes the substrate curvature, so that the substrate 2 can no longer be placed in a planar shape.
- the carrier 4 could only be removed by a grinding process, which then also simultaneously destroys the substrate layers arranged below the carrier 4.
- the invention enables very reliable protection against analysis by the combination of the use of a curved substrate, which is arranged with the side having the integrated circuit on a chemically resistant carrier. LIST OF REFERENCE NUMBERS
Abstract
Description
Claims
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/598,054 US7633149B2 (en) | 2004-02-16 | 2005-02-14 | Integrated circuit arrangement |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102004007690A DE102004007690B3 (de) | 2004-02-16 | 2004-02-16 | Integrierte Schaltungsanordnung |
DE102004007690.1 | 2004-02-16 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2005078794A1 true WO2005078794A1 (de) | 2005-08-25 |
Family
ID=34853494
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/DE2005/000248 WO2005078794A1 (de) | 2004-02-16 | 2005-02-14 | Nicht planar ausgebildete integrierte schaltungsanordnung |
Country Status (3)
Country | Link |
---|---|
US (1) | US7633149B2 (de) |
DE (1) | DE102004007690B3 (de) |
WO (1) | WO2005078794A1 (de) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7566585B2 (en) | 2005-10-25 | 2009-07-28 | Infineon Technologies Ag | Semiconductor component and method for production of a semiconductor component |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101378418B1 (ko) * | 2007-11-01 | 2014-03-27 | 삼성전자주식회사 | 이미지센서 모듈 및 그 제조방법 |
US8691663B2 (en) * | 2009-11-06 | 2014-04-08 | Alliance For Sustainable Energy, Llc | Methods of manipulating stressed epistructures |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60747A (ja) * | 1983-06-17 | 1985-01-05 | Hitachi Ltd | レジンモ−ルドicパツケ−ジ |
JPS61101036A (ja) * | 1984-10-24 | 1986-05-19 | Hitachi Ltd | 半導体装置 |
JPH01244625A (ja) * | 1988-03-26 | 1989-09-29 | Mitsubishi Electric Corp | 半導体装置 |
EP1047128A2 (de) * | 1999-04-23 | 2000-10-25 | Sharp Kabushiki Kaisha | Verbogenes Halbleiterbauelement und dessen Herstellungsverfahren |
WO2002065548A2 (de) * | 2001-02-14 | 2002-08-22 | Infineon Technologies Ag | Integrierte schaltungsanordnung aus einem flächigen substrat |
JP2003174114A (ja) * | 2001-12-07 | 2003-06-20 | Fuji Electric Co Ltd | 半導体回路基板および半導体装置 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5027191A (en) * | 1989-05-11 | 1991-06-25 | Westinghouse Electric Corp. | Cavity-down chip carrier with pad grid array |
DE4415132C2 (de) * | 1994-04-29 | 1997-03-20 | Siemens Ag | Verfahren zur formgebenden Bearbeitung von dünnen Wafern und Solarzellen aus kristallinem Silizium |
JPH1140702A (ja) * | 1997-07-23 | 1999-02-12 | Nec Corp | 半導体素子実装用基板、および半導体装置の製造方法 |
US6429530B1 (en) * | 1998-11-02 | 2002-08-06 | International Business Machines Corporation | Miniaturized chip scale ball grid array semiconductor package |
TW460927B (en) * | 1999-01-18 | 2001-10-21 | Toshiba Corp | Semiconductor device, mounting method for semiconductor device and manufacturing method for semiconductor device |
JP3627565B2 (ja) * | 1999-03-30 | 2005-03-09 | セイコーエプソン株式会社 | 半導体装置およびその製造方法 |
JP3726998B2 (ja) * | 1999-04-01 | 2005-12-14 | 株式会社村田製作所 | 表面波装置 |
JP3265301B2 (ja) * | 2000-06-05 | 2002-03-11 | 株式会社東芝 | 半導体装置とその製造方法 |
DE10043955A1 (de) * | 2000-09-06 | 2002-04-04 | Infineon Technologies Ag | Halbleiterchip mit einer Schutzabdeckung und zugehöriges Herstellungsverfahren |
JP2002353369A (ja) * | 2001-05-28 | 2002-12-06 | Sharp Corp | 半導体パッケージおよびその製造方法 |
DE10126508B4 (de) * | 2001-05-30 | 2008-11-13 | Infineon Technologies Ag | Vorrichtung mit mittels Spritzgusstechnik verpackten elektronischen Bauteilen, Spritzgusswerkzeug und Verfahren zum Verpacken von elektronischen Bauteilen |
US6791072B1 (en) * | 2002-05-22 | 2004-09-14 | National Semiconductor Corporation | Method and apparatus for forming curved image sensor module |
DE10352285A1 (de) * | 2003-11-08 | 2005-06-09 | Dr. Johannes Heidenhain Gmbh | Optoelektronische Bauelementanordnung |
-
2004
- 2004-02-16 DE DE102004007690A patent/DE102004007690B3/de not_active Expired - Fee Related
-
2005
- 2005-02-14 US US10/598,054 patent/US7633149B2/en not_active Expired - Fee Related
- 2005-02-14 WO PCT/DE2005/000248 patent/WO2005078794A1/de active Application Filing
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60747A (ja) * | 1983-06-17 | 1985-01-05 | Hitachi Ltd | レジンモ−ルドicパツケ−ジ |
JPS61101036A (ja) * | 1984-10-24 | 1986-05-19 | Hitachi Ltd | 半導体装置 |
JPH01244625A (ja) * | 1988-03-26 | 1989-09-29 | Mitsubishi Electric Corp | 半導体装置 |
EP1047128A2 (de) * | 1999-04-23 | 2000-10-25 | Sharp Kabushiki Kaisha | Verbogenes Halbleiterbauelement und dessen Herstellungsverfahren |
WO2002065548A2 (de) * | 2001-02-14 | 2002-08-22 | Infineon Technologies Ag | Integrierte schaltungsanordnung aus einem flächigen substrat |
JP2003174114A (ja) * | 2001-12-07 | 2003-06-20 | Fuji Electric Co Ltd | 半導体回路基板および半導体装置 |
Non-Patent Citations (4)
Title |
---|
PATENT ABSTRACTS OF JAPAN vol. 009, no. 110 (E - 314) 15 May 1985 (1985-05-15) * |
PATENT ABSTRACTS OF JAPAN vol. 010, no. 283 (E - 440) 26 September 1986 (1986-09-26) * |
PATENT ABSTRACTS OF JAPAN vol. 013, no. 581 (E - 865) 21 December 1989 (1989-12-21) * |
PATENT ABSTRACTS OF JAPAN vol. 2003, no. 10 8 October 2003 (2003-10-08) * |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7566585B2 (en) | 2005-10-25 | 2009-07-28 | Infineon Technologies Ag | Semiconductor component and method for production of a semiconductor component |
Also Published As
Publication number | Publication date |
---|---|
US7633149B2 (en) | 2009-12-15 |
DE102004007690B3 (de) | 2005-10-13 |
US20080237837A1 (en) | 2008-10-02 |
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