TW519759B - Integrated circuit arrangement comprising a sheet-like substrate - Google Patents

Integrated circuit arrangement comprising a sheet-like substrate Download PDF

Info

Publication number
TW519759B
TW519759B TW091101654A TW91101654A TW519759B TW 519759 B TW519759 B TW 519759B TW 091101654 A TW091101654 A TW 091101654A TW 91101654 A TW91101654 A TW 91101654A TW 519759 B TW519759 B TW 519759B
Authority
TW
Taiwan
Prior art keywords
substrate
integrated circuit
circuit configuration
patent application
item
Prior art date
Application number
TW091101654A
Other languages
English (en)
Chinese (zh)
Inventor
Markus Janke
Peter Laackmann
Original Assignee
Infineon Technologies Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag filed Critical Infineon Technologies Ag
Application granted granted Critical
Publication of TW519759B publication Critical patent/TW519759B/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/40—Arrangements for protection of devices protecting against tampering, e.g. unauthorised inspection or reverse engineering
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Structure Of Printed Boards (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
TW091101654A 2001-02-14 2002-01-31 Integrated circuit arrangement comprising a sheet-like substrate TW519759B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE10106836A DE10106836B4 (de) 2001-02-14 2001-02-14 Integrierte Schaltungsanordnung aus einem flächigen Substrat

Publications (1)

Publication Number Publication Date
TW519759B true TW519759B (en) 2003-02-01

Family

ID=7674011

Family Applications (1)

Application Number Title Priority Date Filing Date
TW091101654A TW519759B (en) 2001-02-14 2002-01-31 Integrated circuit arrangement comprising a sheet-like substrate

Country Status (7)

Country Link
US (1) US7199448B2 (https=)
EP (1) EP1360718A2 (https=)
JP (1) JP3979942B2 (https=)
CN (1) CN100392846C (https=)
DE (1) DE10106836B4 (https=)
TW (1) TW519759B (https=)
WO (1) WO2002065548A2 (https=)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102004004289A1 (de) 2004-01-28 2005-08-25 Infineon Technologies Ag Integrierte Schaltungsanordnung
DE102004007690B3 (de) 2004-02-16 2005-10-13 Infineon Technologies Ag Integrierte Schaltungsanordnung
US8691663B2 (en) * 2009-11-06 2014-04-08 Alliance For Sustainable Energy, Llc Methods of manipulating stressed epistructures
JP5601384B2 (ja) * 2011-02-08 2014-10-08 富士電機株式会社 半導体モジュール用放熱板の製造方法、その放熱板およびその放熱板を用いた半導体モジュール

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4021097A (en) * 1976-03-08 1977-05-03 Sperry Rand Corporation Distributive tee coupler
JPS58164231A (ja) 1982-03-25 1983-09-29 Toshiba Corp 半導体装置の製造方法
JPH01244625A (ja) * 1988-03-26 1989-09-29 Mitsubishi Electric Corp 半導体装置
JP3360105B2 (ja) * 1994-03-04 2002-12-24 富士通株式会社 半導体装置の製造方法
JP3393233B2 (ja) * 1994-06-23 2003-04-07 ソニー株式会社 記録再生用カセットの基板取付構造
JPH08288424A (ja) * 1995-04-18 1996-11-01 Nec Corp 半導体装置
US6027958A (en) * 1996-07-11 2000-02-22 Kopin Corporation Transferred flexible integrated circuit
US5955776A (en) * 1996-12-04 1999-09-21 Ball Semiconductor, Inc. Spherical shaped semiconductor integrated circuit
JP2845232B2 (ja) 1997-01-13 1999-01-13 日本電気株式会社 半導体装置
JP3400329B2 (ja) * 1998-01-07 2003-04-28 日本電信電話株式会社 半導体装置
DE59813938D1 (de) 1998-08-19 2007-04-19 Infineon Technologies Ag Halbleiterchip mit Oberflächenabdeckung gegen optische Untersuchung der Schaltungsstruktur
US6500759B1 (en) * 1998-10-05 2002-12-31 Seiko Epson Corporation Protective layer having compression stress on titanium layer in method of making a semiconductor device
JP3720599B2 (ja) * 1998-10-07 2005-11-30 日本電信電話株式会社 半導体装置
TW460927B (en) * 1999-01-18 2001-10-21 Toshiba Corp Semiconductor device, mounting method for semiconductor device and manufacturing method for semiconductor device
JP3515012B2 (ja) 1999-04-23 2004-04-05 シャープ株式会社 半導体装置およびその製造方法
JP3553457B2 (ja) 2000-03-31 2004-08-11 シャープ株式会社 半導体装置およびその製造方法
JP3265301B2 (ja) * 2000-06-05 2002-03-11 株式会社東芝 半導体装置とその製造方法

Also Published As

Publication number Publication date
CN1541413A (zh) 2004-10-27
JP3979942B2 (ja) 2007-09-19
DE10106836B4 (de) 2009-01-22
DE10106836A1 (de) 2002-09-05
EP1360718A2 (de) 2003-11-12
US20040070052A1 (en) 2004-04-15
CN100392846C (zh) 2008-06-04
WO2002065548A3 (de) 2002-10-17
US7199448B2 (en) 2007-04-03
WO2002065548A2 (de) 2002-08-22
JP2004523904A (ja) 2004-08-05

Similar Documents

Publication Publication Date Title
CN106250806B (zh) 具有中介结构的指纹感测装置
TW420867B (en) Semiconductor device and the manufacturing method thereof
TW447025B (en) Process for precision alignment of chips for mounting on a substrate
TWI310521B (en) Structure of sweep-type fingerprint sensing chip capable of resisting electrostatic discharge (esd) and method of fabricating the same
TW201133714A (en) Wafer and method for forming the same
TW519759B (en) Integrated circuit arrangement comprising a sheet-like substrate
JP5880499B2 (ja) 振動式圧力センサ及びその製造方法
TW200304425A (en) Corrugated diaphragm
TW544897B (en) Circuit arrangement and method for checking the authenticity of said circuit arrangement
TW200834777A (en) Method and system for detecting existence of an undesirable particle during semiconductor fabrication
CN111383953B (zh) 用于制造半导体装置的方法和系统
TW406302B (en) Method of fabricating semiconductor substrate
TWI222173B (en) Method of making a package structure by dicing a wafer from the backside surface thereof
CN101545920A (zh) 加速度传感器装置
JP4147187B2 (ja) 透過性基板上のカラー画像センサの製造方法
TW201119415A (en) Acoustics transducer
JP2005501422A (ja) 薄化前に接触孔が開けられるカラー画像センサの製造方法
JP2004363517A (ja) 半導体ウェハのチップ化方法
JP3392069B2 (ja) 半導体加速度センサおよびその製造方法
CN1165874C (zh) 加强的集成电路
TW490789B (en) Semiconductor device having chip-on-chip structure
JP2000112825A (ja) 半導体装置
CN107169416A (zh) 超声波指纹传感器及其制造方法
JPH05114593A (ja) 半導体ウエハーの研削方法
JP3657817B2 (ja) 研削切断方法

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MM4A Annulment or lapse of patent due to non-payment of fees