DE10106836B4 - Integrierte Schaltungsanordnung aus einem flächigen Substrat - Google Patents

Integrierte Schaltungsanordnung aus einem flächigen Substrat Download PDF

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Publication number
DE10106836B4
DE10106836B4 DE10106836A DE10106836A DE10106836B4 DE 10106836 B4 DE10106836 B4 DE 10106836B4 DE 10106836 A DE10106836 A DE 10106836A DE 10106836 A DE10106836 A DE 10106836A DE 10106836 B4 DE10106836 B4 DE 10106836B4
Authority
DE
Germany
Prior art keywords
substrate
integrated circuit
circuit arrangement
arrangement according
flat substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE10106836A
Other languages
German (de)
English (en)
Other versions
DE10106836A1 (de
Inventor
Marcus Janke
Peter Laackmann
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to DE10106836A priority Critical patent/DE10106836B4/de
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Priority to EP02703497A priority patent/EP1360718A2/de
Priority to CNB028049780A priority patent/CN100392846C/zh
Priority to JP2002564764A priority patent/JP3979942B2/ja
Priority to PCT/DE2002/000191 priority patent/WO2002065548A2/de
Priority to TW091101654A priority patent/TW519759B/zh
Publication of DE10106836A1 publication Critical patent/DE10106836A1/de
Priority to US10/641,264 priority patent/US7199448B2/en
Application granted granted Critical
Publication of DE10106836B4 publication Critical patent/DE10106836B4/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/40—Arrangements for protection of devices protecting against tampering, e.g. unauthorised inspection or reverse engineering
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Structure Of Printed Boards (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE10106836A 2001-02-14 2001-02-14 Integrierte Schaltungsanordnung aus einem flächigen Substrat Expired - Fee Related DE10106836B4 (de)

Priority Applications (7)

Application Number Priority Date Filing Date Title
DE10106836A DE10106836B4 (de) 2001-02-14 2001-02-14 Integrierte Schaltungsanordnung aus einem flächigen Substrat
CNB028049780A CN100392846C (zh) 2001-02-14 2002-01-22 包合薄板状基材之集成电路配置
JP2002564764A JP3979942B2 (ja) 2001-02-14 2002-01-22 平坦な基板を備える集積回路装置及び集積回路装置を製作する方法
PCT/DE2002/000191 WO2002065548A2 (de) 2001-02-14 2002-01-22 Integrierte schaltungsanordnung aus einem flächigen substrat
EP02703497A EP1360718A2 (de) 2001-02-14 2002-01-22 Integrierte schaltungsanordnung aus einem flächigen substrat
TW091101654A TW519759B (en) 2001-02-14 2002-01-31 Integrated circuit arrangement comprising a sheet-like substrate
US10/641,264 US7199448B2 (en) 2001-02-14 2003-08-14 Integrated circuit configuration comprising a sheet-like substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE10106836A DE10106836B4 (de) 2001-02-14 2001-02-14 Integrierte Schaltungsanordnung aus einem flächigen Substrat

Publications (2)

Publication Number Publication Date
DE10106836A1 DE10106836A1 (de) 2002-09-05
DE10106836B4 true DE10106836B4 (de) 2009-01-22

Family

ID=7674011

Family Applications (1)

Application Number Title Priority Date Filing Date
DE10106836A Expired - Fee Related DE10106836B4 (de) 2001-02-14 2001-02-14 Integrierte Schaltungsanordnung aus einem flächigen Substrat

Country Status (7)

Country Link
US (1) US7199448B2 (https=)
EP (1) EP1360718A2 (https=)
JP (1) JP3979942B2 (https=)
CN (1) CN100392846C (https=)
DE (1) DE10106836B4 (https=)
TW (1) TW519759B (https=)
WO (1) WO2002065548A2 (https=)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102004004289A1 (de) 2004-01-28 2005-08-25 Infineon Technologies Ag Integrierte Schaltungsanordnung
DE102004007690B3 (de) 2004-02-16 2005-10-13 Infineon Technologies Ag Integrierte Schaltungsanordnung
US8691663B2 (en) * 2009-11-06 2014-04-08 Alliance For Sustainable Energy, Llc Methods of manipulating stressed epistructures
JP5601384B2 (ja) * 2011-02-08 2014-10-08 富士電機株式会社 半導体モジュール用放熱板の製造方法、その放熱板およびその放熱板を用いた半導体モジュール

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH087526A (ja) * 1994-06-23 1996-01-12 Sony Corp 記録再生用カセットの基板取付構造
US5783845A (en) * 1994-03-04 1998-07-21 Fujitsu Limited Semiconductor device and its manufacture utilizing crystal orientation dependence of impurity concentration
JPH11204566A (ja) * 1998-01-07 1999-07-30 Nippon Telegr & Teleph Corp <Ntt> 半導体装置
US5955776A (en) * 1996-12-04 1999-09-21 Ball Semiconductor, Inc. Spherical shaped semiconductor integrated circuit
WO2000021121A1 (en) * 1998-10-05 2000-04-13 Seiko Epson Corporation Semiconductor device and method for producing the same
JP2000112825A (ja) * 1998-10-07 2000-04-21 Nippon Telegr & Teleph Corp <Ntt> 半導体装置
EP1047128A2 (en) * 1999-04-23 2000-10-25 Sharp Kabushiki Kaisha Warped semiconductor device and method of manufacturing the same

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4021097A (en) * 1976-03-08 1977-05-03 Sperry Rand Corporation Distributive tee coupler
JPS58164231A (ja) 1982-03-25 1983-09-29 Toshiba Corp 半導体装置の製造方法
JPH01244625A (ja) * 1988-03-26 1989-09-29 Mitsubishi Electric Corp 半導体装置
JPH08288424A (ja) * 1995-04-18 1996-11-01 Nec Corp 半導体装置
US6027958A (en) * 1996-07-11 2000-02-22 Kopin Corporation Transferred flexible integrated circuit
JP2845232B2 (ja) 1997-01-13 1999-01-13 日本電気株式会社 半導体装置
DE59813938D1 (de) 1998-08-19 2007-04-19 Infineon Technologies Ag Halbleiterchip mit Oberflächenabdeckung gegen optische Untersuchung der Schaltungsstruktur
TW460927B (en) * 1999-01-18 2001-10-21 Toshiba Corp Semiconductor device, mounting method for semiconductor device and manufacturing method for semiconductor device
JP3553457B2 (ja) 2000-03-31 2004-08-11 シャープ株式会社 半導体装置およびその製造方法
JP3265301B2 (ja) * 2000-06-05 2002-03-11 株式会社東芝 半導体装置とその製造方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5783845A (en) * 1994-03-04 1998-07-21 Fujitsu Limited Semiconductor device and its manufacture utilizing crystal orientation dependence of impurity concentration
JPH087526A (ja) * 1994-06-23 1996-01-12 Sony Corp 記録再生用カセットの基板取付構造
US5955776A (en) * 1996-12-04 1999-09-21 Ball Semiconductor, Inc. Spherical shaped semiconductor integrated circuit
JPH11204566A (ja) * 1998-01-07 1999-07-30 Nippon Telegr & Teleph Corp <Ntt> 半導体装置
WO2000021121A1 (en) * 1998-10-05 2000-04-13 Seiko Epson Corporation Semiconductor device and method for producing the same
JP2000112825A (ja) * 1998-10-07 2000-04-21 Nippon Telegr & Teleph Corp <Ntt> 半導体装置
EP1047128A2 (en) * 1999-04-23 2000-10-25 Sharp Kabushiki Kaisha Warped semiconductor device and method of manufacturing the same

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
JP 08-007 526 A in Pat. Abstr. of Japan
JP 08007526 A in: Patent Abstracts of Japan; *

Also Published As

Publication number Publication date
CN1541413A (zh) 2004-10-27
JP3979942B2 (ja) 2007-09-19
DE10106836A1 (de) 2002-09-05
EP1360718A2 (de) 2003-11-12
US20040070052A1 (en) 2004-04-15
CN100392846C (zh) 2008-06-04
WO2002065548A3 (de) 2002-10-17
US7199448B2 (en) 2007-04-03
WO2002065548A2 (de) 2002-08-22
TW519759B (en) 2003-02-01
JP2004523904A (ja) 2004-08-05

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8364 No opposition during term of opposition
R082 Change of representative

Representative=s name: EPPING HERMANN FISCHER, PATENTANWALTSGESELLSCH, DE

Representative=s name: EPPING HERMANN FISCHER, PATENTANWALTSGESELLSCHAFT

R119 Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee