WO2002037556A1 - Procede de fabrication d'une structure empilee comprenant une couche mince adherant a un substrat cible - Google Patents
Procede de fabrication d'une structure empilee comprenant une couche mince adherant a un substrat cible Download PDFInfo
- Publication number
- WO2002037556A1 WO2002037556A1 PCT/FR2001/003401 FR0103401W WO0237556A1 WO 2002037556 A1 WO2002037556 A1 WO 2002037556A1 FR 0103401 W FR0103401 W FR 0103401W WO 0237556 A1 WO0237556 A1 WO 0237556A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- substrate
- thin layer
- contact
- layer
- target substrate
- Prior art date
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 224
- 238000000034 method Methods 0.000 title claims abstract description 104
- 239000010409 thin film Substances 0.000 title abstract description 23
- 229910052710 silicon Inorganic materials 0.000 claims description 64
- 239000010703 silicon Substances 0.000 claims description 64
- 239000000463 material Substances 0.000 claims description 47
- 238000010438 heat treatment Methods 0.000 claims description 29
- 239000000126 substance Substances 0.000 claims description 25
- 238000011282 treatment Methods 0.000 claims description 23
- 230000001464 adherent effect Effects 0.000 claims description 21
- 238000004519 manufacturing process Methods 0.000 claims description 18
- 238000005498 polishing Methods 0.000 claims description 16
- 229910052594 sapphire Inorganic materials 0.000 claims description 15
- 239000010980 sapphire Substances 0.000 claims description 15
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 12
- 230000010070 molecular adhesion Effects 0.000 claims description 12
- 239000004065 semiconductor Substances 0.000 claims description 12
- 230000007547 defect Effects 0.000 claims description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 9
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 9
- 239000000853 adhesive Substances 0.000 claims description 5
- 230000001070 adhesive effect Effects 0.000 claims description 5
- 230000008859 change Effects 0.000 claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 238000009966 trimming Methods 0.000 claims description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 239000010408 film Substances 0.000 description 141
- 239000010410 layer Substances 0.000 description 136
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 63
- 230000008569 process Effects 0.000 description 48
- 238000007789 sealing Methods 0.000 description 40
- 238000000926 separation method Methods 0.000 description 39
- 235000012431 wafers Nutrition 0.000 description 17
- 238000002513 implantation Methods 0.000 description 13
- 241000894007 species Species 0.000 description 12
- 230000003647 oxidation Effects 0.000 description 11
- 238000007254 oxidation reaction Methods 0.000 description 11
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 10
- 238000012546 transfer Methods 0.000 description 9
- 229910052739 hydrogen Inorganic materials 0.000 description 8
- 239000001257 hydrogen Substances 0.000 description 8
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Inorganic materials [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 8
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 7
- 238000002360 preparation method Methods 0.000 description 7
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 6
- 125000004429 atom Chemical group 0.000 description 6
- 238000005530 etching Methods 0.000 description 6
- 238000000227 grinding Methods 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 6
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 5
- 238000009499 grossing Methods 0.000 description 5
- 150000004767 nitrides Chemical class 0.000 description 5
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 4
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 4
- 238000004140 cleaning Methods 0.000 description 4
- 238000000407 epitaxy Methods 0.000 description 4
- 238000011084 recovery Methods 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 230000003746 surface roughness Effects 0.000 description 4
- 238000004381 surface treatment Methods 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 239000010432 diamond Substances 0.000 description 3
- 229910003460 diamond Inorganic materials 0.000 description 3
- 150000002431 hydrogen Chemical class 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 229910052763 palladium Inorganic materials 0.000 description 3
- 239000010453 quartz Substances 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- 239000003351 stiffener Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000003486 chemical etching Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 125000004435 hydrogen atom Chemical group [H]* 0.000 description 2
- 230000003993 interaction Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000004377 microelectronic Methods 0.000 description 2
- 229910003465 moissanite Inorganic materials 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 241000478345 Afer Species 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 125000004432 carbon atom Chemical group C* 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000012512 characterization method Methods 0.000 description 1
- 238000004581 coalescence Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 239000002178 crystalline material Substances 0.000 description 1
- 230000032798 delamination Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- -1 hydrogen ions Chemical class 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 238000010849 ion bombardment Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000002787 reinforcement Effects 0.000 description 1
- 238000009877 rendering Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000011343 solid material Substances 0.000 description 1
- 239000002887 superconductor Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
Definitions
- the present invention relates to a method of manufacturing a stacked structure comprising a thin layer adhering to a target substrate.
- the invention is particularly applicable in the field of semiconductors.
- Document FR-A-2 681 472 (corresponding to American patent 5 374 564) describes a process for manufacturing thin films of semiconductor material.
- This document discloses that the implantation of a rare gas and / or hydrogen in a substrate of semiconductor material is capable of creating a weakened layer which may include microcavities or microbubbles (also designated by the term "platelets” in Anglo-Saxon terminology) at a depth close to the average penetration depth of the implanted ions.
- This substrate is brought into intimate contact, by its implanted face with a support serving as a stiffener.
- a heat treatment can be applied at a temperature sufficient to induce an interaction (or coalescence) between the microcavities or the microbubbles leading to a separation or fracture of the semiconductor substrate into two parts: a semi-thin film
- the heat treatment is such that the interaction between the microbubbles or microcavities created by implantation induces a separation between the thin film and the rest of the substrate. There is therefore transfer of a thin film from an initial substrate to a stiffener serving as a support for this thin film.
- ion implantation any type of introduction of the species defined above alone or in combination. These include ion bombardment, scattering, etc.
- This process can also be applied to the manufacture of a thin film of solid material other than a semiconductor material (a conductive or dielectric material), crystalline or not.
- This film can be monolayer or multilayer (see for example the document FR-A-2,748,850).
- This process makes it possible to produce, at an advantageous cost, wafers, for example SOI wafers, of electronic quality by transfer of a silicon film onto a silicon substrate covered with an oxide layer.
- Document FR-A-2 725 074 discloses a process for manufacturing a structure comprising a thin semiconductor film adhering to a target substrate.
- the thin film is linked to an initial substrate by a first binding energy.
- the thin film is then transferred from the initial substrate to the substrate target by using pullout forces, making it possible to overcome the first binding energy, and an adhesion of the thin film on the target substrate.
- This transfer of the thin film can be done by means of an intermediate or manipulating substrate which is in turn separated from the thin film by tearing.
- This process requires controlling the bonding energies between the various sealing interfaces associated with the thin film to allow successive tearing.
- BESOI does not use the separation of a thin film by implantation of gaseous species.
- One of its main characteristics is the use of a crystalline barrier layer allowing a so-called selective chemical attack while supporting a monocrystalline layer, typically silicon.
- This barrier layer is a monocrystalline layer or an epitaxial layer. It may be a layer of doped silicon, a layer obtained by epitaxy of crystalline material of a different nature from that of the thin film.
- the known method for producing thin layer structures known as the direct method and described in FR-A-2 681 472, based on the implantation of hydrogen, molecular adhesion with a final support and separation in and / or at neighborhood of the implanted area, does not allow to easily obtain and / or with sufficient quality certain structures having specific properties.
- the direct process is not simply applicable and the technical solution to be provided, object of this invention, does not result from a simple adaptation of the process.
- a first case concerns the production of thin and / or very thin stacked film structures having a crystalline layer present on the surface of an amorphous layer.
- a first example is the production of films which must have thicknesses less than a few tens of nanometers, for example silicon films 20 nm thick on Si0 2 films 20 nm thick and adhering to a silicon support. founded. Bonding defects are then often revealed during the separation step of the direct process, which can be highlighted when the process implements a separation step comprising a heat treatment at low temperature.
- a second example is that where the structure in thin films having specific properties is subjected to heat treatments at temperatures higher than those of heat treatments undergone before, during or after the thinning of one of the substrates used (for example in using thinning by the direct process). Bonding defects, for example bubbles swollen with gas, may then appear to the detriment of the quality of the structure.
- a second case concerns the production of structures where the bonding forces are very low before the separation step by the direct process. For example, for certain conditions of surface preparation before contacting (cleaning, level of component preparation process from which a certain surface roughness results, etc.), the bonding between the final support and the generator plate of the film to be transferred have very low energy. The separation step of the direct process cannot then be carried out.
- a third case concerns the production of stacked structures of materials whose coefficients of thermal expansion are too different. If the material of the film to be transferred and the material of the final support have too different coefficients of thermal expansion, the bonding will fail before separation by the direct process if a heat treatment is applied to the bonding. This is for example the case of silicon and sapphire whose coefficients of thermal expansion are in a ratio of the order of 2.
- a fourth case concerns the production of structures where the bonding forces must be low or very low after the separation step by the direct process. It may be desirable for the sealing energy of the stacked structure to remain low after the step of separation by the direct process, or even less than that necessary for separation, to subsequently provide detachment at the bonding interface. This applies in particular when various treatments can strengthen the sealing interface.
- the thinning by sacrificial oxidation at 950 ° C. of a silicon surface film of an SOI structure, causes an increase in energy. of seal greater than 1 J / m 2 , which is unfavorable for the subsequent separation of the stacked structure from the target substrate.
- a fifth case concerns the realization of stacked structures of heterogeneous materials.
- materials of different natures for example silicon or thermal oxide (various dielectrics, metallic materials, semiconductors, superconductors, etc.) can be the cause of bonding defects highlighted during the direct process.
- the sealing of a silicon wafer covered with a silicon nitride film with a silicon nitride film itself covering a silicon wafer often results in bonding defects which are easily highlighted during the step. separation by the direct process.
- the term “blade” is understood here to mean a substrate or a film or a stacked structure covered on the surface by the cited film.
- a sixth case concerns the production of stacked structures in which a change in phase or in the nature of a material can occur.
- the use of certain materials is not compatible with the thermal budgets possibly employed in the direct process. So a structure stacked consisting of a silicon film, a palladium film and a silicon wafer produced, above 200 ° C., a silicide capable of giving good bonding. At higher temperature, the seal degrades, for example above 900 ° C., a temperature typically used to oxidize a silicon film in order to reduce its thickness.
- a metal mirror can be added by molecular adhesion to a silicon wafer. This metal mirror does not support heat treatment beyond a few tens of ° C, it is not possible to apply the thermal budgets which can be possibly used in the separation process.
- the direct process does not, in certain cases, make it possible to produce structures of stacked films with conservation of a specific surface, known as the front face.
- the structure thinned by the direct process exhibits after the separation step a surface roughness to be reduced as a function of the intended application.
- This reduction in roughness can be conventionally obtained for example by chemical mechanical polishing (CMP) in the case of silicon.
- CMP chemical mechanical polishing
- this polishing is either unsuitable (lack of efficiency) or too long (significant industrial cost).
- a monocrystalline Sic film by its polar nature has the characteristic of having, on one side, a surface consisting mainly of silicon atoms (so-called Si type surface) and, on the other side, a surface constituted mainly carbon atoms (so-called type C surface).
- Si type surface a surface consisting mainly of silicon atoms
- type C surface a surface constituted mainly carbon atoms
- the present invention overcomes the drawbacks of the prior art and provides a stacked structure comprising either a film having certain specific properties, or a film having at least one surface with specific property (s).
- the invention results from the surprising fact noted by the inventors that, unlike the direct process for which there is sealing on the target substrate and then thinning, when the thinning of the initial substrate takes place before the sealing of the thin layer on the target substrate , all the faults listed above can be avoided. To reverse these sealing and thinning steps, you must use one or more intermediate supports.
- the subject of the invention is therefore a method of manufacturing a stacked structure comprising at least one thin layer adhering to a target substrate, comprising the following steps: a) forming a thin layer from an initial substrate, the thin layer having a free face called the first contact face, b) adhering contact of the first contact face with a face of an intermediate support, the structure obtained being compatible with subsequent thinning of the initial substrate, c) thinning of said initial substrate for exposing a free face of the thin layer called the second contact face and opposite the first contact face, d) adherent contacting of one face of the target substrate with at least part of the second contact face, the structure obtained being compatible with a subsequent removal of all or part of the intermediate support, e) removal of at least part of the intermediate support allowing it to be obtained ion of said stacked structure.
- Thinning is understood in step c) or by shrinking in step e) any technique allowing to eliminate the initial substrate or the intermediate support. Mention may be made in particular of detachment, fracture (linked to the creation of a weakened zone by the introduction of gaseous species), mechanical and / or chemical etching. Depending on the type of thinning and shrinking, the substrate and the support can be reused.
- the target substrate is only a temporary support for the thin layer, said steps of the method being completely or partially repeated, the target substrate being assimilated to the initial substrate or to the intermediate support.
- the method according to the invention allows the transfer of the thin layer from one support to another support as many times as necessary to obtain a stacked structure having the desired characteristics and in particular a stack with technological levels of component.
- step b) and / or in step d) the compatibility of said structure can be obtained by the formation, in step a), of a thin layer making it possible to avoid adhesion defects respectively. during the thinning of step c) and during the removal of step e).
- This compatibility can result from the thickness given to the thin layer and / or from the material or materials constituting said thin layer.
- the nature of the intermediate support and / or of the target substrate, in contact with the thin layer can be chosen so as to avoid an incompatibility linked to a change of phase of materials of the structure obtained.
- the nature of the intermediate support and / or of the target substrate, in contact with the thin layer can be chosen so as to avoid a incompatibility linked to a heterogeneity of materials of the structure obtained.
- the nature of the intermediate support and / or of the target substrate, in contact with the thin layer can be chosen so as to avoid an incompatibility linked to a difference in coefficient of thermal expansion with the thin layer.
- the thin layer and / or the intermediate support and / or the target substrate may (may) comprise at least one additional layer having one (or more) contact face (s).
- the additional layer may be provided with all or part of at least one component.
- the additional layer may consist of an oxide or of polycrystalline silicon or of amorphous silicon.
- Steps a) and c) can be such that the first contact face of the thin layer and / or of the intermediate support has a roughness respectively lower than that of its second contact face and / or of the target substrate, the structural compatibility 1 step d) being obtained by adhering contact of the second contact face of the thin layer and removing the intermediate support.
- the adherent contact of the first contact face and / or of the second contact face of the thin layer allowing said compatibility in step b) and / or in step d) may result from the use of a treatment.
- a treatment allowing adherent contact.
- the treatment allowing the adherent contact can be chosen, alone or in combination, among the following treatments: mechanical-chemical and / or ionic polishing, interposition of an intermediate layer between a corresponding contact face of the thin layer and the intermediate support or the target substrate, heat treatment and chemical treatment. Treatment can be carried out at high temperature thanks to the compatibility of the structure.
- the adherent contacting of step b) and / or of step d) is carried out by molecular adhesion.
- the first contact face of the thin layer may have a surface polarity (polarity linked to the nature of the atoms of this surface) different from that of its second contact face, the structural compatibility of step d) being obtained by when the second contact face of the thin layer and the target substrate are brought into adherent contact, and thanks to the removal of the intermediate support from the first contact face of the thin layer which thus becomes a free face.
- the compatibility of the structure produced in step d) can be obtained by bringing the second contact face of the thin layer into adherent contact with the target substrate with a binding energy capable of possibly removing the target substrate after l 'step e).
- this binding energy is low.
- an intermediate step can be provided, consisting of producing elements in the second contact face of the thin layer and / or in the target substrate, the structure obtained after step d) being compatible with the presence of said elements. These elements can be cavities or all or part of components (microelectronics, optronics.) And can achieve a certain surface topology.
- an intermediate step can be provided, consisting of a trimming operation making it possible to isolate at least one zone from the second contact face, step d) bringing into adhesive contact at least one of these zones. with the target substrate. The trimming operation can possibly take place even before step a).
- Step a) can be carried out from a substrate covered with at least one layer of material.
- the method may include a. step consisting in eliminating the layer of material covering the substrate of step a).
- step a) comprises the introduction of gaseous species into the initial substrate, through one of its faces corresponding to said first contact face, to form a weakened layer separating said film from the rest of the initial substrate and which should lead to a fracture of the initial substrate during step c),
- Step c) consists in carrying out a treatment allowing the fracture of the initial substrate to be obtained at the level of the weakened layer.
- This treatment can for example be thermal and / or mechanical.
- the initial substrate can be monolayer or multilayer. It can in particular comprise an epitaxial layer. The same goes for the target substrate and for the intermediate support.
- the removal of at least part of the intermediate support can be carried out by introduction of gaseous species carried out either through the thin layer after contacting, or through the contact face of the intermediate support before or after it is brought into adherent contact with the first contact face of the thin layer, this introduction of gaseous species forming a weakened layer allowing the removal by fracture of part of the intermediate support possibly covered with a film of the thin layer.
- the intermediate support can be reused for example as a new support.
- the stacked structure obtained at the end of step e) is thinned on the side of the first contact face.
- the method can use an initial substrate of very good quality and therefore of high cost, such as, for example, monocrystalline silicon 300 mm in diameter, an intermediate support compatible with the initial substrate within the meaning of step b), by example a monocrystalline silicon substrate covered with a film of oxide Si0 2 , a target substrate in polycrystalline or monocrystalline silicon of lower quality than the silicon of the initial substrate, the thin layer comprising for example silicon oxide on silicon monocrystalline from the initial substrate.
- the target substrate could be other than silicon.
- the film obtained on the target substrate is then of very good quality.
- the initial substrate can be produced and, depending on its quality or cost, the intermediate support will be reusable or sacrificable.
- the thin layer can be a layer of material chosen from Si, GaN, SiC, LiNb0 3 , Ge, GaAs, InP, sapphire and semiconductors.
- a monocrystalline film of good crystalline quality can be transferred while the barrier layer for thinning the intermediate support is an amorphous layer.
- An intermediate recyclable support can be used, for example by controlling its sealing energy, if the intermediate substrate (quality, nature.) Is of significant cost.
- an intermediate support of polycrystalline SiC can be used for the transfer of a monocrystalline film of SiC of high cost and / or of high quality.
- control of the sealing energy can be ensured by controlling the roughness of an additional layer of Si0 2 deposited on the thin layer or on the intermediate support.
- a consumable film for example an oxide
- the principle of the invention can be applied to layers of other monocrystalline materials or not than silicon for (at least) one of the films of the stacked structure.
- the method can be applied to one. sapphire, SiC, GaN, LiNb0 3 , Ge, GaAs, InP film on any medium.
- This same principle can be applied to other types of target substrate than silicon, for example quartz or any substrate, advantageously a low-cost substrate (glass, plastic, ceramic.).
- This process can be applied to any type of semiconductor film, for example to III-V, II-VI and IV semiconductors or to a diamond, nitride film or to any type of film, for example oxides such as Al 2 0 3 , Zr0 2 , SrTi0 3 , LaAl0 3 , MgO, YBa x Cu y O z , SiO x N y , Ru0 2 or other materials, in particular piezoelectric, superconductive, insulating, metallic, pyroelectric, monocrystalline or not .
- This process can be applied to materials having surfaces with polar characters.
- FIG. 1 represents, in cross section, a substrate called the initial substrate to which the present invention applies,
- FIG. 2 represents, in cross section, the initial substrate covered with a layer of material and undergoing an ion implantation step during the implementation of the method according to the invention
- - Figure 3 illustrates the step of adhering contact of the initial substrate, via the layer of material, with an intermediate support according to the present invention
- - Figure 4 illustrates the step of removing at least part of the initial substrate according to the present invention
- FIG. 5 illustrates the step of bringing into adherent contact with a face of a target substrate, via a possible layer, according to the present invention
- FIG. 1 shows, in cross section, a silicon plate 1 725 ⁇ m thick and 200 mm in diameter constituting the initial substrate.
- the face 2 of the initial substrate 1 is oxidized to a thickness of 400 nm by heat treatment to provide an oxide layer 3 (see FIG. 2).
- gaseous species 4 are for example hydrogen ions implanted at an energy of 75 keV and at a dose of approximately 6.10 16 atoms / cm 2 .
- a weakened layer 5 is thus induced in a plane parallel to the face 2.
- the part of the substrate 1 between the face 2 and the weakened layer 5 constitutes a film 6.
- the assembly formed by the stack of film 6 and of oxide layer 3 constitutes a thin layer 7.
- the ' thin layer 7 has a free face 8 called the first contact face.
- the first contact face 8 is cleaned to make it suitable for molecular adhesion, for example by a preparation intended to make it sufficiently hydrophilic, and is brought into contact by molecular adhesion with a face 11 of another silicon plate 10 called intermediate support as shown in FIG. 3.
- a layer (adhesive, fusible layer.) capable of causing adhesion with the intermediate support can be produced with a view to adhesion with said support.
- the assembly constituted by the initial substrate 1 and the intermediate support 10 is subjected to a separation treatment, for example a heat treatment, in order to separate by fracture the film 6 from the rest 9 of the initial substrate 1 (see FIG. 4).
- the film 6 remains integral with the intermediate support 10 and has a free face 12.
- the sealing of the thin layer 7 on the intermediate support 10 is reinforced by a high temperature heat treatment.
- the molecular adhesion energy between these two parts can then reach, for example, a value of the order of 1.5 J / m 2 .
- the free face 12 of the film 6 is then smoothed by means of a surface treatment, for example by means of chemical-mechanical polishing, annealing for example under a partial or total atmosphere of hydrogen, or bombardment by isolated ions or in clusters or a chemical attack enabling all or part of the film 6 to be removed, thus freeing one face of the layer 3 in the case where the layer 3 is fairly selective with respect to the intermediate substrate.
- a surface treatment for example by means of chemical-mechanical polishing, annealing for example under a partial or total atmosphere of hydrogen, or bombardment by isolated ions or in clusters or a chemical attack enabling all or part of the film 6 to be removed, thus freeing one face of the layer 3 in the case where the layer 3 is fairly selective with respect to the intermediate substrate.
- It can be covered with a film 13 which can be multilayer and whose free face constitutes the second contact face 14 (see FIG. 5).
- the film 13 can be obtained by deposition, by heat treatment, by chemical treatment, etc.
- the sealing can be reinforced by a high temperature heat treatment.
- the intermediate support 10 is then removed for example by grinding completed by chemical attack.
- the oxide layer 3 can also be removed to obtain the stacked structure shown in the FIG. 6 and consisting of the target substrate 15, the film 13 and the film 6.
- the film 13 can be an oxide layer 20 nm thick produced thermally on the surface 12 of the film 6.
- the target substrate 15 can be made of silicon and surface oxidized (for example over 20 nm) or not.
- the sealing of the film 13 on the target substrate 15 can be reinforced by a treatment at 1100 ° C. or an adhesion of molecular type.
- sealing with adhesive or fusible material or the like can also be used. This produces a quality stacked structure while avoiding the appearance of bubbles - at the sealing interface.
- the intermediate support 10 is removed by grinding pursued by etching in a solution of tetramethylammonium hydroxide (TMAH) or potassium hydroxide, the oxide layer 3 serves then to etch stop silicon layer.
- This oxide layer 3 is eliminated by means of a solution based on hydrofluoric acid.
- the final thickness of the film 6 is adjusted by thinning, for example by means of sacrificial oxidation. A final thickness of 50 nm can be obtained with very good homogeneity.
- the oxide layer 3 formed on the initial substrate 1 is 400 nm thick.
- the implantation of hydrogen atoms is carried out under the same conditions as above.
- the film 6 is thinned, for example by sacrificial oxidation at 30 nm, and covered with an oxide 13 of 50 nm thick.
- the second contact face 14 is sealed to the target substrate 15. Treatments involving a high temperature can then be performed without risk of bubbles appearing at the bonding interface.
- a third implementation variant makes it possible to provide a sealing interface on the low energy target substrate.
- An oxide film 13 (see FIG. 5) 1000 nm thick is thermally formed.
- the free surface of the film 13 is then roughened with an average RMS value of 0.6 nm, for example by etching using a 10% hydrofluoric acid solution for 12 minutes.
- the second contact face 14 is sealed to the target substrate 15.
- This target substrate is a silicon substrate, which may have been surface oxidized, for example over 1000 nm.
- the sealing energy is adaptable as a function of the induced roughness and of a possible heat treatment. At this stage, it is possible to have a lower sealing energy than that necessary for the proper conduct of the direct process, called threshold sealing energy.
- the intermediate silicon support 10 is then removed, for example by grinding supplemented by a chemical attack in a TMAH or potassium hydroxide solution, the oxide layer 3 serving as an etching stop layer.
- This oxide layer 3 is removed by attack using a hydrofluoric acid solution and the final thickness of the film 6 is adjusted by thinning, for example by sacrificial oxidation.
- This implementation variant makes it possible to obtain a film 6 with a final thickness of 200 nm. approximately with very good homogeneity.
- the sealing energy with the target substrate 15 is low, which makes it possible to recover the film, subsequent to the process, by detachment from the target substrate 15.
- any or part of a component for example for microelectronics, optoelectronics, photovoltaic, sensor, etc. applications.
- Another application of this variant relates to high cost substrates.
- the initial plate can be of monocrystalline silicon, of high quality and / or of high cost, for example a plate of 300 mm in diameter.
- the target support can be made of monocrystalline silicon, of lower quality, or polycrystalline, of low cost.
- the obstacles overcome by this process will be, for example, adhesion defects or the appearance of bubbles observable in the direct process.
- the free face of the thin layer could be sealed directly on the target substrate, for example, in the case where the application requires conductive bonding.
- the free face of the thin layer or of the target substrate can be covered with an oxide film, for example to allow adhesion to the target substrate at low cost.
- the oxide allows a smoothing of the surface to be adhered and the target substrate will be polycrystalline silicon.
- the intermediate silicon substrate can be of low cost, for example polycrystalline.
- An additional layer for surface smoothing, for example made of Si0 2 will advantageously be deposited on the intermediate substrate.
- the intermediate substrate can be made of high quality silicon. It is then advantageous to recover it, for example by a lift-off technique or by implantation of gaseous species followed by separation or by a technique taking into account, for example, a fairly low adhesion energy after the step b) to allow separation, for example, mechanically, pneumatically.
- the initial substrate of high quality and / or high cost for example made of silicon 300 mm in diameter, will be advantageously recovered by using, for example, during step a) an implantation d 'gaseous species and during step c) separation from the rest of the initial substrate.
- a fourth implementation variant makes it possible to provide a sealing interface on the low energy target substrate in order to release the film and recover the target substrate.
- This variant of implementation which has a lot in common with the previous variant, makes it possible to subject the film fixed to the target substrate to a certain number of treatments, for example technological steps for producing electronic components including heat treatments at high temperature. These heat treatments would make it almost impossible to detach a film from a substrate obtained by the direct process.
- Control of the roughness of the surfaces before contacting at RMS values greater than 0.6 nm makes it possible to obtain such sealing energies despite heat treatments at a temperature greater than 900 ° C. These energies are then compatible in order to be able to release the so-called processed film, by detachment from the target substrate after the implementation of the technological steps for producing components. It is then possible to recover the target substrate, which can be advantageous depending on its cost.
- a target substrate of high cost By way of example of a target substrate of high cost, one can for example cite a silicon substrate 300 mm in diameter. Only the film part of the substrate is to be used for the components and it may be important to recover the initial substrate and / or the intermediate support and / or the target substrate.
- a fifth implementation variant applies to the case where the free surface of the film 6 delimited in the initial substrate is such that the direct adhesion to a target substrate is very low, for example because of the roughness on at least one of the two surfaces to put in contact. The sealing energy on the target substrate is then insufficient to allow the film to be separated by the direct process.
- the first contact face 8 is prepared to make it suitable for sealing, for example by depositing a sacrificial film and by an additional so-called planarization smoothing step.
- an intermediate support is used, for example a silicon substrate possibly covered with an oxide layer (for example 100 nm thick) and having a slightly rough contact face, for example with an average RMS value of 0.2 nm. The fact of sticking on a slightly rough surface ensures a sealing energy of sufficient value to allow thereafter the step of separation of the film 6 from the rest of the initial substrate.
- a high temperature heat treatment can be implemented, for example to reinforce the sealing or according to the operations necessary for the intended applications (diffusion of an implanted element, oxide film deposited thereafter , etc.).
- a surface treatment for example a chemical mechanical polishing, makes it possible to smooth all or part of the revealed surface of the film separated from its initial substrate.
- the free surface of the film 6 or of the additional film 13, called the second contact face 14 is sealed on the target silicon substrate which is for example covered with an oxide layer approximately 1000 nm thick. whose surface is roughened by chemical treatment.
- the seal is possibly adapted by heat treatment but retains a low value.
- the sealing energy between the film 6 or the film 13 and the target substrate 15 (or possibly its surface layer) is lower than that necessary for the proper conduct of the film-rest separation step from the initial substrate .
- the intermediate support 10 is then removed for example by grinding and chemical attack and the oxide layer 3 is removed by chemical attack.
- the final thickness of the film 6 is adjusted by thinning, for example by sacrificial oxidation. This thickness can be 50 nm with very good homogeneity.
- this fifth variant will be used when the initial surface roughness of the faces 2 or 8 corresponds to a topology etched on the initial substrate or on the initial thin layer or on the target substrate.
- An oxide film 13 (see FIG. 5) 1000 nm thick can be produced, for example thermally, on the surface of the film 6.
- the topology of the surface not initially allowing the direct process, can be reproduced at this stage, for example by a chemical etching treatment.
- this topology can be exclusively or partially carried out in the target substrate, whether or not covered with additional layers.
- a sixth variant of implementation differs from the previous variant in that the intermediate support can be recovered.
- This solution proves to be interesting because the intermediate support is an element which must have a certain quality to allow the separation of the films and its cost can then be significant.
- the method according to the invention allows for example and advantageously to conserve the sealing energy of the initial substrate on the intermediate support at a value just greater than the threshold energy necessary to allow the separation between the film and the initial substrate.
- the sealing energy of the initial substrate and the intermediate support can be controlled through the roughness of the surfaces and heat treatments. possibly used in addition to the separation treatment. Since the intermediate support can be recycled, expensive substrates (compatible with the application) or even specially prepared substrates can be used as support to facilitate delamination at the interface for first sealing.
- the recovery of the intermediate support after it has been sealed to the target substrate can be carried out for example by a "lift-off" or mechanical and / or pneumatic loosening technique, or alternatively by a method in combination with a gaseous implantation, these techniques being combined together.
- a seventh variant of implementation applies in particular to the case where the free surface of the film separated from the initial substrate is difficult to polish or has an insufficient quality of smoothing after a direct process.
- the films obtained by the direct process often have, after the separation step, a surface roughness to be reduced for the intended application.
- a chemical mechanical polishing can be carried out.
- materials for example "hard” materials (sapphire, SiC, diamond, etc.)
- this polishing is either unsuitable (not effective for polishing a film of hard material when it has been developed for the same material in massive form, insufficient quality, lack of uniformity of thickness), or too long (which increases the manufacturing cost).
- the invention solves this problem.
- an initial substrate 1 constituted by a monocrystalline sapphire plate of orientation [1-102] and polished on the surface with an epitaxial quality.
- the brochure may possibly be covered with a layer of silicon oxide.
- the initial substrate 1 is implanted by gaseous species, for example by hydrogen.
- the implantation energy can be 60 keV for a dose of 2.10 17 atoms / cm 2 . If the oxide layer is present, the implantation energy is then increased to take account of the thickness of this oxide layer.
- the initial substrate After preparation of the implanted face (first contact face), the initial substrate is brought into contact by molecular adhesion with the intermediate support. The separation of the sapphire film is caused in or in the vicinity of the weakened layer.
- the invention makes it possible to obtain a stacked structure comprising a film whose free face (or front face) is this initial face of epitaxial quality.
- the step of separating the film from the rest of the initial substrate is therefore carried out after adhering contact of the initial substrate on the intermediate support via a possible additional initial film.
- the free face of the sapphire film has a certain roughness.
- a layer of a material is deposited there, for example a layer of Si0 2 , and a chemical mechanical polishing allows its planarization . area.
- the second step of adhering contact is carried out.
- the removal of the intermediate support reveals the initial front face of the sapphire film or of the additional initial film.
- This additional initial film can advantageously be a silicon oxide film. In this case, it can be removed by chemical attack to release the initial front face of the sapphire film. If this front face is covered with an oxide layer, this layer can be removed by chemical attack.
- An eighth variant of implementation applies to the case where the film has faces having different characteristics. This is the case mentioned in the prior art of growth recovery by epitaxy on the film 6, for example in SiC (material having a Si type face and a C type face) or in GaN.
- an initial SiC substrate is covered with an oxide layer approximately 400 nm thick.
- the initial substrate is implanted, through the oxide layer, by hydrogen atoms of energy 120 keV and according to a dose of 8.10 1S atoms / cm 2 .
- the implanted surface is then made hydrophilic and is brought into contact for a bond by molecular adhesion with a face of an intermediate support covered with an oxide layer of 1 ⁇ m thick for example.
- a separation treatment makes it possible to separate the film from the rest of the initial substrate.
- the SiC film then adheres to the intermediate support via the oxide layer.
- a surface treatment for example a chemical mechanical polishing or the deposition of a film allowing planarization
- This free surface is made hydrophilic and is brought into contact for a bond by molecular adhesion with a corresponding face of the target substrate.
- the molecular adhesion energy can reach values greater than or equal to 1 J / m 2 .
- the intermediate support 10 is then removed, for example by grinding supplemented by a chemical attack, the oxide layer 3 serving as an etching stop layer.
- the oxide layer 3 is finally removed by etching using a solution based on hydrofluoric acid.
- the final thickness of the film is adapted, for example by means of a slimming heat treatment.
- a final thickness of the film 6 of 100 nm is obtained with very good homogeneity over a major part of the structure.
- the released surface of the film corresponds to the surface capable of recovery by growth in epitaxy.
- a ninth variant of implementation applies to the case where it is desired to recover the intermediate support and where the film (or one of the films) has faces having different characteristics.
- This variant is a special case of the previous variant.
- an ion implantation step is carried out through the surface 12 to induce a weakened area in the intermediate substrate or in one of the additional layers deposited on the intermediate substrate or the thin layer 7 depending on their nature. It can be an implantation of hydrogen in the intermediate substrate at an energy of 140 keV and according to a dose of 8.10 iS atoms / cm 2 for the example of the materials cited in the eighth variant and in which the intermediate substrate is made of SiC.
- the target substrate is brought into adherent contact with the second contact face.
- the intermediate support is then separated from the stacked structure and can be recycled.
- the recovery of the intermediate support of SiC is of definite economic interest.
- the oxide layer 3 is removed by etching using a hydrofluoric acid solution.
- the final thickness of the film 6 is adjusted by thinning, for example by sacrificial oxidation.
- a tenth implementation variant relates to the case where the film and the target substrate have at least one characteristic making the direct process incompatible. This may be the case where the materials constituting the film and the target substrate have coefficients of thermal expansion that are too different.
- a heat treatment used before or during the separation step, by the direct process, causes either a loosening at the contacting interface, or a rupture of one of the two elements placed in adherent contact.
- an initial substrate 1 consisting of a silicon wafer covered with an oxide layer 3 400 nm thick.
- a weakened layer 5 is created by implantation of hydrogen at an energy of 75 keV and with a dose of 6.10 16 atoms / cm 2 .
- the contact face 8 is sealed to an intermediate support 10 having a coefficient of compatible thermal expansion.
- This intermediate support can be another silicon wafer covered with an oxide layer 200 nm thick.
- Heat treatments can then be carried out. These heat treatments make it possible to increase the sealing energy, which will lead to a quality separation between the film and the rest of the initial substrate.
- the stack shown in FIG. 4 is obtained.
- a surface treatment makes it possible to minimize the surface microroughness of the film 6.
- the stack is sealed on a target substrate, the coefficient of expansion can be very different from that of the initial substrate, for example a quartz or sapphire plate and the intermediate support is removed for example by grinding, by chemical attack, by lift-off.
- step d) Another example of this tenth variant consists in causing adhesion to step b) whose energy corresponds at least to the threshold energy below which step c) cannot take place.
- an ion implantation for example of hydrogen, is carried out in the intermediate substrate or in one of the additional layers of this intermediate substrate through the face 12. This implantation induces therein a weakened layer in which s will perform the separation during step e).
- the intermediate substrate can then be recovered and reused.
- initial substrates themselves made up of a stacked structure, for example a silicon wafer covered with a nitride layer while the target substrate can be a silicon wafer covered with a thick layer thermal oxide.
- the coefficient of expansion of the nitride film may be greater than 4.10 ⁇ S / K while that of the oxide film is less than 10 "6 / K.
- a high temperature heat treatment used during or following the direct process by example for thinning the silicon film by sacrificial oxidation, is not compatible for certain conditions of adhesion energy between the nitride and silica films In this case, the use of the method according to the invention makes it possible to resolve the problem.
- the thin layer is treated at high temperature to thin it by sacrificial oxidation of silicon.
- step d an additional layer of nitride (Si 3 N 4 ) is produced on the free face of the thin layer and the target substrate is covered with an oxide film (Si0 2 ).
- the two layers can also be deposited on the free face of the thin layer or on the target substrate.
- the final stacked structure corresponds to the thinned layer of if the silicon supported by the two films with very different expansion coefficients.
- the characteristic rendering the direct process incompatible may be a phase change occurring in a film.
- a palladium film brought into contact with a silicon substrate allows adhesion by forming a silicide by means of a heat treatment at a temperature above 200 ° C.
- this silicide degrades, making for example thus impossible a sacrificial oxidation step at 900 ° C in the direct process. The invention solves this problem.
- the silicon film is thinned at 900 ° C. by sacrificial oxidation, then the film of palladium is deposited after the step of smoothing the free face 12 and constitutes all or part of the film referenced 13.
- the heat treatment of sealing with the target substrate being carried out at a temperature below 870 ° C., the sealing will be of good quality and the silicon film will be at the right thickness.
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Recrystallisation Techniques (AREA)
- Element Separation (AREA)
Abstract
Description
Claims
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020037006179A KR100855083B1 (ko) | 2000-11-06 | 2001-11-05 | 타겟 기판에 결합된 박막을 구비하는 적층 구조의 제조 방법 |
AU2002223735A AU2002223735A1 (en) | 2000-11-06 | 2001-11-05 | Method for making a stacked structure comprising a thin film adhering to a target substrate |
JP2002540206A JP2004513517A (ja) | 2000-11-06 | 2001-11-05 | ターゲット基板に結合される少なくとも一の薄層を備えた積層構造の作製方法 |
US10/415,672 US6974759B2 (en) | 2000-11-06 | 2001-11-05 | Method for making a stacked comprising a thin film adhering to a target substrate |
EP01993021.3A EP1344249B1 (fr) | 2000-11-06 | 2001-11-05 | Procédé de fabrication d'une structure empilée comprenant une couche mince adhérant à un substrat cible |
US13/841,196 US8679946B2 (en) | 2000-11-06 | 2013-03-15 | Manufacturing process for a stacked structure comprising a thin layer bonding to a target substrate |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0014170A FR2816445B1 (fr) | 2000-11-06 | 2000-11-06 | Procede de fabrication d'une structure empilee comprenant une couche mince adherant a un substrat cible |
FR00/14170 | 2000-11-06 |
Related Child Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10415672 A-371-Of-International | 2001-11-05 | ||
US11/233,785 Continuation US8481409B2 (en) | 2000-11-06 | 2005-09-23 | Manufacturing process for a stacked structure comprising a thin layer bonding to a target substrate |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2002037556A1 true WO2002037556A1 (fr) | 2002-05-10 |
Family
ID=8856075
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/FR2001/003401 WO2002037556A1 (fr) | 2000-11-06 | 2001-11-05 | Procede de fabrication d'une structure empilee comprenant une couche mince adherant a un substrat cible |
Country Status (9)
Country | Link |
---|---|
US (3) | US6974759B2 (fr) |
EP (1) | EP1344249B1 (fr) |
JP (3) | JP2004513517A (fr) |
KR (1) | KR100855083B1 (fr) |
CN (1) | CN1327505C (fr) |
AU (1) | AU2002223735A1 (fr) |
FR (1) | FR2816445B1 (fr) |
TW (1) | TW513752B (fr) |
WO (1) | WO2002037556A1 (fr) |
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2003063214A2 (fr) * | 2002-01-22 | 2003-07-31 | S.O.I.Tec Silicon On Insulator Technologies | Procede de preparation d'ensembles semi-conducteurs separable, en particulier pour former des substrats pour composants electroniques, optoelectroniques et optiques |
FR2840730A1 (fr) * | 2002-06-11 | 2003-12-12 | Soitec Silicon On Insulator | Procede de fabrication d'un substrat comportant une couche utile en materiau semi-conducteur monocristallin de proprietes ameliorees |
WO2003105219A1 (fr) * | 2002-06-11 | 2003-12-18 | S.O.I.T.E.C. Silicon On Insulator Technologies | Procede de production d'un substrat comprenant une couche utile de materiau semi-conducteur monocristallin |
FR2842648A1 (fr) * | 2002-07-18 | 2004-01-23 | Commissariat Energie Atomique | Procede de transfert d'une couche mince electriquement active |
FR2845523A1 (fr) * | 2002-10-07 | 2004-04-09 | Soitec Silicon On Insulator | Procede pour realiser un substrat par transfert d'une plaquette donneuse comportant des especes etrangeres, et plaquette donneuse associee |
WO2005004231A1 (fr) * | 2003-06-24 | 2005-01-13 | Osram Opto Semiconductors Gmbh | Procede de fabrication de puces a semi-conducteur |
US7465645B2 (en) | 2003-08-04 | 2008-12-16 | S.O.I.Tec Silicon On Insulator Technologies | Method of detaching a layer from a wafer using a localized starting area |
US7615468B2 (en) | 2000-11-27 | 2009-11-10 | S.O.I.Tec Silicon On Insulator Technologies | Methods for making substrates and substrates formed therefrom |
US8252664B2 (en) | 2000-11-27 | 2012-08-28 | Soitec | Fabrication of substrates with a useful layer of monocrystalline semiconductor material |
US9011598B2 (en) | 2004-06-03 | 2015-04-21 | Soitec | Method for making a composite substrate and composite substrate according to the method |
FR3042647A1 (fr) * | 2015-10-20 | 2017-04-21 | Soitec Silicon On Insulator | Structure composite et procede de fabrication associe |
WO2019186267A1 (fr) | 2018-03-29 | 2019-10-03 | Soitec | Procede de transfert d'une couche |
Families Citing this family (261)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2773261B1 (fr) | 1997-12-30 | 2000-01-28 | Commissariat Energie Atomique | Procede pour le transfert d'un film mince comportant une etape de creation d'inclusions |
FR2835097B1 (fr) * | 2002-01-23 | 2005-10-14 | Procede optimise de report d'une couche mince de carbure de silicium sur un substrat d'accueil | |
FR2837981B1 (fr) * | 2002-03-28 | 2005-01-07 | Commissariat Energie Atomique | Procede de manipulation de couches semiconductrices pour leur amincissement |
JP4277481B2 (ja) * | 2002-05-08 | 2009-06-10 | 日本電気株式会社 | 半導体基板の製造方法、半導体装置の製造方法 |
FR2845518B1 (fr) * | 2002-10-07 | 2005-10-14 | Commissariat Energie Atomique | Realisation d'un substrat semiconducteur demontable et obtention d'un element semiconducteur |
CN101800183B (zh) * | 2002-11-13 | 2013-02-06 | 日本冲信息株式会社 | 具有半导体薄膜的组合半导体装置 |
JP4407127B2 (ja) * | 2003-01-10 | 2010-02-03 | 信越半導体株式会社 | Soiウエーハの製造方法 |
FR2857953B1 (fr) * | 2003-07-21 | 2006-01-13 | Commissariat Energie Atomique | Structure empilee, et procede pour la fabriquer |
FR2857983B1 (fr) * | 2003-07-24 | 2005-09-02 | Soitec Silicon On Insulator | Procede de fabrication d'une couche epitaxiee |
US7538010B2 (en) * | 2003-07-24 | 2009-05-26 | S.O.I.Tec Silicon On Insulator Technologies | Method of fabricating an epitaxially grown layer |
US8475693B2 (en) | 2003-09-30 | 2013-07-02 | Soitec | Methods of making substrate structures having a weakened intermediate layer |
FR2861497B1 (fr) | 2003-10-28 | 2006-02-10 | Soitec Silicon On Insulator | Procede de transfert catastrophique d'une couche fine apres co-implantation |
FR2864336B1 (fr) | 2003-12-23 | 2006-04-28 | Commissariat Energie Atomique | Procede de scellement de deux plaques avec formation d'un contact ohmique entre celles-ci |
US20060234486A1 (en) * | 2005-04-13 | 2006-10-19 | Speck James S | Wafer separation technique for the fabrication of free-standing (Al,In,Ga)N wafers |
FR2872627B1 (fr) | 2004-06-30 | 2006-08-18 | Commissariat Energie Atomique | Assemblage par adhesion moleculaire de deux substrats |
US7497907B2 (en) * | 2004-07-23 | 2009-03-03 | Memc Electronic Materials, Inc. | Partially devitrified crucible |
KR20070085639A (ko) * | 2004-11-19 | 2007-08-27 | 아크조 노벨 엔.브이. | 가요성이 기계적으로 보정된 투명 층상 물질의 제조 방법 |
EP1681712A1 (fr) * | 2005-01-13 | 2006-07-19 | S.O.I. Tec Silicon on Insulator Technologies S.A. | Méthode de formation de substrats pour applications optoélectroniques. |
FR2889887B1 (fr) | 2005-08-16 | 2007-11-09 | Commissariat Energie Atomique | Procede de report d'une couche mince sur un support |
FR2895391B1 (fr) * | 2005-12-27 | 2008-01-25 | Commissariat Energie Atomique | Procede d'elaboration de nanostructures ordonnees |
FR2895420B1 (fr) * | 2005-12-27 | 2008-02-22 | Tracit Technologies Sa | Procede de fabrication d'une structure demontable en forme de plaque, en particulier en silicium, et application de ce procede. |
FR2910179B1 (fr) | 2006-12-19 | 2009-03-13 | Commissariat Energie Atomique | PROCEDE DE FABRICATION DE COUCHES MINCES DE GaN PAR IMPLANTATION ET RECYCLAGE D'UN SUBSTRAT DE DEPART |
FR2911598B1 (fr) * | 2007-01-22 | 2009-04-17 | Soitec Silicon On Insulator | Procede de rugosification de surface. |
WO2008096194A1 (fr) * | 2007-02-08 | 2008-08-14 | S.O.I.Tec Silicon On Insulator Technologies | Procédé de fabrication de substrats dissipant la chaleur de manière importante |
US7799656B2 (en) * | 2007-03-15 | 2010-09-21 | Dalsa Semiconductor Inc. | Microchannels for BioMEMS devices |
US7776718B2 (en) * | 2007-06-25 | 2010-08-17 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing semiconductor substrate with reduced gap size between single-crystalline layers |
JP5498670B2 (ja) * | 2007-07-13 | 2014-05-21 | 株式会社半導体エネルギー研究所 | 半導体基板の作製方法 |
FR2920589B1 (fr) * | 2007-09-04 | 2010-12-03 | Soitec Silicon On Insulator | "procede d'obtention d'un substrat hybride comprenant au moins une couche d'un materiau nitrure" |
JP5463017B2 (ja) * | 2007-09-21 | 2014-04-09 | 株式会社半導体エネルギー研究所 | 基板の作製方法 |
FR2925221B1 (fr) | 2007-12-17 | 2010-02-19 | Commissariat Energie Atomique | Procede de transfert d'une couche mince |
FR2926674B1 (fr) * | 2008-01-21 | 2010-03-26 | Soitec Silicon On Insulator | Procede de fabrication d'une structure composite avec couche d'oxyde de collage stable |
FR2926748B1 (fr) | 2008-01-25 | 2010-04-02 | Commissariat Energie Atomique | Objet muni d'un element graphique reporte sur un support et procede de realisation d'un tel objet. |
JP2009212387A (ja) * | 2008-03-05 | 2009-09-17 | Semiconductor Energy Lab Co Ltd | 半導体基板の製造方法 |
WO2010067794A1 (fr) | 2008-12-10 | 2010-06-17 | 株式会社村田製作所 | Procédé pour la fabrication d'un substrat composite piézoélectrique et procédé pour la fabrication d'un élément piézoélectrique |
JP2010165927A (ja) * | 2009-01-16 | 2010-07-29 | Sumitomo Electric Ind Ltd | 発光素子用基板 |
US7927975B2 (en) | 2009-02-04 | 2011-04-19 | Micron Technology, Inc. | Semiconductor material manufacture |
US8373439B2 (en) | 2009-04-14 | 2013-02-12 | Monolithic 3D Inc. | 3D semiconductor device |
US9509313B2 (en) | 2009-04-14 | 2016-11-29 | Monolithic 3D Inc. | 3D semiconductor device |
US7986042B2 (en) | 2009-04-14 | 2011-07-26 | Monolithic 3D Inc. | Method for fabrication of a semiconductor device and structure |
US8384426B2 (en) * | 2009-04-14 | 2013-02-26 | Monolithic 3D Inc. | Semiconductor device and structure |
US9711407B2 (en) * | 2009-04-14 | 2017-07-18 | Monolithic 3D Inc. | Method of manufacturing a three dimensional integrated circuit by transfer of a mono-crystalline layer |
US8362482B2 (en) * | 2009-04-14 | 2013-01-29 | Monolithic 3D Inc. | Semiconductor device and structure |
US8058137B1 (en) | 2009-04-14 | 2011-11-15 | Monolithic 3D Inc. | Method for fabrication of a semiconductor device and structure |
US8405420B2 (en) * | 2009-04-14 | 2013-03-26 | Monolithic 3D Inc. | System comprising a semiconductor device and structure |
US8362800B2 (en) | 2010-10-13 | 2013-01-29 | Monolithic 3D Inc. | 3D semiconductor device including field repairable logics |
US8378715B2 (en) | 2009-04-14 | 2013-02-19 | Monolithic 3D Inc. | Method to construct systems |
US8427200B2 (en) | 2009-04-14 | 2013-04-23 | Monolithic 3D Inc. | 3D semiconductor device |
US9577642B2 (en) | 2009-04-14 | 2017-02-21 | Monolithic 3D Inc. | Method to form a 3D semiconductor device |
US8669778B1 (en) | 2009-04-14 | 2014-03-11 | Monolithic 3D Inc. | Method for design and manufacturing of a 3D semiconductor device |
US8754533B2 (en) * | 2009-04-14 | 2014-06-17 | Monolithic 3D Inc. | Monolithic three-dimensional semiconductor device and structure |
US8395191B2 (en) | 2009-10-12 | 2013-03-12 | Monolithic 3D Inc. | Semiconductor device and structure |
JP5443833B2 (ja) * | 2009-05-29 | 2014-03-19 | 信越化学工業株式会社 | 貼り合わせsoi基板の製造方法 |
FR2946435B1 (fr) | 2009-06-04 | 2017-09-29 | Commissariat A L'energie Atomique | Procede de fabrication d'images colorees avec une resolution micronique enfouies dans un support tres robuste et tres perenne |
US7985658B2 (en) * | 2009-06-08 | 2011-07-26 | Aptina Imaging Corporation | Method of forming substrate for use in imager devices |
FR2947098A1 (fr) | 2009-06-18 | 2010-12-24 | Commissariat Energie Atomique | Procede de transfert d'une couche mince sur un substrat cible ayant un coefficient de dilatation thermique different de celui de la couche mince |
US8742476B1 (en) | 2012-11-27 | 2014-06-03 | Monolithic 3D Inc. | Semiconductor device and structure |
US8581349B1 (en) | 2011-05-02 | 2013-11-12 | Monolithic 3D Inc. | 3D memory semiconductor device and structure |
US11984445B2 (en) | 2009-10-12 | 2024-05-14 | Monolithic 3D Inc. | 3D semiconductor devices and structures with metal layers |
US8476145B2 (en) | 2010-10-13 | 2013-07-02 | Monolithic 3D Inc. | Method of fabricating a semiconductor device and structure |
US12027518B1 (en) | 2009-10-12 | 2024-07-02 | Monolithic 3D Inc. | 3D semiconductor devices and structures with metal layers |
US8450804B2 (en) | 2011-03-06 | 2013-05-28 | Monolithic 3D Inc. | Semiconductor device and structure for heat removal |
US10354995B2 (en) | 2009-10-12 | 2019-07-16 | Monolithic 3D Inc. | Semiconductor memory device and structure |
US9099424B1 (en) | 2012-08-10 | 2015-08-04 | Monolithic 3D Inc. | Semiconductor system, device and structure with heat removal |
US10910364B2 (en) | 2009-10-12 | 2021-02-02 | Monolitaic 3D Inc. | 3D semiconductor device |
US10157909B2 (en) | 2009-10-12 | 2018-12-18 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US10043781B2 (en) | 2009-10-12 | 2018-08-07 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US10366970B2 (en) | 2009-10-12 | 2019-07-30 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US8536023B2 (en) | 2010-11-22 | 2013-09-17 | Monolithic 3D Inc. | Method of manufacturing a semiconductor device and structure |
US8148728B2 (en) | 2009-10-12 | 2012-04-03 | Monolithic 3D, Inc. | Method for fabrication of a semiconductor device and structure |
US11374118B2 (en) | 2009-10-12 | 2022-06-28 | Monolithic 3D Inc. | Method to form a 3D integrated circuit |
US10388863B2 (en) | 2009-10-12 | 2019-08-20 | Monolithic 3D Inc. | 3D memory device and structure |
US11018133B2 (en) | 2009-10-12 | 2021-05-25 | Monolithic 3D Inc. | 3D integrated circuit |
KR101055473B1 (ko) * | 2009-12-15 | 2011-08-08 | 삼성전기주식회사 | 기판 제조용 캐리어 부재 및 이를 이용한 기판의 제조방법 |
US8367519B2 (en) * | 2009-12-30 | 2013-02-05 | Memc Electronic Materials, Inc. | Method for the preparation of a multi-layered crystalline structure |
US8541819B1 (en) | 2010-12-09 | 2013-09-24 | Monolithic 3D Inc. | Semiconductor device and structure |
US8373230B1 (en) | 2010-10-13 | 2013-02-12 | Monolithic 3D Inc. | Method for fabrication of a semiconductor device and structure |
US8492886B2 (en) | 2010-02-16 | 2013-07-23 | Monolithic 3D Inc | 3D integrated circuit with logic |
US8026521B1 (en) * | 2010-10-11 | 2011-09-27 | Monolithic 3D Inc. | Semiconductor device and structure |
US8461035B1 (en) | 2010-09-30 | 2013-06-11 | Monolithic 3D Inc. | Method for fabrication of a semiconductor device and structure |
US9099526B2 (en) | 2010-02-16 | 2015-08-04 | Monolithic 3D Inc. | Integrated circuit device and structure |
FR2961948B1 (fr) * | 2010-06-23 | 2012-08-03 | Soitec Silicon On Insulator | Procede de traitement d'une piece en materiau compose |
SG177816A1 (en) * | 2010-07-15 | 2012-02-28 | Soitec Silicon On Insulator | Methods of forming bonded semiconductor structures, and semiconductor structures formed by such methods |
US9953925B2 (en) | 2011-06-28 | 2018-04-24 | Monolithic 3D Inc. | Semiconductor system and device |
US8901613B2 (en) | 2011-03-06 | 2014-12-02 | Monolithic 3D Inc. | Semiconductor device and structure for heat removal |
US9219005B2 (en) | 2011-06-28 | 2015-12-22 | Monolithic 3D Inc. | Semiconductor system and device |
US8642416B2 (en) | 2010-07-30 | 2014-02-04 | Monolithic 3D Inc. | Method of forming three dimensional integrated circuit devices using layer transfer technique |
US10217667B2 (en) | 2011-06-28 | 2019-02-26 | Monolithic 3D Inc. | 3D semiconductor device, fabrication method and system |
US8273610B2 (en) | 2010-11-18 | 2012-09-25 | Monolithic 3D Inc. | Method of constructing a semiconductor device and structure |
US11482440B2 (en) | 2010-12-16 | 2022-10-25 | Monolithic 3D Inc. | 3D semiconductor device and structure with a built-in test circuit for repairing faulty circuits |
US8163581B1 (en) | 2010-10-13 | 2012-04-24 | Monolith IC 3D | Semiconductor and optoelectronic devices |
US10497713B2 (en) | 2010-11-18 | 2019-12-03 | Monolithic 3D Inc. | 3D semiconductor memory device and structure |
US11600667B1 (en) | 2010-10-11 | 2023-03-07 | Monolithic 3D Inc. | Method to produce 3D semiconductor devices and structures with memory |
US8114757B1 (en) | 2010-10-11 | 2012-02-14 | Monolithic 3D Inc. | Semiconductor device and structure |
US11024673B1 (en) | 2010-10-11 | 2021-06-01 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11315980B1 (en) | 2010-10-11 | 2022-04-26 | Monolithic 3D Inc. | 3D semiconductor device and structure with transistors |
US10896931B1 (en) | 2010-10-11 | 2021-01-19 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11158674B2 (en) | 2010-10-11 | 2021-10-26 | Monolithic 3D Inc. | Method to produce a 3D semiconductor device and structure |
US11227897B2 (en) | 2010-10-11 | 2022-01-18 | Monolithic 3D Inc. | Method for producing a 3D semiconductor memory device and structure |
US11469271B2 (en) | 2010-10-11 | 2022-10-11 | Monolithic 3D Inc. | Method to produce 3D semiconductor devices and structures with memory |
US11018191B1 (en) | 2010-10-11 | 2021-05-25 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11793005B2 (en) * | 2010-10-11 | 2023-10-17 | Monolithic 3D Inc. | 3D semiconductor devices and structures |
US10290682B2 (en) | 2010-10-11 | 2019-05-14 | Monolithic 3D Inc. | 3D IC semiconductor device and structure with stacked memory |
US11257867B1 (en) | 2010-10-11 | 2022-02-22 | Monolithic 3D Inc. | 3D semiconductor device and structure with oxide bonds |
US11956976B2 (en) * | 2010-10-11 | 2024-04-09 | Monolithic 3D Inc. | 3D semiconductor devices and structures with transistors |
US9197804B1 (en) | 2011-10-14 | 2015-11-24 | Monolithic 3D Inc. | Semiconductor and optoelectronic devices |
US11605663B2 (en) | 2010-10-13 | 2023-03-14 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with image sensors and wafer bonding |
US10998374B1 (en) | 2010-10-13 | 2021-05-04 | Monolithic 3D Inc. | Multilevel semiconductor device and structure |
US10833108B2 (en) | 2010-10-13 | 2020-11-10 | Monolithic 3D Inc. | 3D microdisplay device and structure |
US11327227B2 (en) | 2010-10-13 | 2022-05-10 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with electromagnetic modulators |
US8379458B1 (en) | 2010-10-13 | 2013-02-19 | Monolithic 3D Inc. | Semiconductor device and structure |
US11063071B1 (en) | 2010-10-13 | 2021-07-13 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with waveguides |
US10943934B2 (en) | 2010-10-13 | 2021-03-09 | Monolithic 3D Inc. | Multilevel semiconductor device and structure |
US11163112B2 (en) | 2010-10-13 | 2021-11-02 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with electromagnetic modulators |
US10679977B2 (en) | 2010-10-13 | 2020-06-09 | Monolithic 3D Inc. | 3D microdisplay device and structure |
US11929372B2 (en) | 2010-10-13 | 2024-03-12 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with image sensors and wafer bonding |
US11164898B2 (en) | 2010-10-13 | 2021-11-02 | Monolithic 3D Inc. | Multilevel semiconductor device and structure |
US11869915B2 (en) | 2010-10-13 | 2024-01-09 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with image sensors and wafer bonding |
US11043523B1 (en) | 2010-10-13 | 2021-06-22 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with image sensors |
US11855100B2 (en) | 2010-10-13 | 2023-12-26 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with oxide bonding |
US10978501B1 (en) | 2010-10-13 | 2021-04-13 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with waveguides |
US11437368B2 (en) | 2010-10-13 | 2022-09-06 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with oxide bonding |
US11133344B2 (en) | 2010-10-13 | 2021-09-28 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with image sensors |
US11404466B2 (en) | 2010-10-13 | 2022-08-02 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with image sensors |
US11694922B2 (en) | 2010-10-13 | 2023-07-04 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with oxide bonding |
US11855114B2 (en) | 2010-10-13 | 2023-12-26 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with image sensors and wafer bonding |
US11984438B2 (en) | 2010-10-13 | 2024-05-14 | Monolithic 3D Inc. | Multilevel semiconductor device and structure with oxide bonding |
US11784082B2 (en) | 2010-11-18 | 2023-10-10 | Monolithic 3D Inc. | 3D semiconductor device and structure with bonding |
US11094576B1 (en) | 2010-11-18 | 2021-08-17 | Monolithic 3D Inc. | Methods for producing a 3D semiconductor memory device and structure |
US11004719B1 (en) | 2010-11-18 | 2021-05-11 | Monolithic 3D Inc. | Methods for producing a 3D semiconductor memory device and structure |
US11854857B1 (en) | 2010-11-18 | 2023-12-26 | Monolithic 3D Inc. | Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers |
US11482438B2 (en) | 2010-11-18 | 2022-10-25 | Monolithic 3D Inc. | Methods for producing a 3D semiconductor memory device and structure |
US11495484B2 (en) | 2010-11-18 | 2022-11-08 | Monolithic 3D Inc. | 3D semiconductor devices and structures with at least two single-crystal layers |
US11018042B1 (en) | 2010-11-18 | 2021-05-25 | Monolithic 3D Inc. | 3D semiconductor memory device and structure |
US11211279B2 (en) | 2010-11-18 | 2021-12-28 | Monolithic 3D Inc. | Method for processing a 3D integrated circuit and structure |
US11862503B2 (en) | 2010-11-18 | 2024-01-02 | Monolithic 3D Inc. | Method for producing a 3D semiconductor device and structure with memory cells and multiple metal layers |
US11610802B2 (en) | 2010-11-18 | 2023-03-21 | Monolithic 3D Inc. | Method for producing a 3D semiconductor device and structure with single crystal transistors and metal gate electrodes |
US11804396B2 (en) | 2010-11-18 | 2023-10-31 | Monolithic 3D Inc. | Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers |
US11901210B2 (en) | 2010-11-18 | 2024-02-13 | Monolithic 3D Inc. | 3D semiconductor device and structure with memory |
US11569117B2 (en) | 2010-11-18 | 2023-01-31 | Monolithic 3D Inc. | 3D semiconductor device and structure with single-crystal layers |
US11923230B1 (en) | 2010-11-18 | 2024-03-05 | Monolithic 3D Inc. | 3D semiconductor device and structure with bonding |
US11164770B1 (en) | 2010-11-18 | 2021-11-02 | Monolithic 3D Inc. | Method for producing a 3D semiconductor memory device and structure |
US12033884B2 (en) | 2010-11-18 | 2024-07-09 | Monolithic 3D Inc. | Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers |
US11355381B2 (en) | 2010-11-18 | 2022-06-07 | Monolithic 3D Inc. | 3D semiconductor memory device and structure |
US11615977B2 (en) | 2010-11-18 | 2023-03-28 | Monolithic 3D Inc. | 3D semiconductor memory device and structure |
US11121021B2 (en) | 2010-11-18 | 2021-09-14 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11482439B2 (en) | 2010-11-18 | 2022-10-25 | Monolithic 3D Inc. | Methods for producing a 3D semiconductor memory device comprising charge trap junction-less transistors |
US11443971B2 (en) | 2010-11-18 | 2022-09-13 | Monolithic 3D Inc. | 3D semiconductor device and structure with memory |
US11355380B2 (en) | 2010-11-18 | 2022-06-07 | Monolithic 3D Inc. | Methods for producing 3D semiconductor memory device and structure utilizing alignment marks |
US11107721B2 (en) | 2010-11-18 | 2021-08-31 | Monolithic 3D Inc. | 3D semiconductor device and structure with NAND logic |
US11508605B2 (en) | 2010-11-18 | 2022-11-22 | Monolithic 3D Inc. | 3D semiconductor memory device and structure |
US11521888B2 (en) | 2010-11-18 | 2022-12-06 | Monolithic 3D Inc. | 3D semiconductor device and structure with high-k metal gate transistors |
US11735462B2 (en) | 2010-11-18 | 2023-08-22 | Monolithic 3D Inc. | 3D semiconductor device and structure with single-crystal layers |
US11031275B2 (en) | 2010-11-18 | 2021-06-08 | Monolithic 3D Inc. | 3D semiconductor device and structure with memory |
US8975670B2 (en) | 2011-03-06 | 2015-03-10 | Monolithic 3D Inc. | Semiconductor device and structure for heat removal |
US20130154049A1 (en) * | 2011-06-22 | 2013-06-20 | George IMTHURN | Integrated Circuits on Ceramic Wafers Using Layer Transfer Technology |
FR2977069B1 (fr) | 2011-06-23 | 2014-02-07 | Soitec Silicon On Insulator | Procede de fabrication d'une structure semi-conductrice mettant en oeuvre un collage temporaire |
US10388568B2 (en) | 2011-06-28 | 2019-08-20 | Monolithic 3D Inc. | 3D semiconductor device and system |
RU2469433C1 (ru) * | 2011-07-13 | 2012-12-10 | Юрий Георгиевич Шретер | Способ лазерного отделения эпитаксиальной пленки или слоя эпитаксиальной пленки от ростовой подложки эпитаксиальной полупроводниковой структуры (варианты) |
US8687399B2 (en) | 2011-10-02 | 2014-04-01 | Monolithic 3D Inc. | Semiconductor device and structure |
US9029173B2 (en) | 2011-10-18 | 2015-05-12 | Monolithic 3D Inc. | Method for fabrication of a semiconductor device and structure |
US9000557B2 (en) | 2012-03-17 | 2015-04-07 | Zvi Or-Bach | Semiconductor device and structure |
US11088050B2 (en) | 2012-04-09 | 2021-08-10 | Monolithic 3D Inc. | 3D semiconductor device with isolation layers |
US11476181B1 (en) | 2012-04-09 | 2022-10-18 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers |
US10600888B2 (en) | 2012-04-09 | 2020-03-24 | Monolithic 3D Inc. | 3D semiconductor device |
US11164811B2 (en) | 2012-04-09 | 2021-11-02 | Monolithic 3D Inc. | 3D semiconductor device with isolation layers and oxide-to-oxide bonding |
US8557632B1 (en) | 2012-04-09 | 2013-10-15 | Monolithic 3D Inc. | Method for fabrication of a semiconductor device and structure |
US11694944B1 (en) | 2012-04-09 | 2023-07-04 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers and a connective path |
US11616004B1 (en) | 2012-04-09 | 2023-03-28 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers and a connective path |
US11881443B2 (en) | 2012-04-09 | 2024-01-23 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers and a connective path |
US11410912B2 (en) | 2012-04-09 | 2022-08-09 | Monolithic 3D Inc. | 3D semiconductor device with vias and isolation layers |
US11594473B2 (en) | 2012-04-09 | 2023-02-28 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers and a connective path |
US11735501B1 (en) | 2012-04-09 | 2023-08-22 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers and a connective path |
WO2013190793A1 (fr) * | 2012-06-18 | 2013-12-27 | パナソニック株式会社 | Dispositif de détection infrarouge |
US9481566B2 (en) | 2012-07-31 | 2016-11-01 | Soitec | Methods of forming semiconductor structures including MEMS devices and integrated circuits on opposing sides of substrates, and related structures and devices |
US8574929B1 (en) | 2012-11-16 | 2013-11-05 | Monolithic 3D Inc. | Method to form a 3D semiconductor device and structure |
US8686428B1 (en) | 2012-11-16 | 2014-04-01 | Monolithic 3D Inc. | Semiconductor device and structure |
US11309292B2 (en) | 2012-12-22 | 2022-04-19 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers |
US11967583B2 (en) | 2012-12-22 | 2024-04-23 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers |
US11916045B2 (en) | 2012-12-22 | 2024-02-27 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers |
US11784169B2 (en) | 2012-12-22 | 2023-10-10 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers |
US11018116B2 (en) | 2012-12-22 | 2021-05-25 | Monolithic 3D Inc. | Method to form a 3D semiconductor device and structure |
US11961827B1 (en) | 2012-12-22 | 2024-04-16 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers |
US11063024B1 (en) | 2012-12-22 | 2021-07-13 | Monlithic 3D Inc. | Method to form a 3D semiconductor device and structure |
US11217565B2 (en) | 2012-12-22 | 2022-01-04 | Monolithic 3D Inc. | Method to form a 3D semiconductor device and structure |
US8674470B1 (en) | 2012-12-22 | 2014-03-18 | Monolithic 3D Inc. | Semiconductor device and structure |
US10892169B2 (en) | 2012-12-29 | 2021-01-12 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US10115663B2 (en) | 2012-12-29 | 2018-10-30 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US9385058B1 (en) | 2012-12-29 | 2016-07-05 | Monolithic 3D Inc. | Semiconductor device and structure |
US10903089B1 (en) | 2012-12-29 | 2021-01-26 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11430667B2 (en) | 2012-12-29 | 2022-08-30 | Monolithic 3D Inc. | 3D semiconductor device and structure with bonding |
US11430668B2 (en) | 2012-12-29 | 2022-08-30 | Monolithic 3D Inc. | 3D semiconductor device and structure with bonding |
US10600657B2 (en) | 2012-12-29 | 2020-03-24 | Monolithic 3D Inc | 3D semiconductor device and structure |
US11004694B1 (en) | 2012-12-29 | 2021-05-11 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US10651054B2 (en) | 2012-12-29 | 2020-05-12 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11087995B1 (en) | 2012-12-29 | 2021-08-10 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11177140B2 (en) | 2012-12-29 | 2021-11-16 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US9871034B1 (en) | 2012-12-29 | 2018-01-16 | Monolithic 3D Inc. | Semiconductor device and structure |
US11935949B1 (en) | 2013-03-11 | 2024-03-19 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers and memory cells |
US11869965B2 (en) | 2013-03-11 | 2024-01-09 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers and memory cells |
US10325651B2 (en) | 2013-03-11 | 2019-06-18 | Monolithic 3D Inc. | 3D semiconductor device with stacked memory |
US8902663B1 (en) | 2013-03-11 | 2014-12-02 | Monolithic 3D Inc. | Method of maintaining a memory state |
US10840239B2 (en) | 2014-08-26 | 2020-11-17 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US8994404B1 (en) | 2013-03-12 | 2015-03-31 | Monolithic 3D Inc. | Semiconductor device and structure |
US11088130B2 (en) | 2014-01-28 | 2021-08-10 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11398569B2 (en) | 2013-03-12 | 2022-07-26 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11923374B2 (en) | 2013-03-12 | 2024-03-05 | Monolithic 3D Inc. | 3D semiconductor device and structure with metal layers |
US10224279B2 (en) | 2013-03-15 | 2019-03-05 | Monolithic 3D Inc. | Semiconductor device and structure |
US9117749B1 (en) | 2013-03-15 | 2015-08-25 | Monolithic 3D Inc. | Semiconductor device and structure |
US11270055B1 (en) | 2013-04-15 | 2022-03-08 | Monolithic 3D Inc. | Automation for monolithic 3D devices |
US11720736B2 (en) | 2013-04-15 | 2023-08-08 | Monolithic 3D Inc. | Automation methods for 3D integrated circuits and devices |
US11030371B2 (en) | 2013-04-15 | 2021-06-08 | Monolithic 3D Inc. | Automation for monolithic 3D devices |
US9021414B1 (en) | 2013-04-15 | 2015-04-28 | Monolithic 3D Inc. | Automation for monolithic 3D devices |
US11574109B1 (en) | 2013-04-15 | 2023-02-07 | Monolithic 3D Inc | Automation methods for 3D integrated circuits and devices |
US11341309B1 (en) | 2013-04-15 | 2022-05-24 | Monolithic 3D Inc. | Automation for monolithic 3D devices |
US11487928B2 (en) | 2013-04-15 | 2022-11-01 | Monolithic 3D Inc. | Automation for monolithic 3D devices |
US9741603B2 (en) | 2013-05-01 | 2017-08-22 | Shin-Etsu Chemical Co., Ltd. | Method for producing hybrid substrate, and hybrid substrate |
FR3007891B1 (fr) * | 2013-06-28 | 2016-11-25 | Soitec Silicon On Insulator | Procede de fabrication d'une structure composite |
JP6200273B2 (ja) * | 2013-10-17 | 2017-09-20 | 信越半導体株式会社 | 貼り合わせウェーハの製造方法 |
CN105684133B (zh) * | 2013-11-06 | 2020-05-15 | 应用材料公司 | 溶胶凝胶涂布的支撑环 |
US11107808B1 (en) | 2014-01-28 | 2021-08-31 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11031394B1 (en) | 2014-01-28 | 2021-06-08 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US10297586B2 (en) | 2015-03-09 | 2019-05-21 | Monolithic 3D Inc. | Methods for processing a 3D semiconductor device |
US10381328B2 (en) | 2015-04-19 | 2019-08-13 | Monolithic 3D Inc. | Semiconductor device and structure |
US11056468B1 (en) | 2015-04-19 | 2021-07-06 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US10825779B2 (en) | 2015-04-19 | 2020-11-03 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11011507B1 (en) | 2015-04-19 | 2021-05-18 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11956952B2 (en) | 2015-08-23 | 2024-04-09 | Monolithic 3D Inc. | Semiconductor memory device and structure |
US11937422B2 (en) | 2015-11-07 | 2024-03-19 | Monolithic 3D Inc. | Semiconductor memory device and structure |
US11114427B2 (en) | 2015-11-07 | 2021-09-07 | Monolithic 3D Inc. | 3D semiconductor processor and memory device and structure |
CN115942752A (zh) | 2015-09-21 | 2023-04-07 | 莫诺利特斯3D有限公司 | 3d半导体器件和结构 |
US11978731B2 (en) | 2015-09-21 | 2024-05-07 | Monolithic 3D Inc. | Method to produce a multi-level semiconductor memory device and structure |
US10522225B1 (en) | 2015-10-02 | 2019-12-31 | Monolithic 3D Inc. | Semiconductor device with non-volatile memory |
US12016181B2 (en) | 2015-10-24 | 2024-06-18 | Monolithic 3D Inc. | 3D semiconductor device and structure with logic and memory |
US11114464B2 (en) | 2015-10-24 | 2021-09-07 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11296115B1 (en) | 2015-10-24 | 2022-04-05 | Monolithic 3D Inc. | 3D semiconductor device and structure |
US11991884B1 (en) | 2015-10-24 | 2024-05-21 | Monolithic 3D Inc. | 3D semiconductor device and structure with logic and memory |
US10847540B2 (en) | 2015-10-24 | 2020-11-24 | Monolithic 3D Inc. | 3D semiconductor memory device and structure |
US10418369B2 (en) | 2015-10-24 | 2019-09-17 | Monolithic 3D Inc. | Multi-level semiconductor memory device and structure |
US12035531B2 (en) | 2015-10-24 | 2024-07-09 | Monolithic 3D Inc. | 3D semiconductor device and structure with logic and memory |
FR3045933B1 (fr) | 2015-12-22 | 2018-02-09 | Soitec | Substrat pour un dispositif a ondes acoustiques de surface ou a ondes acoustiques de volume compense en temperature |
US10037985B2 (en) | 2016-05-17 | 2018-07-31 | X-Celeprint Limited | Compound micro-transfer-printed power transistor device |
FR3051979B1 (fr) * | 2016-05-25 | 2018-05-18 | Soitec | Procede de guerison de defauts dans une couche obtenue par implantation puis detachement d'un substrat |
US11930648B1 (en) | 2016-10-10 | 2024-03-12 | Monolithic 3D Inc. | 3D memory devices and structures with metal layers |
US11711928B2 (en) | 2016-10-10 | 2023-07-25 | Monolithic 3D Inc. | 3D memory devices and structures with control circuits |
US11329059B1 (en) | 2016-10-10 | 2022-05-10 | Monolithic 3D Inc. | 3D memory devices and structures with thinned single crystal substrates |
US11251149B2 (en) | 2016-10-10 | 2022-02-15 | Monolithic 3D Inc. | 3D memory device and structure |
US11869591B2 (en) | 2016-10-10 | 2024-01-09 | Monolithic 3D Inc. | 3D memory devices and structures with control circuits |
US11812620B2 (en) | 2016-10-10 | 2023-11-07 | Monolithic 3D Inc. | 3D DRAM memory devices and structures with control circuits |
FR3078822B1 (fr) * | 2018-03-12 | 2020-02-28 | Soitec | Procede de preparation d’une couche mince de materiau ferroelectrique a base d’alcalin |
FR3079534B1 (fr) * | 2018-03-28 | 2022-03-18 | Soitec Silicon On Insulator | Procede de fabrication d'une couche monocristalline de materiau gaas et substrat pour croissance par epitaxie d'une couche monocristalline de materiau gaas |
CN109192670A (zh) * | 2018-08-17 | 2019-01-11 | 中国科学院上海微系统与信息技术研究所 | 柔性半导体复合薄膜及其制备方法 |
CN109850877A (zh) * | 2019-02-21 | 2019-06-07 | 中国科学院上海微系统与信息技术研究所 | 石墨烯纳米带的转移方法 |
US10892016B1 (en) | 2019-04-08 | 2021-01-12 | Monolithic 3D Inc. | 3D memory semiconductor devices and structures |
US11763864B2 (en) | 2019-04-08 | 2023-09-19 | Monolithic 3D Inc. | 3D memory semiconductor devices and structures with bit-line pillars |
US11158652B1 (en) | 2019-04-08 | 2021-10-26 | Monolithic 3D Inc. | 3D memory semiconductor devices and structures |
US11296106B2 (en) | 2019-04-08 | 2022-04-05 | Monolithic 3D Inc. | 3D memory semiconductor devices and structures |
US11018156B2 (en) | 2019-04-08 | 2021-05-25 | Monolithic 3D Inc. | 3D memory semiconductor devices and structures |
CN113540339B (zh) * | 2020-04-21 | 2024-07-12 | 济南晶正电子科技有限公司 | 一种制备压电复合薄膜的方法及压电复合薄膜 |
CN111834279B (zh) * | 2020-06-29 | 2021-08-17 | 中国科学院上海微系统与信息技术研究所 | 一种临时键合和解键合方法、载片结构及应用 |
US11152395B1 (en) | 2020-11-12 | 2021-10-19 | X-Celeprint Limited | Monolithic multi-FETs |
FR3116652A1 (fr) | 2020-11-26 | 2022-05-27 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Procédé de fabrication d’un composant comprenant une couche en matériau monocristallin compatible avec des budgets thermiques élevés |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5391257A (en) * | 1993-12-10 | 1995-02-21 | Rockwell International Corporation | Method of transferring a thin film to an alternate substrate |
FR2781082A1 (fr) * | 1998-07-10 | 2000-01-14 | Commissariat Energie Atomique | Structure semiconductrice en couche mince comportant une couche de repartition de chaleur |
WO2000019499A1 (fr) * | 1998-09-30 | 2000-04-06 | MAX-PLANCK-Gesellschaft zur Förderung der Wissenschaften e.V. | Procede de transfert de couches minces de matiere monocristalline sur un substrat voulu |
Family Cites Families (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3565594A (en) * | 1968-11-22 | 1971-02-23 | Normand A Hill | Gasoline vapor generator |
US5044552A (en) * | 1989-11-01 | 1991-09-03 | The United States Of America As Represented By The United States Department Of Energy | Supersonic coal water slurry fuel atomizer |
JPH04199504A (ja) * | 1990-11-28 | 1992-07-20 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
JP3112106B2 (ja) * | 1991-10-11 | 2000-11-27 | キヤノン株式会社 | 半導体基材の作製方法 |
FR2725074B1 (fr) * | 1994-09-22 | 1996-12-20 | Commissariat Energie Atomique | Procede de fabrication d'une structure comportant une couche mince semi-conductrice sur un substrat |
JPH08186166A (ja) * | 1994-12-27 | 1996-07-16 | Mitsubishi Materials Shilicon Corp | 張り合わせ誘電体分離ウェーハの製造方法 |
FR2744285B1 (fr) * | 1996-01-25 | 1998-03-06 | Commissariat Energie Atomique | Procede de transfert d'une couche mince d'un substrat initial sur un substrat final |
US6074892A (en) * | 1996-05-07 | 2000-06-13 | Ciena Corporation | Semiconductor hetero-interface photodetector |
FR2748851B1 (fr) * | 1996-05-15 | 1998-08-07 | Commissariat Energie Atomique | Procede de realisation d'une couche mince de materiau semiconducteur |
JP3962465B2 (ja) * | 1996-12-18 | 2007-08-22 | キヤノン株式会社 | 半導体部材の製造方法 |
JPH10223495A (ja) * | 1997-02-04 | 1998-08-21 | Nippon Telegr & Teleph Corp <Ntt> | 柔軟な構造を有する半導体装置とその製造方法 |
US6210479B1 (en) * | 1999-02-26 | 2001-04-03 | International Business Machines Corporation | Product and process for forming a semiconductor structure on a host substrate |
JPH11111839A (ja) * | 1997-10-01 | 1999-04-23 | Denso Corp | 半導体基板およびその製造方法 |
FR2765398B1 (fr) * | 1997-06-25 | 1999-07-30 | Commissariat Energie Atomique | Structure a composant microelectronique en materiau semi-conducteur difficile a graver et a trous metallises |
JPH1126733A (ja) * | 1997-07-03 | 1999-01-29 | Seiko Epson Corp | 薄膜デバイスの転写方法、薄膜デバイス、薄膜集積回路装置,アクティブマトリクス基板、液晶表示装置および電子機器 |
JPH1197379A (ja) * | 1997-07-25 | 1999-04-09 | Denso Corp | 半導体基板及び半導体基板の製造方法 |
FR2774214B1 (fr) * | 1998-01-28 | 2002-02-08 | Commissariat Energie Atomique | PROCEDE DE REALISATION D'UNE STRUCTURE DE TYPE SEMI-CONDUCTEUR SUR ISOLANT ET EN PARTICULIER SiCOI |
JP2000036609A (ja) * | 1998-05-15 | 2000-02-02 | Canon Inc | 太陽電池の製造方法と薄膜半導体の製造方法、薄膜半導体の分離方法及び半導体形成方法 |
FR2781925B1 (fr) * | 1998-07-30 | 2001-11-23 | Commissariat Energie Atomique | Transfert selectif d'elements d'un support vers un autre support |
JP4476390B2 (ja) * | 1998-09-04 | 2010-06-09 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
JP2000124092A (ja) * | 1998-10-16 | 2000-04-28 | Shin Etsu Handotai Co Ltd | 水素イオン注入剥離法によってsoiウエーハを製造する方法およびこの方法で製造されたsoiウエーハ |
FR2784795B1 (fr) * | 1998-10-16 | 2000-12-01 | Commissariat Energie Atomique | Structure comportant une couche mince de materiau composee de zones conductrices et de zones isolantes et procede de fabrication d'une telle structure |
US6744800B1 (en) * | 1998-12-30 | 2004-06-01 | Xerox Corporation | Method and structure for nitride based laser diode arrays on an insulating substrate |
US6326279B1 (en) * | 1999-03-26 | 2001-12-04 | Canon Kabushiki Kaisha | Process for producing semiconductor article |
US6355541B1 (en) * | 1999-04-21 | 2002-03-12 | Lockheed Martin Energy Research Corporation | Method for transfer of thin-film of silicon carbide via implantation and wafer bonding |
AU6795200A (en) * | 1999-08-26 | 2001-03-19 | Exxonmobil Research And Engineering Company | Superheating atomizing steam with hot fcc feed oil |
WO2002084725A1 (fr) * | 2001-04-17 | 2002-10-24 | California Institute Of Technology | Procede utilisant un transfert de la couche au germanium au si pour applications photovoltaiques, et heterostructures realisees par ce procede |
JP4097510B2 (ja) * | 2002-11-20 | 2008-06-11 | 株式会社沖データ | 半導体装置の製造方法 |
JP5102445B2 (ja) | 2005-12-08 | 2012-12-19 | カゴメ株式会社 | 加熱手段を備えたストレーナー、ならびに、凍結濃縮汁の解凍システム及びその解凍方法 |
-
2000
- 2000-11-06 FR FR0014170A patent/FR2816445B1/fr not_active Expired - Lifetime
-
2001
- 2001-11-02 TW TW090127343A patent/TW513752B/zh not_active IP Right Cessation
- 2001-11-05 CN CNB018183360A patent/CN1327505C/zh not_active Expired - Lifetime
- 2001-11-05 KR KR1020037006179A patent/KR100855083B1/ko active IP Right Grant
- 2001-11-05 US US10/415,672 patent/US6974759B2/en not_active Expired - Lifetime
- 2001-11-05 JP JP2002540206A patent/JP2004513517A/ja active Pending
- 2001-11-05 AU AU2002223735A patent/AU2002223735A1/en not_active Abandoned
- 2001-11-05 WO PCT/FR2001/003401 patent/WO2002037556A1/fr active Application Filing
- 2001-11-05 EP EP01993021.3A patent/EP1344249B1/fr not_active Expired - Lifetime
-
2005
- 2005-09-23 US US11/233,785 patent/US8481409B2/en active Active
-
2009
- 2009-01-23 JP JP2009013500A patent/JP5528711B2/ja not_active Expired - Lifetime
-
2013
- 2013-03-06 JP JP2013044223A patent/JP5770767B2/ja not_active Expired - Lifetime
- 2013-03-15 US US13/841,196 patent/US8679946B2/en not_active Expired - Lifetime
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5391257A (en) * | 1993-12-10 | 1995-02-21 | Rockwell International Corporation | Method of transferring a thin film to an alternate substrate |
FR2781082A1 (fr) * | 1998-07-10 | 2000-01-14 | Commissariat Energie Atomique | Structure semiconductrice en couche mince comportant une couche de repartition de chaleur |
WO2000019499A1 (fr) * | 1998-09-30 | 2000-04-06 | MAX-PLANCK-Gesellschaft zur Förderung der Wissenschaften e.V. | Procede de transfert de couches minces de matiere monocristalline sur un substrat voulu |
Non-Patent Citations (2)
Title |
---|
HAMAGUCHI T ET AL: "NOVEL LSI/SOI WAFER FABRICATION USING DEVICE LAYER TRANSFER TECHNIQUE", WASHINGTON, DEC. 1 - 4, 1985,WASHINGTON, IEEE,US, vol. -, 1 December 1985 (1985-12-01), pages 688 - 691, XP002037723 * |
ISHIKAWA Y ET AL: "EFFECTS OF ELECTRON TUNNELING INTO A SINGLE-CRYSTALLINE SI LAYER THROUGH AN ULTRATHIN BURIED OXIDE", EXTENDED ABSTRACTS OF THE INTERNATIONAL CONFERENCE ON SOLID STATE DEVICES AND MATERIALS,JAPAN SOCIETY OF APPLIED PHYSICS. TOKYO,JA, September 1998 (1998-09-01), pages 182 - 183, XP000823131 * |
Cited By (33)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8507361B2 (en) | 2000-11-27 | 2013-08-13 | Soitec | Fabrication of substrates with a useful layer of monocrystalline semiconductor material |
US7615468B2 (en) | 2000-11-27 | 2009-11-10 | S.O.I.Tec Silicon On Insulator Technologies | Methods for making substrates and substrates formed therefrom |
US7839001B2 (en) | 2000-11-27 | 2010-11-23 | S.O.I.Tec Silicon On Insulator Technologies | Methods for making substrates and substrates formed therefrom |
US7265029B2 (en) | 2000-11-27 | 2007-09-04 | S.O.I.Tec Silicon On Insulator Technologies | Fabrication of substrates with a useful layer of monocrystalline semiconductor material |
US7888235B2 (en) | 2000-11-27 | 2011-02-15 | S.O.I.Tec Silicon On Insulator Technologies | Fabrication of substrates with a useful layer of monocrystalline semiconductor material |
US7939428B2 (en) | 2000-11-27 | 2011-05-10 | S.O.I.Tec Silicon On Insulator Technologies | Methods for making substrates and substrates formed therefrom |
US8252664B2 (en) | 2000-11-27 | 2012-08-28 | Soitec | Fabrication of substrates with a useful layer of monocrystalline semiconductor material |
US10002763B2 (en) | 2000-11-27 | 2018-06-19 | Soitec | Fabrication of substrates with a useful layer of monocrystalline semiconductor material |
WO2003063214A2 (fr) * | 2002-01-22 | 2003-07-31 | S.O.I.Tec Silicon On Insulator Technologies | Procede de preparation d'ensembles semi-conducteurs separable, en particulier pour former des substrats pour composants electroniques, optoelectroniques et optiques |
CN100444318C (zh) * | 2002-01-22 | 2008-12-17 | S.O.I.Tec绝缘体上硅技术公司 | 用于制备可分离半导体组件的工艺、特别是制成电子器件、光电器件和光学器件用的衬底 |
US7256101B2 (en) | 2002-01-22 | 2007-08-14 | S.O.I.Tec Silicon On Insulator Technologies | Methods for preparing a semiconductor assembly |
WO2003063214A3 (fr) * | 2002-01-22 | 2003-11-27 | Soitec Silicon On Insulator | Procede de preparation d'ensembles semi-conducteurs separable, en particulier pour former des substrats pour composants electroniques, optoelectroniques et optiques |
WO2003105219A1 (fr) * | 2002-06-11 | 2003-12-18 | S.O.I.T.E.C. Silicon On Insulator Technologies | Procede de production d'un substrat comprenant une couche utile de materiau semi-conducteur monocristallin |
FR2840730A1 (fr) * | 2002-06-11 | 2003-12-12 | Soitec Silicon On Insulator | Procede de fabrication d'un substrat comportant une couche utile en materiau semi-conducteur monocristallin de proprietes ameliorees |
WO2004010494A3 (fr) * | 2002-07-18 | 2004-04-08 | Commissariat Energie Atomique | Procede de transfert d'une couche mince electriquement active |
WO2004010494A2 (fr) * | 2002-07-18 | 2004-01-29 | Commissariat A L'energie Atomique | Procede de transfert d'une couche mince electriquement active |
FR2842648A1 (fr) * | 2002-07-18 | 2004-01-23 | Commissariat Energie Atomique | Procede de transfert d'une couche mince electriquement active |
EP1408545A2 (fr) * | 2002-10-07 | 2004-04-14 | S.O.I. Tec Silicon on Insulator Technologies | Procédé pour réaliser un substrat par transfert d'une plaquette donneuse comportant des espèces étrangères, et plaquette donneuse associée |
EP1408545A3 (fr) * | 2002-10-07 | 2004-08-04 | S.O.I. Tec Silicon on Insulator Technologies | Procédé pour réaliser un substrat par transfert d'une plaquette donneuse comportant des espèces étrangères, et plaquette donneuse associée |
FR2845523A1 (fr) * | 2002-10-07 | 2004-04-09 | Soitec Silicon On Insulator | Procede pour realiser un substrat par transfert d'une plaquette donneuse comportant des especes etrangeres, et plaquette donneuse associee |
US7645684B2 (en) | 2002-10-07 | 2010-01-12 | S.O.I.Tec Silicon On Insulator Technologies | Wafer and method of producing a substrate by transfer of a layer that includes foreign species |
US7535115B2 (en) | 2002-10-07 | 2009-05-19 | S.O.I.Tec Silicon On Insulator Technologies | Wafer and method of producing a substrate by transfer of a layer that includes foreign species |
US7008859B2 (en) | 2002-10-07 | 2006-03-07 | S.O.I.Tec Silicon On Insulator Technologies S.A. | Wafer and method of producing a substrate by transfer of a layer that includes foreign species |
JP2004179630A (ja) * | 2002-10-07 | 2004-06-24 | Soi Tec Silicon On Insulator Technologies | 異物種を含有するドナーウエハを転写することによる基板の製造方法および関連するドナーウエハ |
US7329587B2 (en) | 2003-06-24 | 2008-02-12 | Osram Opto Semiconductors Gmbh | Method for the production of semi-conductor chips |
WO2005004231A1 (fr) * | 2003-06-24 | 2005-01-13 | Osram Opto Semiconductors Gmbh | Procede de fabrication de puces a semi-conducteur |
US7465645B2 (en) | 2003-08-04 | 2008-12-16 | S.O.I.Tec Silicon On Insulator Technologies | Method of detaching a layer from a wafer using a localized starting area |
US9011598B2 (en) | 2004-06-03 | 2015-04-21 | Soitec | Method for making a composite substrate and composite substrate according to the method |
FR3042647A1 (fr) * | 2015-10-20 | 2017-04-21 | Soitec Silicon On Insulator | Structure composite et procede de fabrication associe |
WO2017068270A1 (fr) * | 2015-10-20 | 2017-04-27 | Soitec | Structure composite et procédé de fabrication associé |
CN108271425A (zh) * | 2015-10-20 | 2018-07-10 | 索泰克公司 | 复合结构及相关制造方法 |
WO2019186267A1 (fr) | 2018-03-29 | 2019-10-03 | Soitec | Procede de transfert d'une couche |
US11501997B2 (en) | 2018-03-29 | 2022-11-15 | Soitec | Process for transferring a layer |
Also Published As
Publication number | Publication date |
---|---|
JP5770767B2 (ja) | 2015-08-26 |
JP5528711B2 (ja) | 2014-06-25 |
US20040014299A1 (en) | 2004-01-22 |
KR20030051782A (ko) | 2003-06-25 |
FR2816445A1 (fr) | 2002-05-10 |
US6974759B2 (en) | 2005-12-13 |
CN1473361A (zh) | 2004-02-04 |
EP1344249A1 (fr) | 2003-09-17 |
FR2816445B1 (fr) | 2003-07-25 |
KR100855083B1 (ko) | 2008-08-29 |
US20130230967A1 (en) | 2013-09-05 |
TW513752B (en) | 2002-12-11 |
JP2009081478A (ja) | 2009-04-16 |
JP2004513517A (ja) | 2004-04-30 |
CN1327505C (zh) | 2007-07-18 |
US20060079071A1 (en) | 2006-04-13 |
AU2002223735A1 (en) | 2002-05-15 |
US8481409B2 (en) | 2013-07-09 |
EP1344249B1 (fr) | 2017-01-18 |
JP2013138248A (ja) | 2013-07-11 |
US8679946B2 (en) | 2014-03-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP1344249B1 (fr) | Procédé de fabrication d'une structure empilée comprenant une couche mince adhérant à un substrat cible | |
EP1423873B1 (fr) | Procede d'obtention d'une couche mince auto-portee d'un materiau semi-conducteur supportant au moins un composant et/ou circuit electronique | |
EP1922752B1 (fr) | Procede de report d'une couche mince sur un support | |
EP2342744B1 (fr) | Procede de formation d'une couche monocristalline dans le domaine micro-electronique | |
EP1631983A1 (fr) | Procede d'obtention concomitante d'une paire de substrats recouverts d'une couche utile | |
FR2910702A1 (fr) | Procede de fabrication d'un substrat mixte | |
EP1879220A2 (fr) | Procédé de collage hydrophobe direct de deux substrats utilisés en électronique, optique ou opto-électronique. | |
WO2001093325A1 (fr) | Substrat fragilise et procede de fabrication d'un tel substrat | |
EP2764535B1 (fr) | Procédé de double report de couche | |
FR2905801A1 (fr) | Procede de transfert d'une couche a haute temperature | |
FR2907966A1 (fr) | Procede de fabrication d'un substrat. | |
FR2950734A1 (fr) | Procede de collage et de transfert d'une couche | |
FR3094573A1 (fr) | Procede de preparation d’une couche mince de materiau ferroelectrique | |
FR2977069A1 (fr) | Procede de fabrication d'une structure semi-conductrice mettant en oeuvre un collage temporaire | |
EP1631982B1 (fr) | Procede d'obtention d'une couche tres mince par amincissement par auto-portage provoque | |
FR2860340A1 (fr) | Collage indirect avec disparition de la couche de collage | |
FR2968121A1 (fr) | Procede de transfert d'une couche a haute temperature | |
EP3766094B1 (fr) | Procédé de préparation d'une couche mince de matériau ferroélectrique à base d'alcalin | |
FR2858461A1 (fr) | Realisation d'une structure comprenant une couche protegeant contre des traitements chimiques | |
FR2866982A1 (fr) | Procede de fabrication de composants electroniques | |
WO2023144495A1 (fr) | Procede de fabrication d'une structure de type double semi-conducteur sur isolant | |
WO2021144534A1 (fr) | Procédé de fabrication d'un capteur d'image | |
FR3108439A1 (fr) | Procede de fabrication d’une structure empilee |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
DFPE | Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101) | ||
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
REEP | Request for entry into the european phase |
Ref document number: 2001993021 Country of ref document: EP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2001993021 Country of ref document: EP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2002540206 Country of ref document: JP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 10415672 Country of ref document: US Ref document number: 018183360 Country of ref document: CN |
|
WWE | Wipo information: entry into national phase |
Ref document number: 1020037006179 Country of ref document: KR |
|
WWP | Wipo information: published in national office |
Ref document number: 1020037006179 Country of ref document: KR |
|
WWP | Wipo information: published in national office |
Ref document number: 2001993021 Country of ref document: EP |
|
REG | Reference to national code |
Ref country code: DE Ref legal event code: 8642 |