AU2002223735A1 - Method for making a stacked structure comprising a thin film adhering to a target substrate - Google Patents

Method for making a stacked structure comprising a thin film adhering to a target substrate

Info

Publication number
AU2002223735A1
AU2002223735A1 AU2002223735A AU2373502A AU2002223735A1 AU 2002223735 A1 AU2002223735 A1 AU 2002223735A1 AU 2002223735 A AU2002223735 A AU 2002223735A AU 2373502 A AU2373502 A AU 2373502A AU 2002223735 A1 AU2002223735 A1 AU 2002223735A1
Authority
AU
Australia
Prior art keywords
making
thin film
stacked structure
target substrate
film adhering
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2002223735A
Other languages
English (en)
Inventor
Bernard Aspar
Eric Jalaguier
Fabrice Letertre
Hubert Moriceau
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat a lEnergie Atomique CEA filed Critical Commissariat a lEnergie Atomique CEA
Publication of AU2002223735A1 publication Critical patent/AU2002223735A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Element Separation (AREA)
AU2002223735A 2000-11-06 2001-11-05 Method for making a stacked structure comprising a thin film adhering to a target substrate Abandoned AU2002223735A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR0014170 2000-11-06
FR0014170A FR2816445B1 (fr) 2000-11-06 2000-11-06 Procede de fabrication d'une structure empilee comprenant une couche mince adherant a un substrat cible
PCT/FR2001/003401 WO2002037556A1 (fr) 2000-11-06 2001-11-05 Procede de fabrication d'une structure empilee comprenant une couche mince adherant a un substrat cible

Publications (1)

Publication Number Publication Date
AU2002223735A1 true AU2002223735A1 (en) 2002-05-15

Family

ID=8856075

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2002223735A Abandoned AU2002223735A1 (en) 2000-11-06 2001-11-05 Method for making a stacked structure comprising a thin film adhering to a target substrate

Country Status (9)

Country Link
US (3) US6974759B2 (fr)
EP (1) EP1344249B1 (fr)
JP (3) JP2004513517A (fr)
KR (1) KR100855083B1 (fr)
CN (1) CN1327505C (fr)
AU (1) AU2002223735A1 (fr)
FR (1) FR2816445B1 (fr)
TW (1) TW513752B (fr)
WO (1) WO2002037556A1 (fr)

Families Citing this family (283)

* Cited by examiner, † Cited by third party
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FR2837981B1 (fr) * 2002-03-28 2005-01-07 Commissariat Energie Atomique Procede de manipulation de couches semiconductrices pour leur amincissement
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FR2845523B1 (fr) * 2002-10-07 2005-10-28 Procede pour realiser un substrat par transfert d'une plaquette donneuse comportant des especes etrangeres, et plaquette donneuse associee
FR2845518B1 (fr) * 2002-10-07 2005-10-14 Commissariat Energie Atomique Realisation d'un substrat semiconducteur demontable et obtention d'un element semiconducteur
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