WO2001058010A2 - Dispositifs et procedes d'etalonnage d'etages d'amplification et de compensation d'erreurs dans des composants montes en amont d'etages d'amplification - Google Patents

Dispositifs et procedes d'etalonnage d'etages d'amplification et de compensation d'erreurs dans des composants montes en amont d'etages d'amplification Download PDF

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Publication number
WO2001058010A2
WO2001058010A2 PCT/DE2001/000238 DE0100238W WO0158010A2 WO 2001058010 A2 WO2001058010 A2 WO 2001058010A2 DE 0100238 W DE0100238 W DE 0100238W WO 0158010 A2 WO0158010 A2 WO 0158010A2
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Prior art keywords
amplifier
amplifier stage
stage
calibrated
calibration
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PCT/DE2001/000238
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German (de)
English (en)
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WO2001058010A3 (fr
Inventor
Bernhard Engl
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Infineon Technologies Ag
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Application filed by Infineon Technologies Ag filed Critical Infineon Technologies Ag
Priority to US10/203,550 priority Critical patent/US7312732B2/en
Priority to AU2001237232A priority patent/AU2001237232A1/en
Priority to DE50115073T priority patent/DE50115073D1/de
Priority to EP01909504A priority patent/EP1290785B1/fr
Publication of WO2001058010A2 publication Critical patent/WO2001058010A2/fr
Publication of WO2001058010A3 publication Critical patent/WO2001058010A3/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/10—Calibration or testing
    • H03M1/1009—Calibration
    • H03M1/1014—Calibration at one point of the transfer characteristic, i.e. by adjusting a single reference value, e.g. bias or gain error
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
    • G11C27/02—Sample-and-hold arrangements
    • G11C27/024—Sample-and-hold arrangements using a capacitive memory element
    • G11C27/026—Sample-and-hold arrangements using a capacitive memory element associated with an amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
    • H03F3/45632—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit
    • H03F3/45744—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit by offset reduction
    • H03F3/45748—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit by offset reduction by using a feedback circuit
    • H03F3/45753—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit by offset reduction by using a feedback circuit using switching means, e.g. sample and hold
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
    • H03F3/45632—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit
    • H03F3/45744—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit by offset reduction
    • H03F3/45766—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit by offset reduction by using balancing means
    • H03F3/45771—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit by offset reduction by using balancing means using switching means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/331—Sigma delta modulation being used in an amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45048—Calibrating and standardising a dif amp
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/14—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit
    • H03M1/141—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit in which at least one step is of the folding type; Folding stages therefore

Definitions

  • the present invention relates to devices and methods for calibrating amplifier stages and for compensating for errors in components connected upstream of amplifier stages, by means of which errors caused in particular by statistical fluctuations in the component parameters (mismatch) and / or by integral non-linearity (INL) or differential non-linearity (DNL) caused can be eliminated or minimized.
  • the known devices and methods have the disadvantage that they can only be implemented with great effort and / or that they do not work as quickly and / or precisely as would be desirable in many cases.
  • the present invention is therefore based on the object of finding devices and methods for calibrating amplifier stages and for compensating for errors in components connected upstream of amplifier stages, which are simple to implement and nevertheless enable fast and accurate calibration or compensation.
  • FIG. 1 shows a section of a known analog / digital converter that works according to the folding principle (analog / digital converter that works according to the folding principle).
  • FIG. 2 shows a section of an embodiment of a folding converter according to the invention
  • FIG. 3 shows an illustration to explain the mode of operation of a first means from FIG. 2 with corresponding signals
  • FIG. 4 shows a circuit diagram of an embodiment of the first means
  • 5a to 7 are circuit diagrams of differential amplifiers with second means from FIG. 2,
  • FIG. 8 shows a circuit diagram of a third means from FIG. 2,
  • FIG. 9 shows a circuit diagram for explaining an analog self-calibration method
  • FIG. 10 shows a circuit diagram of the third means in the case of digital storage of the calibration values
  • FIGS. 11 to 19 are circuit diagrams of further designs of the first means, Figures 20a to 20c circuit diagrams to explain the effects of the first means,
  • FIG. 21 shows a circuit for explaining the calibration of individual current sources
  • FIG. 22 shows a further embodiment of FIG. 21,
  • FIG. 23 shows a circuit with sampling switches between the stages for pipeline operation
  • FIG. 24 shows a known amplifier stage, more precisely a differential broadband amplifier
  • FIG. 25 shows a selection of groups, signal processing chains, and signal processing trees which can be formed from such amplifier stages
  • FIG. 26 shows a basic circuit diagram to illustrate the device according to the invention
  • FIG. 27 shows an exemplary embodiment of a calibratable amplifier stage, which also contains parts of the memory unit that are responsible for it,
  • FIG. 28 shows a section of an ADC, which is based on the calibratable amplifier stage according to FIG. 27,
  • FIG. 29 shows a simple example of the circuitry implementation of the first means with transfer switches
  • FIG. 30 shows a simple example of the implementation of second means in terms of circuitry
  • FIG. 31 shows a simple example of the circuitry implementation of third means
  • Figure 32 shows another example of the circuitry
  • FIG. 33 shows an example of the use of second means in a two-stage amplifier suitable for folding ADCs
  • FIG. 34 shows an example of the implementation of second means in circuitry which is particularly suitable for folding ADCs and which also works in the case of a single-stage folding amplifier
  • FIG. 35 shows an inventive basic principle and exemplary embodiment of the circuit implementation of two means with particularly good common-mode suppression
  • Figure 36 shows an example of second means for setting a frequency response
  • FIG. 37 shows a particularly advantageous example of implementing third means, in which the capacitive load on nodes of the amplifier stage is minimized in normal operation
  • FIG. 38 shows an offset-compensatable variant of the third means
  • FIG. 40 shows an embodiment of the memory register with a combinatorial logic connected downstream, in which a particularly quick change between normal operation and calibration operation is possible
  • FIG. 41 the input stage of an ADC
  • FIGS. 42a and 42b block diagrams of a device for eliminating errors in a reference voltage divider chain
  • FIG. 43 shows the structure of the differential amplifier shown in FIG. 42b
  • FIGS. 44a and 44b further embodiments of a device for eliminating errors in a reference voltage divider chain
  • FIG. 45 shows the structure of a known sample-and-hold stage
  • FIG. 46 shows the structure of an arrangement which can be used as a separate-and-hold stage and for generating the calibration signals required for the calibration of the reference voltage divider chain
  • FIG. 47 shows the sequence of a reference voltage divider chain calibration using the arrangement shown in FIG. 46
  • FIG. 48 shows a representation of signals occurring during the reference voltage divider chain calibration
  • FIG. 49 shows a block diagram of an arrangement by means of which the method shown in FIGS. 47 and 48 can be implemented
  • FIG. 50 shows a plurality of differential amplifiers and a known input stage for fast ADCs containing this sample and hold stage
  • FIG. 51 a shows an arrangement with a first exemplary embodiment of a device for compensating for errors contained in a sample and hold stage
  • FIG. 51b shows an arrangement with a device provided for other differential amplifiers for compensating errors contained in a sample and hold stage
  • FIG. 52 shows the structure of one of the differential amplifiers shown in FIG. 51b
  • FIG. 53a shows an arrangement with a second exemplary embodiment of a device for compensating errors contained in a sample-and-hold stage
  • FIG. 53b shows an arrangement with a device provided for other differential amplifiers for compensating errors contained in a sample and hold stage
  • FIG. 54 a shows an arrangement with a device for compensating for errors contained in a sample and hold stage, two different reference voltage divider chains being used,
  • FIG. 54b shows an arrangement with a device provided for other differential amplifiers for compensating errors contained in a sample and hold stage
  • FIG. 55 shows a possible implementation of the means for setting the offset voltage of a differential amplifier.
  • P P- ⁇ PS P PS s P ⁇ PS ⁇ N P P ⁇ ⁇ TJ ⁇ r PS ⁇ ⁇ ⁇ P ⁇ J__ tr P- o O ⁇ ⁇
  • P- Pt 3 O P ⁇ P- Ph 0 P- ⁇ PS ⁇ N O 0 ⁇ P p- P. ⁇ EP 0 t tr ⁇ s: O P ⁇
  • P- ⁇ P- rt cn PPO P- cn PS P ⁇ P- er t tr 0 cn> P- o 0 ⁇ t ⁇ ⁇ ⁇ 0 cn ⁇ tr s ⁇ Cd ⁇ EP r cn PS P- s ⁇ ⁇ o ⁇ PS ⁇ 0 cn cn ⁇ 0 ⁇ 1 (- ⁇ 3
  • Thing - ADC not only offset differential pairs, but other components, such as resistors and current sources, which are also subject to a matching error and can cause both offset and gain errors, so that these error sources often have to be subjected to compensation.
  • a process in which all sources of error in the ADC are compensated for in a systematic manner is often referred to in the literature as "self-calibration", and this is very extensive for Flash, Subranging, Pipeline, Successive Approximation - ADCs etc. (e.g. [ 7] ... [10]).
  • Folding ADCs have so far not found any useful self-calibration procedure, presumably because the task mentioned above has not been able to solve this task due to the factors mentioned above.
  • Folding ADCs of higher resolution known in the literature e.g. [11] therefore resort to the use of BiCMOS processes in order to mitigate the offset problem on the basis of the bipolar transistors available there.
  • BiCMOS processes it does not achieve a nominal resolution of more than 12 bits [11], so that even if such a BiCMOS process was used, and not only with pure CMOS, it would be very useful for the designer to have a usable method for self-calibration. which can be applied in general to folding ADCs of most diverse architectures.
  • the present invention is essentially based on the fact that a self-calibration or a regulated calibration of a folding analog / digital converter by first means for sensitization, inhibition and activation of signal paths by the folding converter, by second means for generating an equilibrium state of the stages containing the first means , by third means for querying states in these stages and by fourth means for forming control signals depending on the queried states.
  • the previous state of the art is shown by way of example in FIG. 1. It is a section of a folding ADC with cascaded folding, ie the folding takes place in more than one folding stage. The purpose of this is to make the invention useful even for this more difficult one
  • a reference chain 1 leads to preamplifier 2 of a preamplifier stage VS, the outputs PPi and PMi of which lead to a first folding stage FS1 with differential amplifiers 3.
  • the outputs FIPj and FIMj of the first folding stage lead to a second folding stage FS2 with differential amplifiers 4, the outputs F2Pk and F2Mk of which lead to a comparator stage with interpolator 5 and subsequent comparators 6, the so-called bubble gates 7, the logic circuits for replacing bits with the value representing "0 ⁇ within bit sequences with the values of" l ⁇ and serve for correction of the folded thermometer code are followed, which act on a ROM or encoder 8 so as to come out at the output of low-order bits of the quantized input value.
  • the function and mode of operation of these parts per se and their circuitry structure can be assumed to be known to the person skilled in the art and is described in detail in the relevant literature [1] ... [5], [11].
  • Some more common variations of the basic circuit shown would be the installation of an additional interpolator after the first folding stage [11] or an averaging network [3].
  • the invention can be used for all of these cases and, of course, also for simple architectures with only one folding stage, or those architectures in which the preamplifiers are combined with the folding stage.
  • the combination of preamplifier / folding stage is to be regarded as a folding stage in the sense of the invention and to be equipped with the means according to the invention for folding stages.
  • the elements denoted by 2, 3, 4 are generally broad banded symmetrical differential amplifier consisting of a differential pair, a foot current source and a pair of load elements, mostly resistors, but also active circuits [3], which invert the input signal.
  • every second amplifier of this type is connected with interchanged outputs. This makes it difficult to assign the correct polarities to the differential signals P i, PPi, FIPj, FIMj, F2Pk, F2Mk, etc.
  • the polarity of the signal names is rather a convention of the designer and is therefore insignificant for the disclosure of the invention.
  • FIG. 2 shows a preferred exemplary embodiment of the device according to the invention in a folding converter.
  • the same basic circuit as in FIG. 1 is present, which is formed by first to fourth means 9, 10, 11; 13; 15 and 20 is added.
  • the first means 9, 10, 11 allow the inputs of circuit stages within the folding ADC to be disconnected from their normal sources and to be connected to auxiliary potentials 12 which are supplied to the means. These auxiliary potentials are chosen so that the circuit stages can assume certain operating points, which will be explained later in the description of the self-calibration method.
  • auxiliary potentials are represented in FIG. 2 by voltage sources, but can be taken from any point within the circuit in any way, as long as the effects of the first means according to the invention are achieved. These variations are shown later as examples. In particular, there are a large number of variants for the possible implementation of the first means 9 acting on the first stage.
  • the first means 10 which are provided at the input of folding stages, have at least four operating states or oo N. ro P »P- 1
  • P- P- P- TJ rt PS er PS os P- 0 ⁇ ⁇ ⁇ 0 0 ⁇ ⁇ ⁇ ⁇ P- 1 K 3 rt 0 o ⁇ o TJ 0 P- P s P- o P-
  • the second means 13 within the circuit stages with first means make it possible to adjust the equilibrium state within the circuit stages via control inputs 14.
  • the presence of the second means within a symbol is represented by a smaller number "13" next to the larger type number of the symbol 2, 3, 4 or 6.
  • the third means 15 on or in the comparators allow the state of the comparator to be evaluated without this information being falsified by the logic following the comparator.
  • These third means can be additional outputs on the comparator, or means for direct observation of individual comparator outputs, such as a multiplexer consisting of tristate drivers, which selects individual comparator outputs, and leads to busbars.
  • a multiplexer consisting of tristate drivers, which selects individual comparator outputs, and leads to busbars.
  • PS M P- ⁇ cn o ⁇ ⁇ S P rt cn er S ⁇ P P 0 tr P- 0 rt
  • P- P TJ 0 P 0 er P- 0 P- rt p: ⁇ ⁇ P- p- ⁇ 0 ⁇ PP 0 o ⁇ ⁇ PPO P- 0 o P- P s P- PS EP cn ⁇ rt 0 rt ⁇ tr P- h-> ⁇ P 0 p- 0 ⁇ P- 1 P- 1 0 PS P EP P- 1 PS s ⁇ P "s EP
  • P- ⁇ 0 P- ⁇ tr 0 PS P.
  • FIGS. 5a to 5c each show an example of a typical internal circuit of preamplifiers 2 and folding stages 3, 4 equipped with the second means 13 according to the invention.
  • the inputs 33 and 34 of the preamplifiers according to FIG. 5a lead to a differential pair 30 with a foot current source 31
  • Outputs of the differential pair lead to load elements 32.
  • Resistors as shown in these figures or active circuits can be considered as load elements.
  • the common nodes of the outputs of the differential pair and the load elements lead to the outputs of stage 35, 36.
  • the second means 13 are also connected with their outputs 37 to the nodes connected to the outputs 35, 36. Their function is to draw an adjustable current from the connected nodes controlled by the inputs 14 at the outputs 37.
  • FIG. 5b shows a circuit which is particularly suitable for folding stages and which has the advantage that the setting process of the second means has no influence on the total current through the load elements connected to the outputs 35, 36, so that there is a possibility of a simplified implementation of the second means , which is shown later in Figure 7.
  • Typical variants of these exemplary basic circuits would be, in addition to the use of active circuits as load elements already mentioned, the installation of cascodes at the output of the differential pairs, or, for low supply voltages, a folding of the circuit structure, as described as
  • a further patent application relates to a system which is particularly suitable for this solution and consists of the self-calibrating ADC according to the invention and a digital filter which compensates for the gaps in the quantized data stream resulting from the self-calibration steps.
  • the digital implementation of the second means shown consists of weighted current sources 40 which can be connected to the outputs 37 of the second means via controllable switches 26.
  • the current I of the weighted current sources is to be selected so that the expected errors in the equilibrium state can be set to target in any case. As a rule, this current is orders of magnitude lower than that of the foot current source of the differential pair of the stage on which the second means act.
  • the digital control signals can be stored at a central point, for example within the fourth means, or locally at the second means by adding a register, which is not shown in the figure for reasons of these two existing options.
  • the solution with local storage of the calibration information is particularly advantageous when a large number of second means have to be operated, so that in total a large number of signal lines to the inputs 14 would be required.
  • Addressable registers for digital storage of the calibration information which are each arranged locally near the second means, and via a common co co t) t P > cn o cn o c ⁇ o C ⁇
  • P--- 0 Pt Q rt -> ⁇ ⁇ ⁇ P- 1 ⁇ PS rt P- 1 P- 1 P.
  • P TJ O O 0 P- X er cn ⁇ P- tr 0 rt ⁇ s N P- 1 cn S 0 ⁇ ⁇ P- tr 0
  • P. s ⁇ s CO SX ⁇ P ⁇ Pt OP PS rx PS ⁇ Pt 0 ⁇ P ⁇ P. Pt P- P- ⁇ ⁇ -3 P ⁇ 0 P o ⁇ P- cn 0 tr cn ⁇ P- P- ⁇ 0 O: cn P- • 0 0 S ⁇ cn C ⁇ ⁇ ⁇ P ⁇ &
  • PS PS 0 F- Pt tr tr o ⁇ o ⁇ 0 1 O cn ⁇ P cn M PS ⁇ P PS ⁇ er ⁇ PS>
  • F- p 0 s ⁇ P P TJ N iQ P.
  • EP ⁇ F- 0 P ⁇ F- PS 0 P 0 cn cn 0 rt F- rt F-
  • a second operating state 01 the first input is connected to a low auxiliary voltage VL, the second input to a higher auxiliary voltage VH, each of which comes from voltage sources 12.
  • VL low auxiliary voltage
  • VH higher auxiliary voltage
  • the first input is connected to a higher auxiliary voltage VH, the second input to a lower auxiliary voltage VL.
  • VH auxiliary voltage
  • VL auxiliary voltage
  • a fourth operating state 11 the first input and the second input are connected to the tap VRi + 1, VRi or VRi-1 of the reference voltage divider 1 assigned to the preamplifier, so that there is a state of equilibrium at the outputs PMi and PPi, in the figure by a Symbolizes equal sign.
  • This realizes the fourth effect of the first means, which is used during the calibration process if this state of equilibrium is to be brought to target by the second means.
  • PS Cd 10 ⁇ > P- vP ⁇ ⁇ ⁇ d 0 P F- p tr PS F- ⁇ PJ cn ⁇ P. ⁇ ⁇ F- cn PS 0 ⁇ ⁇ PS ⁇ o cn ⁇ iQ H ⁇ - cn F- F- cn PP vQ P 0 ⁇ tr ⁇ 5! rt Ph p.
  • PS p ⁇ 0 P p PS rt H cd 00 P. ⁇ rt 3 P p- er vP er F- ⁇ ⁇ O PS rt
  • one differential level is calibrated after the other, the differential level to be calibrated being brought into balance (sensitized) by the fourth effect of the first means, and the uninvolved differential levels being prevented (inhibited) by the second and third effects of the first means.
  • the signal path is activated via the first effect of the first means, which corresponds to normal operation, via all the differential stages following the sensitized differential stage up to the third means.
  • the digital control unit contained in the fourth means makes the calibration decision as to how the second means are to be set in order to bring the equilibrium state to the desired value, or allows the circuit to do this automatically by means of an activated analog feedback loop.
  • this calibration information obtained in this way is stored in the sensitized differential level.
  • the digital control unit opens the sampling switches in the second means assigned to the differential stage; in the case of digital implementation, the value determined is stored in a register contained in the second means or at another suitable location.
  • the self-calibration process begins with the stage furthest away from the entrance of the ADC and equipped with the first and second means according to the invention. If all levels have these means, the self-calibration procedure begins with the calibration of all differential levels of the comparators. All differential stages of the last folding stage are then calibrated. Once these have been calibrated, it is the turn of the previous stage viewed from the input of the ADC until the first stage is calibrated.
  • the invention has several variants discloses how this first stage can be calibrated, including variants which also calibrate out the mismatch errors of the reference chain. At the end of the self-calibration process, an almost ideal folding ADC is available, which remains almost ideal as long as the stored self-calibration information remains valid.
  • the invention can be used generally for self-calibration of structures with convergent and reconvergent signal paths. Now that all the basics and modes of operation of the invention have been disclosed, it should be readily possible for the person skilled in the art to implement the invention. It is readily possible for a person skilled in the art to derive variations in the circuits and solutions shown that deviate from the pictorial representation, but have the same or a similar mode of operation. In particular, it is possible for the person skilled in the art to improve circuit details, for example by installing cascodes or deriving complementary circuits, introducing partially bipolar transistors instead of the MOSFETs, etc. It is also possible to calibrate several signal paths simultaneously if the fourth means according to the invention be designed accordingly and the control and signal line bundles leading to and from the fourth means are designed correspondingly extensively.
  • Converters and also in other circuits that contain one or more amplifier stages, a sample and hold stage and / or a reference voltage divider are used.
  • the device and the method for calibrating a group of amplifier stages are started, whereby
  • Group of amplifier stages are to be understood as circuit structures composed of chains or trees of amplifier stages, - The group of amplifier stages can (but does not have to) be part of an integrated circuit, and
  • mismatch means or the setting of a certain property, e.g. reinforcing the levels.
  • Circuit structures made up of chains or trees of amplifier stages referred to in the text with the generic term "groups of amplifier stages", since the most varied topology variants can occur can be found, for example, in so-called flash or folding analog / digital converters, ADCs, many, sometimes hundreds or can contain thousands of individual amplifier stages, which are usefully connected to groups of amplifier stages.
  • FIG. 24 shows a typical example of an amplifier stage for ADCs, for which the invention is particularly suitable, and the symbol used for this in the later figures.
  • the invention can also be used to advantage in many other types of amplifiers if a larger number, i.e. a group, and a calibration of its parameters is necessary.
  • the devices and methods described below can also be used for individual amplifier stages, i.e. use amplifier stages that are not part of a group of amplifier stages and that the amplifier stage to be calibrated.
  • the amplifier stages to be calibrated also do not have to be part of an ADC, but can also be contained in any other devices. Designate in Figure 24
  • E1, E2 differential inputs which lead to the gates of MOSFETs T1, T2,
  • IS is a foot power source of the differential pair thus formed
  • RI and R2 load elements of the MOSFETS which are shown here by way of example as resistors, but can be replaced by MOSFETs or other active circuits (see for example [4]) both here and in the arrangements shown in the further figures, and
  • amplifier stages according to FIG. 24 generally work without negative feedback and do not contain any compensation of the frequency response, they are not operational amplifiers. For this, their signal processing bandwidth is usually very large, and the gain per stage is relatively low, a typical value for fast ADCs in the range of a few 100 MHz signal bandwidth is an amplification factor of only four.
  • an offset can not only be minimized, but can be set specifically to any values within a calibration range.
  • Structures that contain groups of amplifier stages can also be found in many other circuits, such as in the field of parallel signal processing, keyword neural networks, silicon retina, integrated sensor fields, etc., and also here it is desirable to have a method which allows a group of amplifier stages to be calibrated in an efficient manner.
  • the calibration device described contains
  • third means in order to be able to build up a clear signal path from the amplifier stage to be calibrated to at least one comparator unit
  • At least one comparator unit which can determine a match with a target value or the existence of an equilibrium state
  • the first, second and third means can be made digital
  • a digital storage unit which stores all or part of the control values of the first to third means for each calibratable amplifier stage and is designed such that the memory cells assigned to a calibratable amplifier stage are located near or in the calibratable amplifier stage,
  • control and selection or address lines are present which connect the control unit to the storage unit, so that these can select, read and write cells from the storage unit, and
  • the device and the method make it possible to carry out a cascaded stepwise calibration, in which already calibrated amplifier stages are used in order to amplify signals from amplifier stages preceding them in a signal path during the calibration before they reach the comparator unit.
  • Read / write memory can be understood, which is distributed systematically over the integrated circuit, and whose memory cells instead of just storing information also use this information to set analog parameters within amplifier stages that are interwoven with the memory field.
  • the content of the memory cells is manipulated by the control unit in such a way that the parameter of a selected amplifier stage measured via a comparator unit is brought to a desired value, the method described accomplishing this in a particularly efficient manner by - where oo 00 ro ro P>P> c ⁇ o Cn o C ⁇ o C ⁇
  • FIG. 25a shows a chain connection of amplifier stages shown in FIG. 24, which is typical for flash ADCs.
  • the input of the ADC is labeled E here
  • the reference voltages from the reference divider chain RK are labeled VRi-1, VRi, VRi + 1.
  • the arrangement shown in FIG. 25a contains several amplifier stage chain circuits; one of the chain circuits is e.g. from amplifier stages VI and V2 and the comparator CMP1.
  • FIG. 25b shows a tree structure typical of folding ADCs of amplifier stages shown in FIG. 24, in which, in contrast to a flash ADC, several amplifier stages V4, V5, V6 are connected at the outputs to enable a folding operation.
  • the described device and the described method are able to use such structures in a particularly efficient manner 00 00 ro ro P 1

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  • Amplifiers (AREA)

Abstract

L'invention concerne un mode d'étalonnage d'étages d'amplification comprenant les étapes suivantes : réunir les conditions préalables pour permettre un étalonnage des étages d'amplification ; comparer, entre eux ou avec des valeurs de référence associées, des signaux fournis par les étages d'amplification ou des grandeurs électriques intervenant dans les étages d'amplification et modifier les propriétés à étalonner des étages d'amplification en fonction du résultat de la comparaison. Les dispositifs et procédés décrits permettent d'échantillonner des étages d'amplification et de compenser des erreurs intervenant dans des étages d'amplification, rapidement et avec précision et de manière étonnamment simple.
PCT/DE2001/000238 2000-02-04 2001-01-19 Dispositifs et procedes d'etalonnage d'etages d'amplification et de compensation d'erreurs dans des composants montes en amont d'etages d'amplification WO2001058010A2 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
US10/203,550 US7312732B2 (en) 2000-02-04 2001-01-19 Devices and methods for calibrating amplifier stages and for compensating for errors in amplifier stages of series-connected components
AU2001237232A AU2001237232A1 (en) 2000-02-04 2001-01-19 Devices and methods for calibrating amplifier stages and for compensating for errors in amplifier stages of series-connected components
DE50115073T DE50115073D1 (de) 2000-02-04 2001-01-19 Vorrichtungen und verfahren zur kalibrierung von verstärkerstufen und zur kompensierung von fehlern in verstärkerstufen vorgeschalteten komponenten
EP01909504A EP1290785B1 (fr) 2000-02-04 2001-01-19 Dispositifs et procedes d'etalonnage d'etages d'amplification et de compensation d'erreurs dans des composants montes en amont d'etages d'amplification

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10004996.6 2000-02-04
DE10004996A DE10004996C2 (de) 2000-02-04 2000-02-04 Vorrichtung und Verfahren zur Selbstkalibrierung von Faltungs-Analog/Digitalwandlern

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WO2001058010A2 true WO2001058010A2 (fr) 2001-08-09
WO2001058010A3 WO2001058010A3 (fr) 2002-12-27

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US (1) US7312732B2 (fr)
EP (3) EP1603139B1 (fr)
AU (1) AU2001237232A1 (fr)
DE (4) DE10004996C2 (fr)
WO (1) WO2001058010A2 (fr)

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EP1603139A1 (fr) 2005-12-07
EP1619515B1 (fr) 2010-04-21
WO2001058010A3 (fr) 2002-12-27
US20030184459A1 (en) 2003-10-02
EP1619515A2 (fr) 2006-01-25
EP1290785B1 (fr) 2009-08-26
DE10004996C2 (de) 2002-09-26
AU2001237232A1 (en) 2001-08-14
DE50115449D1 (de) 2010-06-02
DE50115506D1 (de) 2010-07-15
EP1290785A2 (fr) 2003-03-12
EP1603139B1 (fr) 2010-06-02
DE50115073D1 (de) 2009-10-08
DE10004996A1 (de) 2001-08-09
US7312732B2 (en) 2007-12-25
EP1619515A3 (fr) 2006-02-15

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