WO1997045960A1 - Convertisseur analogique-numerique a etalonnage automatique et dispositif de detection le comprenant - Google Patents

Convertisseur analogique-numerique a etalonnage automatique et dispositif de detection le comprenant Download PDF

Info

Publication number
WO1997045960A1
WO1997045960A1 PCT/SE1997/000947 SE9700947W WO9745960A1 WO 1997045960 A1 WO1997045960 A1 WO 1997045960A1 SE 9700947 W SE9700947 W SE 9700947W WO 9745960 A1 WO9745960 A1 WO 9745960A1
Authority
WO
WIPO (PCT)
Prior art keywords
analog
converter
value
digital converter
digital
Prior art date
Application number
PCT/SE1997/000947
Other languages
English (en)
Inventor
Ulf Ringh
Christer Jansson
Original Assignee
Försvarets Forskningsanstalt
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Försvarets Forskningsanstalt filed Critical Försvarets Forskningsanstalt
Publication of WO1997045960A1 publication Critical patent/WO1997045960A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/10—Calibration or testing
    • H03M1/1009—Calibration
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/14—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit
    • H03M1/145—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit the steps being performed sequentially in series-connected stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/36—Analogue value compared with reference values simultaneously only, i.e. parallel type
    • H03M1/361—Analogue value compared with reference values simultaneously only, i.e. parallel type having a separate comparator and reference value for each quantisation level, i.e. full flash converter type
    • H03M1/362—Analogue value compared with reference values simultaneously only, i.e. parallel type having a separate comparator and reference value for each quantisation level, i.e. full flash converter type the reference values being generated by a resistive voltage divider
    • H03M1/365—Analogue value compared with reference values simultaneously only, i.e. parallel type having a separate comparator and reference value for each quantisation level, i.e. full flash converter type the reference values being generated by a resistive voltage divider the voltage divider being a single resistor string
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/50—Analogue/digital converters with intermediate conversion to time interval

Definitions

  • the present invention relates to an autocalibrating analog-to-digital converter and a sensor device comprising such a converter.
  • ADC analog-to-digital converters
  • the drawbacks are that the input signal must be band- limited and that the converted digital signal only corresponds to the frequency con ⁇ tent of the analog signal, whereby individual or individually independent analog data samples cannot be converted. Moreover, there is a need of a so-called decimation filter which requires a large silicon area and consumes a great part of the total power.
  • the drawback of double ramp converters and pulse-counting converters is the low conversion rate.
  • the A/D converter called Pulse Rest ADC (PR-ADC)
  • PR-ADC Pulse Rest ADC
  • the PR-ADC is a hybrid converter, which in a first phase converts the most signifi ⁇ cant bits by a method which is robust in respect of component tolerances and which thus can achieve an extremely high accuracy. After having converted so many of the most significant bits that the remaining bits are no more than 8-10, this first phase is interrupted.
  • the invention has been developed for digitising the signals from an infrared (IR) sensor, and therefore the specification is based on this use.
  • IR infrared
  • the invention has other conceivable fields of utilisation, such as telecommunications, hearing aids, audio products, measuring equipment etc, which means that the patent protection applied for expressly concerns a general use.
  • Fig. 1 shows a prior-art feedback integrator, on which the invention is based
  • Fig. 2 shows a prior-art analog-to-digital converter, on which the invention is based
  • Fig. 3 shows a prior-art analog part of a converter with a chopping input
  • Fig. 4 shows a prior-art sensor device using a converter according to the previous Figures
  • Fig. 5 shows a first embodiment of an inventive compensation of charge injection in devices according to Figs 1-4
  • Fig. 6 shows a second embodiment of an inventive compensation of charge injection in devices according to Figs 1-4
  • Fig. 7 shows a third embodiment of an inventive compensation of charge injection in devices according to Figs 1-4
  • Fig. 8 shows calibration of the feedback levels in a device according to the invention.
  • a PR-ADC As the basis of the specification of the invention, an embodiment of a PR-ADC will first be described, and then a modification according to the present invention is described.
  • the PR-ADC involved is built around a feedback integrator according to Fig. 1 , which is reset to zero before each conversion. If it were not for the negative feedback via the digital-to-analog converter (DAC), the input signal would, after some clock cycles, saturate the integrator owing to the accumulation of the signal.
  • DAC digital-to-analog converter
  • the feedback is time-discrete and is updated at each positive clock edge and the time therebetween constitutes an integration period. Only three feedback levels are possible in the example, +ref, 0, or -ref, where +ref increases the value of the inte- grator, -ref decreases this and 0 has no effect at all.
  • thresholding the value of the integrator with a comparator it is determined whether the feedback level -ref or +ref is to be used. Zero feedback is used during the first integration cycle only.
  • the absolute level of the feedback, ref is set such that it can precisely counteract the greatest input signal amplitude. The maximum input signal then gives the feedback -ref all the time, and the minimum input signal +ref.
  • n n ⁇ + n2-
  • 2 n 1
  • the binary value of this number then corresponds to the n-
  • the device functions during this first phase as a voltage-to-pulse- amount-converter, above referred to as a pulse-counting converter.
  • the input signal is disconnected to make the next phase function correctly.
  • the value of the integrator will after the first phase be the sum of the input signal and the registered feedback during these N-
  • the invention will be described below, based on the fact that the measured value which is the input signal to the device, has the form of a voltage.
  • the input signal may have other forms, such as current or charge. That stated below regarding residual voltage must then, of course, be read as residual value of the type concerned etc.
  • the conversion of the residual voltage requires but an accuracy and resolution corresponding to n2 bits and can therefore be carried out with traditional successive approximation, which yields a considerably faster rate of conversion than if the remaining bits should have been resolved by pulse counting.
  • the successive approximation is carried out by halving the absolute value of the feedback in each of the following n2 clock periods. Moreover, the input signal must be disabled by grounding the input. As a result, the n2 least significant bits at the output of the comparator are obtained with falling significance. To keep the intended accuracy, the n2 feedback levels must keep n2 bits precision.
  • input signal samples is obtained by weighting the number of negative feedbacks with the bits from the successive approximation as shown in Fig. 2.
  • the analog part in a PR-ADC implementation with a chopping input may be of the type as shown in Fig. 3.
  • the switches S re f and S ⁇ n ⁇ are both conductive, whereupon Cj n t loses its charge.
  • the subsequent integration is done such that the switches S re f and Sj n t alternate, which means that they are not conductive simultaneously.
  • the sign of the feedback is determined by the phase of this chopping, which in turn is determined by the decision of the comparator.
  • Zero feedback is solved by not chopping, i.e. fixing Sf ⁇ towards, for example, zero reference.
  • the feedback is halved by reducing the chopped voltage.
  • the time of conversion, t c is the sum of the time of the voltage-to-pulse-amount conversion during phase 1, t « j , and the time of the conversion of the residual volt ⁇ age during the second phase, t2- 1-) is linear to the resolution, i.e. t-j is the time of 2 n 1 clock periods and .2 is the time of n2 clock periods.
  • is most often much greater than t.2, and the total time of conversion can therefore be reduced considerably if the accuracy in the conversion of residual voltage can be increased. If, for instance, two bits can be moved from the first to the second phase, the time of conversion is decreased approximately four times.
  • the maladjustment in the charge injection depends, among other things, on the conditions that the control signals may have different rise and fall times, that the capacitive load on the switches is distributed differently, that the switches, owing to relative arrangement and orientation on the chip, are different, and that the manu ⁇ facturing process may cause local variations. Also leak currents in diffusions and transistors may occur.
  • the inaccuracy of the resistor ladder is derived from variation in geometry and resistivity over this.
  • the invention can be used to radically improve the accuracy in e.g. ADC based on successive approximation by calibration of the maladjustment in charge injection and resistor ladder.
  • the exemplified autocalibration uses the fact that the PR-ADC is suited for parallel implementation with a common resistor ladder. Extra parallel PR-ADC channels do therefore not cost much as to extra area and power, espe ⁇ cially if the application from the beginning requires a massive parallel conversion by maybe up to several hundred parallel channels.
  • the effect of the charge injection is represented by a small but constant input signal that is added to the integrator in each period.
  • the first phase is robust in respect of this and gives only one offset on the output, but the effect on the conversion of the residual voltage will be monotonicity errors, which restricts the accuracy. This is due to the fact that the charge injection shifts the correct threshold level from the com ⁇ parator level one bit for each clock period, which interferes with the successive approximation.
  • the charge injection is signal-independent in the given implementation and there- fore is the same for each clock period. If all channels have largely the same charge injection, an extra PR-ADC without input signal can be used to measure the charge injection. The measured charge injection is then allowed to control a compensation signal which enters all channels in parallel via an extra input with low amplification for the purpose of exactly subtracting the signal that is applied by the charge injection.
  • This measurement can be implemented in various ways, but it is important not to include any other offsets in the measurement since otherwise the estimation of the charge injection becomes incorrect.
  • the parallel and uniform structure must not be interrupted either since otherwise additional complexity and nonuniform charge injection are provided, which makes the compensation poor.
  • the absolute switching point of the comparator is not critical to the function of the converter in any phase, but deviations thereof from the initial value of the integrator introduce an equivalent offset on the input of the PR-ADC.
  • the initial value of the integrator is its voltage during resetting but is also to be found in each period when S re f is closed. When compensating, this offset will be spread over all the clock periods of the conversion. If the proportion of the number of clock periods in the first phase to that in the second phase is great, the total offset during the conversion of the residual voltage becomes small and therefore constitutes a problem only if the offset of the comparator is great.
  • the operational amplifier is of the type which, from voltages on the inputs, produces a current on the output, called OTA.
  • a field of utilisation which shows the applicability of the invention and also exempli- fies an embodiment is a 256x256 sensor array for infrared radiation with A/D con ⁇ version on the same chip shown in Fig. 4.
  • the relationship between the offset that the detectors have over the array and the generated signal amplitude for a desired temperature sensitivity of 0.1 °K requires an ADC resolution of at least 16 bits in order to manage the great dynamic range. With a view to managing both rate of conversion and resolution, a parallel solution by columns confers advantages.
  • the PR-ADC is very well suited for this solution.
  • the maximum clock frequency for accurate analog settling and the image frequency required result in an upper limit of about 8 bits for the first conversion phase of the PR-ADC. This results in a resolution of 8 bits for the conversion of the residual voltage. It has been found that the charge injection may then cause signifi ⁇ cant monotonicity errors. This depends on the fact that the silicon area which is available for each ADC is very restricted in this case, which implies that small capacitors must be used, which results in the circuit being subjected to charge injection to a greater extent. In case of still higher total resolutions of e.g. 18 bits, the compensation of the charge injection becomes even more significant.
  • FIG. 5 A first implementation of such compensation is illustrated in Fig. 5, where the extra ADC channel is shown in a block diagram.
  • the solution uses a resistor ladder, which makes the compensation static.
  • the resistor ladder can be the same as the one used for the generation of the feedback levels.
  • the compensation level, Vcomp, 's selected from a resistor ladder. This voltage is then chopped and buff ⁇ ered centrally and is applied in parallel on the compensation inputs of all the PR- ADC channels.
  • the input of the first channel, it ⁇ is indicated by a dashed thick line. Instead of being half the supply voltage as indicated, the chopping reference can be selected from the resistor ladder.
  • the compensation level can be stored in a digital register with an up and down counter, which feeds the decoder.
  • the adjustment of the compensation level is effected by counting up the value of the register if the compensation voltage is too low, and counting it down if the level is too high.
  • the up or down adjustment is controlled in the simplest way by using the available comparator in the circuit, as illustrated.
  • a decision on increasing or decreasing the compensation is made in the last period of the successive approximation phase to permit as much charge injec ⁇ tion as possible to be stored. This can be achieved by using the control signal for the storing of the least significant bit as a clock for the up and down counter since this signal is high during this range only.
  • the measuring ADC must be modified, such that Sj n and Sfb contact earth or some other stable voltage.
  • the comparator in the PR-ADC is not offset-compensated, it is suitable to offset-compensate at least the comparator in the measuring ADC.
  • Such compensation is standard for CMOS comparators. If the charge injection is now perfectly compensated for, the value of the integrator in the last period becomes the same as its initial and reset value. It may then be determined by thresholding of the comparator around this value whether there is too low or too high a compensation level.
  • the compensation will probably be far from correct. It will then be adjusted one step at a time until the correct compensation has been achieved. Subse ⁇ quently, the compensation will alternate around the optimum level concurrently with the adjustment. If it were not for noise in the comparator and above all in the switching in the integrator, the compensation would never be more than one step from optimum. However, the noise affects the compensation, and by this simple principle, the compensation can be incorrect by several steps. It is then important that the steps, at least close to optimum, are so small that they constitute but a fraction of the least significant bit, Isb, in a converted value.
  • the step length in the adjustment is determined by, inter alia, the coupling capaci- tance for the extra input. This should not be selected to be greater than to allow the greatest charge injection error to be adjusted with full deflection of the compensa ⁇ tion voltage. This results in a minimum step length for a given resolution in the compensation and a minimum increase of the noise in the PR-ADC.
  • the capacitance can be accomplished by the parasitic capacitance of an intersect ⁇ ing conductor over the array of ADC channels and thus occupies a minimum area.
  • the adjusting time for a compensation with 1000 different levels and a rate of con ⁇ version in the PR-ADC of 10 ksamples/s will be max. 0.1 s after application of the voltage, which in most cases is sufficient. If the manufacturing process allows non ⁇ volatile memories to be implemented, a correct compensation can be achieved much faster.
  • a dynamic solution may save some hardware in the form of switches, an optional extra resistor ladder, a demultiplexer, a digital register and an adder.
  • a solution is presented in Fig. 6. It contains a compensation integrator, to which a small positive or negative charge is applied depending on the thresholding of the comparator. The charge is applied by charging C U p or C,j 0Wn when these are connected to the respective transistors. The transistor then transmits the charge to the compensation integrator. The result ⁇ ing voltage of the compensation integrator then replaces the voltage from the demultiplexer in the former solution.
  • FIG. 7 A third example of dynamic implementation is shown in Fig. 7, where the adjust- ment is directly proportional to the charge injection. There the difference between the initial value and the final value of the integrator is quite simply sampled. The difference is applied to the compensation integrator by the switching of the capaci ⁇ tance C s . This method eliminates the alternation around an optimum compensation level owing to the compensation not being quantified. The effect of noise on the compensation, however, cannot be avoided.
  • the buffer in the Figure has two functions. On the one hand, the buffer utilises the input step of the comparator to resemble the capacitive load of the ordinary ADC channels, thereby obtaining the same charge injection. On the other hand, the amplification in the buffer implies that the offset of the compensation integrator can be neglected.
  • the algorithm for successive approxi ⁇ mation can be made tolerant towards charge injection.
  • the search range is reduced by a factor two per step since this results in the quickest search and binarily weighted bits.
  • This method comes sensitive to drift, which may arise from e.g. charge injection. If the value that is to be approximated drifts as the approximation proceeds and gets outside the previously determined range, the approximation cannot cover the drifting value. As a result, the binary code becomes incorrect.
  • the range by a factor less than two, it will also be possible to cover a drifting value by the approximation algorithm. This applies if the drift per step is less than the resulting additional covering in the upper and lower edge of the range compared with a halving of the range. Thus, the successive approximation becomes more tolerant towards drift and incorrect comparator decisions in the vicinity of the range limits.
  • the output code will, however, not be binary, but each bit corresponds to the covering of the respective ranges. Besides, the maximum resolution will be limited to the same size as the charge injection per cycle.
  • the range of each step is deter ⁇ mined by the voltage level from the resistor ladder.
  • the resistor ladder should then be constructed such that the voltage level falls more slowly than a factor two.
  • a technique of obtaining a correct weighting is internal measuring of the resistor ladder and, thus, the range. This can be carried out with an extra ADC channel intended especially for this purpose. The result of these measurements may then directly control the weighting of the associated decision in the successively approximating search.
  • Another technique is the keeping, by means of autocalibration of the resistor ladder, accurate, predetermined ranges by methods which resemble those mentioned below for calibration of the resistance ladder to exactly halving levels.
  • the inaccuracy of the resistor ladder will limit the accuracy and resolution that can be obtained in the conversion of the residual voltage in an otherwise well-designed PF - ADC.
  • the PR-ADC has a greater accuracy than the conversion of the residual voltage, which is restricted by the resistor ladder.
  • the greater accuracy is a result of the robust first phase with voltage-to-pulse-amount conversion. The totally seen greater accuracy can then be used to calibrate the resistor ladder to a higher accuracy.
  • one more parallel PR-ADC channel is suitably added to the existing PR-ADC array
  • the purpose of this channel will be to measure the feedback levels from the resistor ladder, such that these can be calibrated to be accurate halvings of each other
  • the feedback levels of the resistor ladder are then connected successively to this channel so as to be digitised with high accuracy
  • the measurement of a feedback level is done in such a manner that the input of the measuring ADC chops between the current outlet from the resistor ladder and ref 0
  • the measuring of the resistor ladder must start by measuring the own offset of the ADC so as to allow subtracting this in the measure ⁇ ments on the resistor ladder
  • the charge injection is compensated for, which results in such a low offset that an offset compensation need not be made
  • the offset compensation should be re- quired, there is a need of a digital register for storing this offset, a subtractor for subtracting it and an extra measuring cycle for measu ⁇ ng the offset with the input earthed
  • each feedback level can be measured twice, but with a different phase of the chopping The signal will then be reversed between the two measuring operations, but the offset remains constant
  • the subtraction of the digitised values then adds the signal, but the offset is subtracted
  • the calibration is not dependent on which method is selected and will therefore not be described
  • a measuring operation begins by measuring the full feedback level during the volt ⁇ age-to-pulse-amount conversion, which constitute the correct reference level, according to which the other feedback levels are to be halved Then ref/2 is measured If the digitised value of ref/2 is smaller than the halved value of the digit ⁇ ised reference level, this level should be increased and vice versa The comparison is carried out with the aid of a digital comparator In the same manner, ref/4 is measured and compared with the reference value which is halved by a further step, whereupon ref/4 is calibrated The remaining feedback levels are measured and compared correspondingly until the last level has been measured
  • each feedback level has its own register which is stepped up or down depending on the outcome of the comparator for the respective levels
  • the calibration can be implemented in various ways An alternative is shown in Fig 8, where the feedback levels are compensated for by varying ref 0 , thereby obtaining correct feedback levels
  • the new ref 0 is defined as ref 0 ( ⁇ ), where i designates the current feedback level, starting from zero for full feedback, and increases by one per halved level.
  • ref o (0) is selected to be identical with ref 0 , which is used during the voltage-to-pulse-amount conversion.
  • Each ref 0 (i), i > 0, is now calibrated such that the resulting feedback level, ref/2'-ref 0 (i), becomes correct.
  • the compensation voltage ref 0 (i) is switched out from a separate second resistor ladder supplied from an outlet of a third resistor ladder.
  • the outlet should be adjusted such that maximum deviations in the main resistor ladder can barely be compensated for.
  • use is made of an outlet of the main resistor ladder to feed the second resistor ladder in order to save complexity.
  • the major part of the complexity resides in the registers which store the current compensation value, the decoder which based on the value of the register selects a corresponding outlet, the arithmetic unit which counts the value of the register up or down and compares the stored reference value with the measured value from the ADC and the control unit, which checks the current feedback level and provides the circuit with control pulses.
  • the rate and point of time of the AD conversions in the example are determined by external requirements and take place in parallel over all channels including the one for calibration.
  • the control unit operates in a cyclic manner and will, after a number of conversions, reach the position where the reference level ref/1 is to be meas ⁇ ured, from where the following description of the function of the example illustrated begins.
  • M a , S a , s a and S s are closed, such that the input of the measuring ADC chops between ref/1 and ref o (0) and the PR-ADC can begin the voltage-to-pulse-amount conversion.
  • the chopping on the input is interrupted, which then becomes inactive.
  • the con- version of the residual voltage requires compensated ref 0 (i) levels.
  • S a is therefore opened and concurrently with the selecting of Sfc-S ⁇ , the corresponding compensa ⁇ tion register containing the current calibration level is addressed, whereupon the current ref 0 (i) are switched out from the second resistor ladder.
  • the digitised ref/1 level is put in the reference register and the control unit steps up for the next measurement.
  • the compensated ref/2 level is to be measured, and therefore M ⁇ is closed at the same time as the register containing the current compensation of ref/2 is addressed, such that the input chops between ref/2 and the selected ref 0 (1).
  • S a and s a are closed, such that the voltage-to-pulse-amount conversion can be begun.
  • the input of the ADC becomes inactive during the conversion of the residual voltage, and when S D -S n are selected, the corresponding compensation register can be addressed and the current ref 0 (i) can be switched out.
  • the digitised measured value is then compared in the arithmetic unit with the halved reference value that is stored.
  • the content of the compensation register is increased or decreased a step towards the correct level by the arithmetic unit recording the new value in the register.
  • the control unit steps up for a new measurement.
  • the control units starts all over by measuring once more ref/1. For each such calibration cycle of the feedback levels, the conversion of the residual voltage gains accuracy and thus also the ADC in its entirety. This makes the accuracy in the cali- bration increase as the process continues.
  • the limit of the total accuracy which is possible to obtain is set by the precision in the voltage-to-pulse-amount converter and is very high (> 16 bits).
  • the calibration value will alternate around the optimum value owing to the control process always stepping towards the optimum. Also in this context, it is therefore important that this step is very small in relation to the level of the least significant bit. Several measurements at each level can be carried out and averaged to suppress noise, such that the calibration of the resistor ladder is seldom more than one quantification interval from the optimum.
  • This calibration is applicable not only to increase the accuracy of the PR-ADC but can also be used to calibrate reference voltages for other ADCs.
  • An example of this is the parallel successive approximation converter (PSA-ADC) which is described in Swedish Patent 9202994-1. It is particularly suited since it uses in a similar manner a common resistor ladder for a plurality of parallel converters of the type successive approximation. These operate one clock period skewed in relation to each other and can in this manner reach conversion rates around 100 Msamples per second in 0.8 ⁇ m CMOS technology. The accuracy, however, is restricted to about 10 bits mainly depending on the precision of the resistor ladder since its levels are used to determine the most significant bits.
  • a PR-ADC is now arranged on the same chip and its resistor ladder is allowed to be common with that of the PSA-ADC, it is possible, by using the described calibra ⁇ tion technique, to obtain a high-resolution PSA-ADC having a maintained high rate of conversion. It is also possible to use only one high-resolution voltage-to-pulse- amount converter for the calibration, but this yields a considerably slower calibra ⁇ tion, in which the converter can take in the order of minutes before it reaches full precision.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

L'invention concerne un convertisseur analogique-numérique à étalonnage automatique et un dispositif de détection le comprenant. Ledit convertisseur est constitué d'un premier convertisseur analogique-numérique du type convertisseur de valeurs mesurées en un certain nombre d'impulsions, d'un second convertisseur analogique-numérique, qui convertit la valeur résiduelle du premier convertisseur à la fin de la première période en une valeur numérique au moyen de valeurs de référence, et d'un sommateur qui ajoute la valeur résiduelle au signal de sortie du premier convertisseur. Les fonctions ou les composants du second convertisseur analogique-numérique sont étalonnés automatiquement au moyen de valeurs d'étalonnage mesurées par le convertisseur analogique-numérique concerné, dont le premier et le second convertisseur analogique-numérique et un autre exemple de convertisseur analogique-numérique de configuration similaire.
PCT/SE1997/000947 1996-05-31 1997-05-30 Convertisseur analogique-numerique a etalonnage automatique et dispositif de detection le comprenant WO1997045960A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SE9602166-2 1996-05-31
SE9602166A SE516581C2 (sv) 1996-05-31 1996-05-31 Auto-kalibrerande analog-till-digitalomvandlare och sensoranordning innefattande sådan

Publications (1)

Publication Number Publication Date
WO1997045960A1 true WO1997045960A1 (fr) 1997-12-04

Family

ID=20402837

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/SE1997/000947 WO1997045960A1 (fr) 1996-05-31 1997-05-30 Convertisseur analogique-numerique a etalonnage automatique et dispositif de detection le comprenant

Country Status (2)

Country Link
SE (1) SE516581C2 (fr)
WO (1) WO1997045960A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001058010A2 (fr) * 2000-02-04 2001-08-09 Infineon Technologies Ag Dispositifs et procedes d'etalonnage d'etages d'amplification et de compensation d'erreurs dans des composants montes en amont d'etages d'amplification
US9015516B2 (en) 2011-07-18 2015-04-21 Hewlett-Packard Development Company, L.P. Storing event data and a time value in memory with an event logging module

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1989011757A1 (fr) * 1988-05-23 1989-11-30 Hughes Aircraft Company Convertisseur analogique/numerique travaillant dans une plage de frequences inferieure et avec possibilite d'etalonnage
US4973974A (en) * 1987-09-08 1990-11-27 Kabushiki Kaisha Toshiba Multi-stage analog-to-digital converting device
WO1996009692A1 (fr) * 1994-09-23 1996-03-28 National Semiconductor Corporation Architecture efficace de correction des defauts de non-concordance des composants et des non-linearites des circuits d'un convertisseur a/n
WO1996013903A1 (fr) * 1994-11-01 1996-05-09 Försvarets Forskningsanstalt Convertisseur analogique/numerique et capteur comprenant un tel convertisseur

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4973974A (en) * 1987-09-08 1990-11-27 Kabushiki Kaisha Toshiba Multi-stage analog-to-digital converting device
WO1989011757A1 (fr) * 1988-05-23 1989-11-30 Hughes Aircraft Company Convertisseur analogique/numerique travaillant dans une plage de frequences inferieure et avec possibilite d'etalonnage
WO1996009692A1 (fr) * 1994-09-23 1996-03-28 National Semiconductor Corporation Architecture efficace de correction des defauts de non-concordance des composants et des non-linearites des circuits d'un convertisseur a/n
WO1996013903A1 (fr) * 1994-11-01 1996-05-09 Försvarets Forskningsanstalt Convertisseur analogique/numerique et capteur comprenant un tel convertisseur

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001058010A2 (fr) * 2000-02-04 2001-08-09 Infineon Technologies Ag Dispositifs et procedes d'etalonnage d'etages d'amplification et de compensation d'erreurs dans des composants montes en amont d'etages d'amplification
WO2001058010A3 (fr) * 2000-02-04 2002-12-27 Infineon Technologies Ag Dispositifs et procedes d'etalonnage d'etages d'amplification et de compensation d'erreurs dans des composants montes en amont d'etages d'amplification
US7312732B2 (en) 2000-02-04 2007-12-25 Infineon Technologies Ag Devices and methods for calibrating amplifier stages and for compensating for errors in amplifier stages of series-connected components
US9015516B2 (en) 2011-07-18 2015-04-21 Hewlett-Packard Development Company, L.P. Storing event data and a time value in memory with an event logging module
US9465755B2 (en) 2011-07-18 2016-10-11 Hewlett Packard Enterprise Development Lp Security parameter zeroization
US9483422B2 (en) 2011-07-18 2016-11-01 Hewlett Packard Enterprise Development Lp Access to memory region including confidential information

Also Published As

Publication number Publication date
SE516581C2 (sv) 2002-01-29
SE9602166L (sv) 1997-12-01
SE9602166D0 (sv) 1996-05-31

Similar Documents

Publication Publication Date Title
JP5090190B2 (ja) アナログ量をデジタル化するための方法、前記方法を実装するデジタル化装置、及びそのような装置を統合する電磁放射線検出器
US5499027A (en) Digitally self-calibrating pipeline analog-to-digital converter
US7944379B2 (en) SAR ADC and method with INL compensation
US6452519B1 (en) Analog to digital converter utilizing a highly stable resistor string
US8970227B2 (en) Circuit for capacitive touch applications
US8441387B2 (en) Continuous ramp generator design and its calibration for CMOS image sensors using single-ramp ADCs
US6784824B1 (en) Analog-to-digital converter which is substantially independent of capacitor mismatch
US6590517B1 (en) Analog to digital conversion circuitry including backup conversion circuitry
US5844514A (en) Analog-to-digital converter and sensor device comprising such a converter
US6414619B1 (en) Autoranging analog to digital conversion circuitry
US10581443B2 (en) Method and apparatus for offset correction in SAR ADC with reduced capacitor array DAC
US20200195266A1 (en) Method of capacitive dac calibration for sar adc
KR20130107275A (ko) 정전용량 방식 터치 애플리케이션용 회로
US7075465B2 (en) Comparator offset calibration for A/D converters
US6310518B1 (en) Programmable gain preamplifier
US5184128A (en) Integrating A/D converter with means for reducing rollover error
US5760616A (en) Current copiers with improved accuracy
Lee et al. A self calibrating 12b 12 µ s CMOS ADC
WO1997045960A1 (fr) Convertisseur analogique-numerique a etalonnage automatique et dispositif de detection le comprenant
US7176818B2 (en) Analog to digital converter, related method and use in voltage regulator circuits
US5561426A (en) Analog-to-digital converter
US11855654B2 (en) Multichannel successive approximation analog-to-digital converter
Rodgers et al. A monolithic+ or-5 1/2-digit BiMOS A/D converter
Uster Current-mode analog-to-digital converter for array implementation
Furuta et al. A digital calibration technique for pipelined analog-to-digital converters

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): CA JP US

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH DE DK ES FI FR GB GR IE IT LU MC NL PT SE

121 Ep: the epo has been informed by wipo that ep was designated in this application
NENP Non-entry into the national phase

Ref country code: JP

Ref document number: 97542244

Format of ref document f/p: F

122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: CA