Classifications

• • G—PHYSICS
  • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
  • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
  • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
  • G03F7/70—Microphotolithographic exposure; Apparatus therefor
  • G03F7/70058—Mask illumination systems
• • G—PHYSICS
  • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
  • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
  • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
  • G03F7/20—Exposure; Apparatus therefor
  • G03F7/24—Curved surfaces
• • G—PHYSICS
  • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
  • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
  • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
  • G03F7/70—Microphotolithographic exposure; Apparatus therefor
  • G03F7/70216—Mask projection systems
  • G03F7/70241—Optical aspects of refractive lens systems, i.e. comprising only refractive elements
• • G—PHYSICS
  • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
  • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
  • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
  • G03F7/70—Microphotolithographic exposure; Apparatus therefor
  • G03F7/70216—Mask projection systems
  • G03F7/70275—Multiple projection paths, e.g. array of projection systems, microlens projection systems or tandem projection systems
• • G—PHYSICS
  • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
  • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
  • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
  • G03F7/70—Microphotolithographic exposure; Apparatus therefor
  • G03F7/70216—Mask projection systems
  • G03F7/703—Non-planar pattern areas or non-planar masks, e.g. curved masks or substrates
• • G—PHYSICS
  • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
  • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
  • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
  • G03F7/70—Microphotolithographic exposure; Apparatus therefor
  • G03F7/70216—Mask projection systems
  • G03F7/7035—Proximity or contact printers
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
  • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10S438/00—Semiconductor device manufacturing: process
  • Y10S438/942—Masking
  • Y10S438/944—Shadow

Definitions

• the present invention relates to methods and apparatus for producing integrated ' circuit devices .
• Packaging An essential step in the manufacture of all integrated circuit devices is known as "packaging" and involves mechanical and environmental protection of a silicon chip which is at the heart of the integrated circuit as well as electrical interconnection between predetermined locations on the silicon chip and exter- nal electrical terminals.
• wire bonding employs heat and ultrasonic energy to weld gold bonding wires between bond pads on the chip and contacts on the package.
• Tape automatic bonding employs a copper foil tape instead of bonding wire.
• the copper foil tape is configured for each specific die and package combi- nation and includes a pattern of copper traces suited thereto.
• the individual leads may be connected individ- ually or as a group to the various bond pads on the chip.
• Flip chips are integrated circuit dice which have solder bumps formed on top of the bonding pads, thus allowing the die to be "flipped" circuit side down and directly soldered to a substrate. Wire bonds are not required and considerable savings in package spac- ing may be realized.
• the above-described technologies each have certain limitations. Both wire bonding and TAB bonding I are prone to bad bond formation and subject the die to relatively high temperatures and mechanical pressures. Both wire bond and TAB technologies are problematic from a package size viewpoint, producing integrated circuit devices having a die-to-package area ratio ranging from about 10% to 60%.
• the flip-chip does not provide packaging but rather only interconnection. The interconnection en- counters problems of uniformity in the solder bumps as well as in thermal expansion mismatching, which limits the use of available substrates to silicon or materials which have thermal expansion characteristics similar to those of silicon.
• the present invention seeks to provide appa- ratus and techniques for production of integrated circuit device overcome many of the above limitations and provide integrated circuits of relatively smaller size and weight and enhanced electrical performance.
• PCT/EP92/02134 entitled Methods and Apparatus for Producing Integrated Circuit Devices filed September 14, 1992 there appear various types of integrated circuit devices including devices having pads which extend over both planar and edge surfaces thereof.
• the present invention seeks to provide meth- ods and apparatus for three dimensional photolithogra- phy, which are particularly suited for producing the above-described integrated circuit devices using mask techniques.
• a method for three dimensional lithography including the steps of providing a substrate having surfaces extending in three dimensions and a light sensitive coating and illuminating the substrate via a mask with light impinging on the surfaces at a non-perpendicular angle with respect thereto.
• a method for photolithographic forming of metal areas on an inte- grated circuit device including the steps of providing an integrated circuit device substrate having surfaces extending in three dimensions and a light sensitive coating and illuminating the substrate via a mask with light impinging on the surfaces at a non-perpendicular angle with respect thereto.
• apparatus for three dimensional lithography including a light source for illuminating a substrate having surfaces extending in three dimensions and a light sensitive coating via a mask with light impinging on the sur- faces at a non-perpendicular angle with respect there- to.
• apparatus for photolithographic forming of metal areas on an inte- grated circuit device including a light source for illuminating an integrated circuit device substrate having surfaces extending in three dimensions and a light sensitive coating via a mask with light imping- ing on the surfaces at a non-perpendicular angle with respect thereto.
• the mask may be located in proximity exposure relationship with the substrate.
• the mask may be spaced from the substrate and optical elements may be located between the mask and the substrate.
• a camera for viewing the substrate prior to and during illumination thereof.
• the illumination may be carried out by em- ploying a square pyramidal prism reflecting light from a light source onto a plurality of mutually spaced mirrors, which in turn reflect light onto edges of the substrate.
• the mask comprises a plurality of reticles and the optical system comprises a plural- ity of projection lenses receiving light from the plurality of reticles and a plurality of folding mir- rors receiving light from the plurality of projection lens and directing it onto edges of the substrate.
• mask exposure of the substrate is car- ried out waferwise.
• exposure can be ⁇ carried out on individual dice.
• a plurality of individual dice may be arranged in an array similar to an array of dice on a wafer and may be exposed together in the same way as a wafer. Different masks may be employed for each exposure. Alternatively the same mask may be used for multiple exposures or all exposures, provided that the mask is rotated appropriately for each exposure direc- tion.
• Fig. 1 is an illustration of an object, such as a semiconductor device having a patterned metal layer formed on surfaces thereof extending in three dimensions in accordance with a preferred embodiment of the present invention
• Fig. 2 is an illustration of angled impinge- ment of light onto surfaces of a coated metal substrate through a mask in accordance with a preferred embodi- ment of the present invention
• Fig. 3 is a simplified sectional illustration of apparatus for illuminating a substrate in accordance with one embodiment of the invention
• Fig. 4 is a plan view of the apparatus of Fig. 3 taken in the direction indicated by arrow IV in Fig. 3;
• Fig. 1 is an illustration of an object, such as a semiconductor device having a patterned metal layer formed on surfaces thereof extending in three dimensions in accordance with a preferred embodiment of the present invention
• Fig. 2 is an illustration of angled impinge- ment of light onto surfaces of a coated metal substrate through a mask in accordance with a preferred embodi- ment of the present invention
• FIG. 5 is a simplified sectional illustration of apparatus for illuminating a substrate in accordance with another embodiment of the invention
• Fig. 6 is a simplified sectional illustration of apparatus for illuminating a substrate in accordance with yet another embodiment of the invention
• Fig. 7A is a simplified illustration of a wafer bearing multiple integrated circuit dice which is produced in accordance with a preferred embodiment of the present invention
• Fig. 7B is an enlarged illustration of part of the wafer of Fig. 7A
• Fig. 8A is a simplified illustration of a mask used in producing the wafer of Figs. 7A and 7B
• Fig. 8B is an enlarged illustration of part of the mask of Fig. 8A
• Fig. 8A is a simplified illustration of a mask used in producing the wafer of Figs. 7A and 7B
• Fig. 8B is an enlarged illustration of part of the mask of Fig. 8A
• Fig. 8A is a simplified illustration of a mask used in producing the wa
• FIG. 9 is a simplified illustration of a technique for producing the wafer of Figs. 7A and 7B in accordance with a preferred embodiment of the present invention.
• Figs. 10A, 10B, IOC and 10D are illustrations of part of the wafer of Figs. 7A and 7B showing the exposed areas of the photoresist following each of the four exposures in the technique of Fig. 9.
• Fig. 1 is an example of an object 10, preferably, but not necessari- ly, an integrated circuit device, having a patterned metal coating 12 on surfaces thereof.
• the object 10 includes a pair of opposite facing planar surfaces 14 and a plurality of edge surfaces 16, joining the planar surfaces 14.
• the patterned metal coating is formed simultaneously on at least one planar surface 14 and at least one edge surface 16.
• the metal coating 12 is formed simultaneously on both planar surfaces 14 and on a plurality of edge surfaces 16, which surfaces extend in three dimensions.
• a layer 18 of a photosensitive coating, such as an elec- trodeposited photoresist is formed over a metal coating layer 20.
• the photoresist layer 18 is preferably ex- posed by light impinging at an angle which is not normal to any of surfaces 14 and 16, which passes through a mask 22.
• the light impinges on both surfaces 14 and 16 at an angle within the general range of 10 - 80 degrees with respect to the normal thereto.
• a more preferred range of angles of impinge- ment is 30 - 45 degrees. Most preferred angles of impingement are 30 and 45 degrees.
• Figs. 3 & 4 illustrate apparatus for providing the illumination illustrated in Fig. 2.
• a light source 30, such as a Xenon or Mercury lamp provides a generally collimated light beam which impinges on a metal coated square pyramidal prism 32.
• the four facets of prism 32 reflect the light from light source 30 onto four mirrors 34, which, in turn, reflect the light through apertures 36 in a support plate 38 onto a mask 40.
• Mask 40 includes patterning apertures 42 which allow light to pass therethrough in proximity exposure engagement with the various surfaces of a substrate 44, much in the manner illustrated in Fig. 3.
• "Proximity exposure" as used throughout the specifica- tion and claims is defined as contact or near contact exposure. Reference is made to Fig.
• FIG. 5 which illus- trates an alternative embodiment of the present inven- tion wherein four images are projected by an image source and optics 50 onto a pyramidal prism 52 which reflects each of the four images in a separate direc- tion simultaneously onto four respective folding mir- rors 54 which may be mounted onto a base 56.
• the four folding mirrors 54 each direct a beam of light through a corresponding aperture 58 and through focusing optics 60 onto a different edge sur- face of an object 62 and a portion of the planar sur- face adjacent thereto.
• a sensor such as a CCD sensor 64, views the object 62 through viewing optics 66 and provides a feedback indication of proper registration of each of the four images on the object.
• the sensor output may be used by an automatic inspection device or system or alternatively may provide a human visible output to an inspector.
• an illuminator 70 such as a 130 mm square UV light source commercially available from Jerry Bachur and Associates (JBA) of San Jose, California, U.S.A. provides a spatially uniform high intensity UV light output via a UV filter 72, preferably having a peak transmission at 365 microns, also commercially available from JBA.
• the filtered UV light passes through four discrete reticles 74, each disposed on a reticle stage 75 along a side of a rectangle defined on a reticle stage support 76.
• the reticles are commercially avail- able from Compugraphics of Scotland, and the reticle stage 75 is commercially available from Newport Corp. of the U.S.A.
• the patterned light from each reticle 74 passes through a f/22 projection lens 78 preferably having 1:1 magnification, commercially available from Janos Technology Inc. of Townsend, Vt. U.S.A..
• Light from each of lenses 78 is reflected by a folding mirror 80 so as to impinge on onto a different edge surface of an object 82 and a portion of the planar surface adja- cent thereto.
• Proper registration of the patterned light onto the object 82 may be monitored using one or more microscopes 84, each of which preferably examines one corner of the object.
• FIGs. 7A - 10D illustrate waferwise three dimensional lithogra- phy in accordance with a preferred embodiment of the invention.
• a wafer 100 on which integrated circuits have been formed, and which has' been notched to delineate individual integrated circuit dice is shown in Figs. 7A and 7B.
• Figs. 7A and 7B may represent an array of separated dice which are arranged in touch- ing or near touching side-by-side relationship.
• Each die is seen to have a generally rectangular top facet 102 and four inclined side facets 104, .106, 108 and 110.
• Wafer 100 is initially subjected to metal deposition by conventional techniques.
• a layer of photoresist is formed over the metal, prefera- bly by an electrophoretic technique.
• a mask 120 such as that illustrated in Figs. 8A and 8B, and having longitudinal openings 122 corre- sponding to desired pads along one edge of top facet 102 and an adjacent side facet, is exposed with light directed generally parallel to the longitudinal axis of openings 122.
• the exposure step is repeated for three sequential 90 degree rotations, either by using a different mask or by using a single mask which may have different masking patterns corresponding to each 90 degree sequential rotation.

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• Physics & Mathematics (AREA)
• General Physics & Mathematics (AREA)
• Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

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Citations (5)

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• 1993
  • 1993-09-02 IL IL106892A patent/IL106892A0/xx unknown
• 1994
  • 1994-08-30 ZA ZA946593A patent/ZA946593B/xx unknown
  • 1994-09-01 AU AU75376/94A patent/AU7537694A/en not_active Abandoned
  • 1994-09-01 WO PCT/EP1994/002908 patent/WO1995006899A1/en not_active Ceased
  • 1994-09-01 US US08/602,853 patent/US5716759A/en not_active Expired - Lifetime
  • 1994-09-01 JP JP7507954A patent/JPH09507607A/ja active Pending
  • 1994-09-02 TW TW083108069A patent/TW288183B/zh active
  • 1994-09-02 SV SV1994000042A patent/SV1994000042A/es not_active Application Discontinuation

Patent Citations (5)

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