US10729009B2 - Ceramic electronic component - Google Patents

Ceramic electronic component Download PDF

Info

Publication number
US10729009B2
US10729009B2 US16/174,623 US201816174623A US10729009B2 US 10729009 B2 US10729009 B2 US 10729009B2 US 201816174623 A US201816174623 A US 201816174623A US 10729009 B2 US10729009 B2 US 10729009B2
Authority
US
United States
Prior art keywords
layer
surface electrode
electronic component
ceramic
sintered layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active, expires
Application number
US16/174,623
Other languages
English (en)
Other versions
US20190069402A1 (en
Inventor
Yuki TAKEMORI
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Assigned to MURATA MANUFACTURING CO., LTD. reassignment MURATA MANUFACTURING CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: TAKEMORI, YUKI
Publication of US20190069402A1 publication Critical patent/US20190069402A1/en
Priority to US16/903,694 priority Critical patent/US11647581B2/en
Priority to US16/903,699 priority patent/US11641712B2/en
Application granted granted Critical
Publication of US10729009B2 publication Critical patent/US10729009B2/en
Active legal-status Critical Current
Adjusted expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0306Inorganic insulating substrates, e.g. ceramic, glass
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B32LAYERED PRODUCTS
    • B32BLAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B15/00Layered products comprising a layer of metal
    • B32B15/04Layered products comprising a layer of metal comprising metal as the main or only constituent of a layer, which is next to another layer of the same or of a different material
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B32LAYERED PRODUCTS
    • B32BLAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B3/00Layered products comprising a layer with external or internal discontinuities or unevennesses, or a layer of non-planar shape; Layered products comprising a layer having particular features of form
    • B32B3/26Layered products comprising a layer with external or internal discontinuities or unevennesses, or a layer of non-planar shape; Layered products comprising a layer having particular features of form characterised by a particular shape of the outline of the cross-section of a continuous layer; characterised by a layer with cavities or internal voids ; characterised by an apertured layer
    • B32B3/263Layered products comprising a layer with external or internal discontinuities or unevennesses, or a layer of non-planar shape; Layered products comprising a layer having particular features of form characterised by a particular shape of the outline of the cross-section of a continuous layer; characterised by a layer with cavities or internal voids ; characterised by an apertured layer characterised by a layer having non-uniform thickness
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B32LAYERED PRODUCTS
    • B32BLAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B3/00Layered products comprising a layer with external or internal discontinuities or unevennesses, or a layer of non-planar shape; Layered products comprising a layer having particular features of form
    • B32B3/26Layered products comprising a layer with external or internal discontinuities or unevennesses, or a layer of non-planar shape; Layered products comprising a layer having particular features of form characterised by a particular shape of the outline of the cross-section of a continuous layer; characterised by a layer with cavities or internal voids ; characterised by an apertured layer
    • B32B3/266Layered products comprising a layer with external or internal discontinuities or unevennesses, or a layer of non-planar shape; Layered products comprising a layer having particular features of form characterised by a particular shape of the outline of the cross-section of a continuous layer; characterised by a layer with cavities or internal voids ; characterised by an apertured layer characterised by an apertured layer, the apertures going through the whole thickness of the layer, e.g. expanded metal, perforated layer, slit layer regular cells B32B3/12
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B32LAYERED PRODUCTS
    • B32BLAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B3/00Layered products comprising a layer with external or internal discontinuities or unevennesses, or a layer of non-planar shape; Layered products comprising a layer having particular features of form
    • B32B3/26Layered products comprising a layer with external or internal discontinuities or unevennesses, or a layer of non-planar shape; Layered products comprising a layer having particular features of form characterised by a particular shape of the outline of the cross-section of a continuous layer; characterised by a layer with cavities or internal voids ; characterised by an apertured layer
    • B32B3/30Layered products comprising a layer with external or internal discontinuities or unevennesses, or a layer of non-planar shape; Layered products comprising a layer having particular features of form characterised by a particular shape of the outline of the cross-section of a continuous layer; characterised by a layer with cavities or internal voids ; characterised by an apertured layer characterised by a layer formed with recesses or projections, e.g. hollows, grooves, protuberances, ribs
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B32LAYERED PRODUCTS
    • B32BLAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B9/00Layered products comprising a layer of a particular substance not covered by groups B32B11/00 - B32B29/00
    • B32B9/005Layered products comprising a layer of a particular substance not covered by groups B32B11/00 - B32B29/00 comprising one layer of ceramic material, e.g. porcelain, ceramic tile
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B32LAYERED PRODUCTS
    • B32BLAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B9/00Layered products comprising a layer of a particular substance not covered by groups B32B11/00 - B32B29/00
    • B32B9/04Layered products comprising a layer of a particular substance not covered by groups B32B11/00 - B32B29/00 comprising such particular substance as the main or only constituent of a layer, which is next to another layer of the same or of a different material
    • B32B9/043Layered products comprising a layer of a particular substance not covered by groups B32B11/00 - B32B29/00 comprising such particular substance as the main or only constituent of a layer, which is next to another layer of the same or of a different material of natural rubber or synthetic rubber
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0271Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • H05K1/111Pads for surface mounting, e.g. lay-out
    • H05K1/112Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/113Via provided in pad; Pad over filled via
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/28Applying non-metallic protective coatings
    • H05K3/285Permanent coating compositions
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4644Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01Dielectrics
    • H05K2201/0137Materials
    • H05K2201/017Glass ceramic coating, e.g. formed on inorganic substrate
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01Dielectrics
    • H05K2201/0183Dielectric layers
    • H05K2201/0195Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03Conductive materials
    • H05K2201/0332Structure of the conductor
    • H05K2201/0335Layered conductors or foils
    • H05K2201/0347Overplating, e.g. for reinforcing conductors or bumps; Plating over filled vias
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09145Edge details
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09372Pads and lands
    • H05K2201/09436Pads or lands on permanent coating which covers the other conductors
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09372Pads and lands
    • H05K2201/09481Via in pad; Pad over filled via
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09654Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/0969Apertured conductors
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09654Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09727Varying width along a single conductor; Conductors or pads having different widths
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09654Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09736Varying thickness of a single conductor; Conductors in the same plane having different thicknesses
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09654Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09745Recess in conductor, e.g. in pad or in metallic substrate
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09818Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/099Coating over pads, e.g. solder resist partly over pads
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1131Sintering, i.e. fusing of metal particles to achieve or improve electrical conductivity
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/24Reinforcing the conductive pattern
    • H05K3/244Finish plating of conductors, especially of copper conductors, e.g. for pads or lands
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00Stock material or miscellaneous articles
    • Y10T428/12All metal or with adjacent metals
    • Y10T428/12201Width or thickness variation or marginal cuts repeating longitudinally
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00Stock material or miscellaneous articles
    • Y10T428/12All metal or with adjacent metals
    • Y10T428/12361All metal or with adjacent metals having aperture or cut
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00Stock material or miscellaneous articles
    • Y10T428/24Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24273Structurally defined web or sheet [e.g., overall dimension, etc.] including aperture
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00Stock material or miscellaneous articles
    • Y10T428/24Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24273Structurally defined web or sheet [e.g., overall dimension, etc.] including aperture
    • Y10T428/24322Composite web or sheet
    • Y10T428/24331Composite web or sheet including nonapertured component

Definitions

  • the present invention relates to a ceramic electronic component.
  • a multilayer ceramic electronic component such as a multilayer ceramic substrate is cited as a ceramic electronic component including an electronic component body and a surface electrode placed on a surface thereof.
  • a covering ceramic layer i.e., a framing layer, is placed on a peripheral section of the surface electrode (refer to Patent Document 1).
  • Patent Document 1 Japanese Unexamined Patent Application Publication No. 2012-186269
  • This covering ceramic layer is placed on a ceramic layer (hereinafter referred to as the base ceramic layer) of an electronic component body in addition to the peripheral section of the surface electrode.
  • the covering ceramic layer is formed in such a manner that a ceramic green sheet for forming the covering ceramic layer is put on a predetermined place and is fired or ceramic paste for forming the covering ceramic layer is applied to a predetermined place and is fired.
  • the covering ceramic layer is preferably formed by firing together with firing for obtaining the electronic component body and the surface electrode.
  • the present invention has been made to solve the above problems. It is an object of the present invention to provide a ceramic electronic component in which the bond strength between a covering ceramic layer and a surface electrode is high and in which the covering ceramic layer can be prevented from being peeled from the surface electrode.
  • a covering ceramic layer is obtained by firing together with firing for obtaining an electronic component body and a surface electrode
  • a ceramic component or glass component contained in a base ceramic layer transforms into a liquid phase, which is supplied to the covering ceramic layer, and as a result, the sinterability of the covering ceramic layer is increased.
  • the inventor has conceived that the difference in amount of the liquid phase supplied to the covering ceramic layer from the base ceramic layer causes the difference in sinterability of the covering ceramic layer between on the surface electrode and on the base ceramic layer.
  • the inventor has conceived that the covering ceramic layer on the surface electrode is unlikely to be supplied with the liquid phase and therefore has poorer sinterability as compared to the covering ceramic layer on the base ceramic layer and the bond strength between the covering ceramic layer and the surface electrode is low.
  • a covering ceramic layer can be prevented from being peeled from a surface electrode in such a manner that a path for supplying a liquid phase from a base ceramic layer to the covering ceramic layer on the surface electrode is formed in the surface electrode, thereby completing the present invention.
  • a ceramic electronic component includes an electronic component body including a superficial base ceramic layer, a surface electrode placed on a surface of the electronic component body, and a covering ceramic layer covering a peripheral section of the surface electrode.
  • the peripheral section of the surface electrode that is covered by the covering ceramic layer has an opening therein.
  • forming the opening in the peripheral section of the surface electrode that is covered by the covering ceramic layer allows a liquid phase to be supplied to the covering ceramic layer from the base ceramic layer through the opening.
  • the sinterability of the covering ceramic layer on the surface electrode is increased and the bond strength between the covering ceramic layer and the surface electrode is increased. Therefore, even in the case where the ceramic electronic component is subjected to a surface treatment such as blasting, the covering ceramic layer is unlikely to be peeled from the surface electrode.
  • the liquid phase is supplied to the covering ceramic layer from the base ceramic layer through the opening as described above. Therefore, even when forming a covering ceramic layer having a composition with low sinterability (for example, a covering ceramic layer in which the content of a metal oxide such as Al 2 O 3 is high), the bond strength between the covering ceramic layer and the surface electrode is high.
  • a covering ceramic layer having a composition with low sinterability for example, a covering ceramic layer in which the content of a metal oxide such as Al 2 O 3 is high
  • the bond strength between the covering ceramic layer and the surface electrode is high.
  • forming the opening in the peripheral section of the surface electrode increases the contact area between the covering ceramic layer and the surface electrode, therefore enhancing an anchoring effect, and increasing the bond strength between the covering ceramic layer and the surface electrode.
  • the opening preferably extends through the surface electrode.
  • Forming the opening in the peripheral section of the surface electrode such that the opening extends through the surface electrode facilitates the supply of the liquid phase to the covering ceramic layer on the surface electrode.
  • the opening is preferably a hole or a slit.
  • the opening which is the hole or the slit, can be readily formed by a method in which screen printing is performed using a screen mask having an opening, a working method using a laser or a mechanical puncher, or the like. Therefore, a path for supplying the liquid phase from the base ceramic layer to the covering ceramic layer on the surface electrode can be readily formed.
  • a ceramic electronic component includes an electronic component body including a superficial base ceramic layer, a surface electrode on a surface of the electronic component body, and a covering ceramic layer covering a peripheral section of the surface electrode.
  • the peripheral section of the surface electrode that is covered by the covering ceramic layer has a thin portion on the peripheral side of the surface electrode and which is thinner than a central section of the surface electrode.
  • the width of the thin portion is 50% or more of the width of the peripheral section of the surface electrode that is covered by the covering ceramic layer.
  • a ceramic electronic component includes an electronic component body including a superficial base ceramic layer, a surface electrode on a surface of the electronic component body, and a covering ceramic layer covering a peripheral section of the surface electrode.
  • the peripheral section of the surface electrode that is covered by the covering ceramic layer has a thin portion on the central side of the surface electrode and which is thinner than a central section of the surface electrode.
  • the width of the thin portion is 20% or more of the width of the peripheral section of the surface electrode that is covered by the covering ceramic layer.
  • the thin portion which is thinner than the central section of the surface electrode, allows a liquid phase to be supplied to the covering ceramic layer from the base ceramic layer through the thin portion.
  • the sinterability of the covering ceramic layer on the surface electrode is increased and the bond strength between the covering ceramic layer and the surface electrode is increased. Therefore, even in the case where the ceramic electronic component is subjected to a surface treatment such as blasting, the covering ceramic layer is unlikely to be peeled from the surface electrode.
  • the thin portion which is thinner than the central section of the surface electrode, allows a liquid phase to be supplied to the covering ceramic layer from the base ceramic layer through the thin portion as is the case with the second embodiment.
  • the liquid phase is supplied to an end portion of the covering ceramic layer that is most likely to be peeled off as compared to the second embodiment.
  • the sinterability of the covering ceramic layer on the surface electrode is increased and the bond strength between the covering ceramic layer and the surface electrode is increased. Therefore, even in the case where the ceramic electronic component is subjected to a surface treatment such as blasting, the covering ceramic layer is unlikely to be peeled from the surface electrode.
  • the liquid phase is likely to be supplied to the covering ceramic layer from the base ceramic layer through the thin portion as described above. Therefore, even in the case of forming a covering ceramic layer having a composition with low sinterability (for example, a covering ceramic layer in which the content of a metal oxide such as Al 2 O 3 is high), the bond strength between the covering ceramic layer and the surface electrode is high.
  • a covering ceramic layer having a composition with low sinterability for example, a covering ceramic layer in which the content of a metal oxide such as Al 2 O 3 is high
  • the bond strength between the covering ceramic layer and the surface electrode is high.
  • the width of the thin portion is preferably 15 ⁇ m or more and the thickness of the thin portion is preferably 10 ⁇ m or less.
  • Adjusting each of the width and thickness of the thin portion to the above range facilitates the supply of the liquid phase to the covering ceramic layer on the surface electrode.
  • the ceramic electronic component according to the first embodiment of the present invention, the ceramic electronic component according to the second embodiment of the present invention, and the ceramic electronic component according to the third embodiment of the present invention also have common shared features.
  • the surface electrode preferably includes a first sintered layer placed on the upper surface of the base ceramic layer, a second sintered layer placed on the upper surface of the first sintered layer, and a plating layer placed on the upper surface of the second sintered layer.
  • the surface electrode to have a multilayer structure composed of the first sintered layer, which is used to increase the bond strength to the base ceramic layer, and the second sintered layer, which is used to form the plating layer. Therefore, the bond strength between the surface electrode and the base ceramic layer can be increased.
  • the first sintered layer preferably contains a metal oxide containing at least one metal element selected from Al, Zr, Ti, Si, and Mg.
  • the metal oxide can be coupled with a ceramic component or glass component contained in the base ceramic layer. Therefore, the bond strength between the first sintered layer and the base ceramic layer can be increased.
  • the second sintered layer preferably contains a smaller amount of the metal oxide as compared to the first sintered layer.
  • the upper surface of the second sintered layer can be kept in such a condition that a plating is likely to adhere.
  • a ceramic electronic component in which the bond strength between a covering ceramic layer and a surface electrode is high and the covering ceramic layer can be prevented from being peeled from the surface electrode can be provided.
  • FIG. 1 is a schematic sectional view of an example of a ceramic electronic component according to a first embodiment of the present invention.
  • FIGS. 2A to 2C are schematic sectional views showing an example of a method for manufacturing the ceramic electronic component 1 shown in FIG. 1 .
  • FIG. 3 is a schematic sectional view of an example of a ceramic electronic component according to a second embodiment of the present invention.
  • FIG. 4 is a schematic sectional view of another example of the ceramic electronic component according to the second embodiment of the present invention.
  • FIG. 5 is a schematic sectional view of another example of the ceramic electronic component according to the second embodiment of the present invention.
  • FIGS. 6A to 6C are schematic sectional views showing an example of a method for manufacturing the ceramic electronic component 2 shown in FIG. 3 .
  • FIG. 7 is a schematic sectional view of an example of a ceramic electronic component according to a third embodiment of the present invention.
  • FIG. 8 is a schematic plan view showing the shape of openings formed in a peripheral section of a surface electrode in a ceramic electronic component 1 - 1 .
  • FIG. 9 is a schematic plan view showing the shape of openings formed in a peripheral section of a surface electrode in a ceramic electronic component 1 - 2 .
  • Embodiments below are illustrative and the partial replacement or combination of configurations described in different embodiments can be made.
  • items common to those described in a first embodiment are not described in detail but only items different from those described therein are described.
  • similar effects due to similar configurations are not mentioned one by one in each embodiment.
  • a ceramic electronic component includes a multilayer ceramic substrate having a plurality of laminated ceramic layers.
  • the present invention is not limited to such a multilayer ceramic electronic component and is applicable to various ceramic electronic components in which an electronic component body includes a superficial base ceramic layer and in which a surface electrode is placed on a surface of the electronic component body.
  • FIG. 1 is a schematic sectional view of an example of a ceramic electronic component according to the first embodiment of the present invention.
  • the ceramic electronic component 1 of which the overall configuration is not shown in FIG. 1 , includes an electronic component body 10 including a superficial base ceramic layer 11 , a surface electrode 20 placed on a surface of the electronic component body 10 , and a covering ceramic layer 30 covering a peripheral section of the surface electrode 20 .
  • the peripheral section of the surface electrode 20 that is covered by the covering ceramic layer 30 has openings 40 .
  • the openings 40 are preferably filled with a ceramic component or glass component, which is not shown in FIG. 1 , contained in the base ceramic layer 11 .
  • the electronic component body 10 has a multilayer structure composed of a plurality of laminated base ceramic layers 11 and an inner conductive film 12 and via-hole conductor 13 serving as inner wiring conductors are placed in the electronic component body 10 .
  • the inner conductive film 12 is electrically connected to the via-hole conductor 13 .
  • the via-hole conductor 13 is electrically connected to the surface electrode 20 .
  • the surface electrode 20 has a three-layer structure and includes a first sintered layer 21 placed on the upper surface of the base ceramic layer 11 located at a surface of the electronic component body 10 , a second sintered layer 22 placed on the upper surface of the first sintered layer 21 , and a plating layer 23 placed on the upper surface of the second sintered layer 22 .
  • a section of a surface electrode that is covered by a covering ceramic layer is referred to as a peripheral section of the surface electrode and a section of the surface electrode that is not covered by the covering ceramic layer is referred to as a central section of the surface electrode.
  • the peripheral section of the surface electrode that is covered by the covering ceramic layer is hereinafter simply referred to as the peripheral section of the surface electrode.
  • a section covered by the covering ceramic layer is referred to as a peripheral section of each layer and a section not covered by the covering ceramic layer is referred to as a central section of the layer.
  • the peripheral section of the surface electrode 20 is covered by the covering ceramic layer 30 , which is placed on the base ceramic layer 11 and the second sintered layer 22 , and has the openings 40 .
  • the openings 40 extend through the first sintered layer 21 and the second sintered layer 22 .
  • a central section of the surface electrode 20 is provided with the plating layer 23 .
  • the plating layer 23 is not covered by the covering ceramic layer 30 .
  • the base ceramic layer which is included in the electronic component body, preferably contains a low-temperature co-fired ceramic material.
  • the low-temperature co-fired ceramic material refers to, among ceramic materials, a material which can be sintered at a firing temperature of 1,000° C. or less and which can be co-fired with Ag or Cu.
  • Examples of the low-temperature co-fired ceramic material which is contained in the base ceramic layer, include glass composite low-temperature co-fired ceramic materials formed by mixing borosilicate glass with ceramic materials such as quartz, alumina, and forsterite; crystal glass low-temperature co-fired ceramic materials containing ZnO—MgO—Al 2 O 3 —SiO 2 crystal glass; and non-glass low-temperature co-fired ceramic materials formed using BaO—Al 2 O 3 —SiO 2 ceramic materials or Al 2 O 3 —CaO—SiO 2 —MgO—B 2 O 3 ceramic materials.
  • Inner wiring conductors (the inner conductive film and the via-hole conductor), which are placed in the electronic component body, contain a conductive component.
  • the conductive component which is contained in the inner wiring conductors, include Au, Ag, Cu, Pt, Ta, W, Ni, Fe, Cr, Mo, Ti, Pd, Ru, and alloys mainly containing one of these metals.
  • the inner wiring conductors preferably contain Au, Ag, or Cu and more preferably Ag or Cu as a conductive component. Au, Ag, and Cu have low resistance and are therefore particularly suitable for the case where the ceramic electronic component is for use in high-frequency applications.
  • the covering ceramic layer which covers the peripheral section of the surface electrode, is placed on the base ceramic layer located at the surface of the electronic component body and the surface electrode.
  • the covering ceramic layer preferably contains a low-temperature co-fired ceramic material.
  • the low-temperature co-fired ceramic material contained in the covering ceramic layer may be the same as or different from the low-temperature co-fired ceramic material contained in the base ceramic layer and is preferably the same as the low-temperature co-fired ceramic material contained in the base ceramic layer.
  • the covering ceramic layer may contain the same metal oxide as a metal oxide which is contained in the first sintered layer of the surface electrode as described below and preferably contains substantially no metal oxide.
  • the content of the metal oxide in the covering ceramic layer is preferably less than 50% by weight.
  • the thickness of the covering ceramic layer is not particularly limited and is preferably 0.5 ⁇ m to 40 ⁇ m.
  • the surface electrode which is placed on the surface of the electronic component body, is one connected to another electronic component such as a wiring board or a mounted component.
  • the surface electrode is connected to the other electronic component by soldering or the like.
  • Examples of a conductive component contained in the surface electrode include Au, Ag, Cu, Pt, Ta, W, Ni, Fe, Cr, Mo, Ti, Pd, Ru, and alloys mainly containing one of these metals.
  • the surface electrode preferably contains the same conductive component as that contained in the inner wiring conductors.
  • the surface electrode preferably contains Au, Ag, or Cu and more preferably Ag or Cu as a conductive component.
  • the width (the length represented by W 1 in FIG. 1 ) of the peripheral section of the surface electrode is not particularly limited and is preferably 15 ⁇ m to 1 mm.
  • the width of the peripheral section of the surface electrode refers to the distance from the periphery of the surface electrode to the inner edge of the covering ceramic layer.
  • the peripheral section of the surface electrode that is covered by the covering ceramic layer characteristically has the openings.
  • the openings are preferably filled with the ceramic component or glass component contained in the base ceramic layer.
  • the peripheral section of the surface electrode may be provided with a single opening and is preferably provided with a plurality of openings.
  • the openings which are placed in the peripheral section of the surface electrode, may extend through the surface electrode and may be open to a principal surface of the surface electrode without extending through the surface electrode.
  • the openings preferably extend through the surface electrode.
  • the distance from a principal surface of the surface electrode that has no openings to each opening is preferably 10 ⁇ m or less.
  • all of the openings preferably extend through the surface electrode and openings extending through the surface electrode and openings not extending through the surface electrode may be present in a mixed state.
  • a location where the openings are placed is not particularly limited and is preferably the peripheral section of the surface electrode.
  • the openings are preferably uniformly placed in the peripheral section of the surface electrode.
  • the openings which are placed in the peripheral section of the surface electrode, are preferably holes or slits.
  • the planar shape of the holes is preferably substantially circular or regularly polygonal and is more preferably substantially circular or square.
  • the planar shape of the slits is preferably substantially oval or rectangular.
  • peripheral section of the surface electrode When the peripheral section of the surface electrode is provided with a hole or a slit, one or more holes only may be placed, one or more slits only may be placed, or holes and slits may be present in a mixed state.
  • the holes When the peripheral section of the surface electrode is provided with a plurality of holes, the holes may have different shapes and preferably have the same shape. This applied to slits.
  • the surface electrode may have a single-layer structure or a multilayer structure and preferably has the multilayer structure.
  • the surface electrode When the surface electrode has the single-layer structure, the surface electrode is preferably composed of a sintered layer only.
  • the multilayer structure is preferably an at least two-layer structure including a sintered layer placed on the upper surface of the base ceramic layer located at the surface of the electronic component body and a plating layer placed on the upper surface of the sintered layer and is more preferably an at least three-layer structure including a first sintered layer placed on the upper surface of the base ceramic layer located at the surface of the electronic component body, a second sintered layer placed on the upper surface of the first sintered layer, and a plating layer placed on the upper surface of the second sintered layer.
  • the sintered layers are those formed by baking conductive paste and the plating layers are those formed by electroplating or electroless plating after the sintered layers are formed.
  • the surface electrode preferably includes a plating layer located outermost and the surface electrode preferably includes a sintered layer only without including any plating layer.
  • the plating layer is usually formed after the sintered layers and the covering ceramic layer are formed. Therefore, the plating layer is not covered by the covering ceramic layer.
  • the first sintered layer, second sintered layer, and plating layer of the surface electrode are described below.
  • the first sintered layer, which is included in the surface electrode, contains a conductive component.
  • the first sintered layer preferably further contains a metal oxide.
  • the conductive component contained in the first sintered layer examples include Au, Ag, Cu, Pt, Ta, W, Ni, Fe, Cr, Mo, Ti, Pd, Ru, and alloys mainly containing one of these metals.
  • the first sintered layer preferably contains the same conductive component as that contained in the inner wiring conductors.
  • the first sintered layer preferably contains Au, Ag, or Cu and more preferably Ag or Cu as a conductive component.
  • the metal oxide contained in the first sintered layer is, for example, a metal oxide containing at least one metal element selected from the group consisting of Al, Zr, Ti, Si, and Mg.
  • the metal oxide may be used alone or in combination with one or more metal oxides.
  • a metal oxide containing at least one metal element selected from the group consisting of Al, Zr, and Ti is preferable and a metal oxide containing Al element is more preferable.
  • the content of the metal oxide in the first sintered layer is not particularly limited and is preferably higher than the content of the content of the metal oxide in the second sintered layer.
  • the content of the metal oxide in the first sintered layer is preferably 1% by weight or more and more preferably 3% by weight or more.
  • the content of the metal oxide in the first sintered layer is preferably less than 10% by weight and more preferably less than 5% by weight.
  • the first sintered layer contains the metal oxide
  • particles of metal contained in the conductive component and particles of the metal oxide may be present in a dispersed state and surroundings of the metal particles may be covered by the metal oxide.
  • the surroundings of the metal particles are preferably covered by the metal oxide.
  • the planar shape of the first sintered layer is not particularly limited and is, for example, rectangular, tetragonal, polygonal rather than tetragonal, circular, or oval.
  • the second sintered layer which is included in the surface electrode, contains a conductive component.
  • the conductive component contained in the second sintered layer is preferably the same as the conductive component contained in the first sintered layer.
  • the second sintered layer may contain the same metal oxide as the metal oxide contained in the first sintered layer.
  • the second sintered layer preferably contains a smaller amount of the metal oxide as compared to the first sintered layer and more preferably contains substantially no metal oxide.
  • the content of the metal oxide in the second sintered layer is preferably less than 1% by weight when the content of the metal oxide in the first sintered layer is 1% by weight to less than 10% by weight.
  • the content of the metal oxide in the second sintered layer is preferably less than 3% by weight and more preferably less than 1% by weight.
  • the area of the upper surface of the second sintered layer is preferably substantially the same as the area of the upper surface of the first sintered layer. That is, the planar shape of the second sintered layer is preferably substantially the same as the planar shape of the first sintered layer.
  • the number of sintered layers is not limited to two and another sintered layer may be placed between the first sintered layer, which is placed on the upper surface of the base ceramic layer, and the second sintered layer, of which the upper surface is overlaid with the plating layer.
  • the plating layer, which is included in the surface electrode is preferably made of Au, Ag, Ni, Pd, Cu, Sn, or an alloy containing these metals.
  • the plating layer, which is included in the surface electrode may be a plating layer composed of a plurality of sublayers such as a nickel plating sublayer and gold plating sublayer that are the first sublayer and the second sublayer, respectively, from the second sintered layer side; a nickel plating sublayer and tin plating sublayer that are the first sublayer and the second sublayer, respectively, from the second sintered layer side; and a nickel plating sublayer, palladium plating sublayer, and gold plating sublayer that are the first sublayer, the second sublayer, and the third sublayer, respectively, from the second sintered layer side.
  • a section provided with the covering ceramic layer is provided with no plating layer. Therefore, the area of the upper surface of the plating layer is preferably less than the area of the upper surface of the second sintered layer.
  • the thickness of the plating layer is not particularly limited and is preferably 1 ⁇ m to 10 ⁇ m.
  • FIGS. 2A to 2C are schematic sectional views showing an example of a method for manufacturing the ceramic electronic component 1 shown in FIG. 1 .
  • an unsintered multilayer body 100 is prepared as shown in FIG. 2A .
  • the base ceramic green sheets 111 are those converted into the base ceramic layers 11 after firing.
  • the base ceramic green sheets are those obtained by forming, for example, slurry containing a powder of a ceramic raw material such as a low-temperature co-fired ceramic material, an organic binder, and a solvent into sheets by a doctor blade process or the like.
  • the slurry may contain various additives such as a dispersant and a plasticizer.
  • the organic binder contained in the slurry may be, for example, a butyral resin (polyvinyl butyral), an acrylic resin, a methacrylic resin, or the like.
  • the solvent may be, for example, toluene, an alcohol such as isopropyl alcohol, or the like.
  • the plasticizer may be, for example, di-n-butyl phthalate or the like.
  • a through-hole for forming the via-hole conductor 13 is formed in a specific one of the base ceramic green sheets 111 .
  • the through-hole is filled with a conductive paste containing, for example, Ag or Cu as a conductive component, whereby a conductive paste body 113 to be converted into the via-hole conductor 13 is formed.
  • a conductive paste film 112 to be converted into the inner conductive film 12 is formedC on a specific one of the base ceramic green sheets 111 by, for example, a process such as screen printing using a conductive paste having the same composition as that of the above conductive paste.
  • a conductive paste film 121 to be converted into the first sintered layer 21 is formed on the base ceramic green sheet 111 placed superficially after stacking.
  • a conductive paste film 122 to be converted into the second sintered layer 22 is formed on the conductive paste film 121 .
  • the conductive paste film 121 to be converted into the first sintered layer 21 can be formed by a process such as screen printing using, for example, a conductive paste containing a conductive component such as Ag or Cu and a metal oxide such as Al 2 O 3 .
  • the conductive paste film 122 to be converted into the second sintered layer 22 can be formed by a process such as screen printing using, for example, a conductive paste containing a conductive component such as Ag or Cu.
  • the conductive paste film 121 and the conductive paste film 122 are formed so as to have openings such that openings 140 are formed so as to extend through the conductive paste film 121 to be converted into the first sintered layer 21 and the conductive paste film 122 to be converted into the second sintered layer 22 .
  • the openings are formed therein.
  • the conductive paste film 121 to be converted into the first sintered layer 21 and the conductive paste film 122 to be converted into the second sintered layer 22 may be formed before firing.
  • the metal oxide contained in the conductive paste include Al 2 O 3 , ZrO 2 , TiO 2 , SiO 2 , and MgO. Among these oxides, Al 2 O 3 is preferably used.
  • Examples of a method for forming the conductive paste films having the openings include a method in which screen printing is performed using a screen mask having openings and a method in which after a conductive paste film is formed on a transfer film such as a PET film and openings are formed in the conductive paste film on the transfer film using a mechanical puncher, the conductive paste film is transferred to a base ceramic green sheet.
  • An example of a method for forming the openings after the formation of the conductive paste films is a method in which after a conductive paste film is formed on a base ceramic green sheet, openings are formed in the conductive paste film only using a laser or the like.
  • a covering ceramic green sheet 130 is separately prepared.
  • the covering ceramic green sheet 130 is one converted into the covering ceramic layer 30 after firing.
  • the covering ceramic green sheet is one obtained by forming, for example, slurry containing a powder of a ceramic raw material such as a low-temperature co-fired ceramic material, an organic binder, and a solvent into a sheet by a doctor blade process or the like.
  • the slurry may contain various additives such as a dispersant and a plasticizer.
  • the slurry for preparing the covering ceramic green sheet may be the slurry for preparing the base ceramic green sheets.
  • the unsintered multilayer body 100 is prepared by stacking and then pressure-bonding the base ceramic green sheet 111 provided with the conductive paste body 113 to be converted into the via-hole conductor 13 or the conductive paste film 112 to be converted into the inner conductive film 12 , the base ceramic green sheets 111 provided with the conductive paste film 121 to be converted into the first sintered layer 21 and the conductive paste film 122 to be converted into the second sintered layer 22 , and the covering ceramic green sheet 130 .
  • the covering ceramic green sheet 130 is provided on the base ceramic green sheet 111 placed superficially after stacking and the conductive paste film 122 to be converted into the second sintered layer 22 so as to cover a region provided with the openings 140 .
  • the unsintered multilayer body 100 can be prepared in such a manner that, instead of the covering ceramic green sheet 130 , a paste-like composition is applied to the base ceramic green sheet 111 located at a surface of the unsintered multilayer body 100 and the conductive paste film 122 to be converted into the second sintered layer 22 .
  • the paste-like composition may be applied to the unstacked base ceramic green sheet 111 and the conductive paste film 122 to be converted into the second sintered layer 22 .
  • the unsintered multilayer body 100 is fired.
  • This allows the following body to be obtained as shown in FIG. 2B : a multilayer body including the electronic component body 10 , which includes the base ceramic layer 11 placed superficially; the first sintered layer 21 , which is placed on the upper surface of the base ceramic layer 11 ; the second sintered layer 22 , which is placed on the upper surface of the first sintered layer 21 ; and the covering ceramic layer 30 , which is placed on the base ceramic layer 11 and the second sintered layer 22 . Peripheral sections of the first and second sintered layers 21 and 22 that are covered by the covering ceramic layer 30 are provided with the openings 40 .
  • the ceramic component or the glass component, which is contained in the base ceramic layer 11 transforms into a liquid phase, which is not shown in FIG. 2B , during firing.
  • the liquid phase is supplied to the covering ceramic layer 30 (the covering ceramic green sheet 130 ) from the base ceramic layer 11 (the base ceramic green sheets 111 ) through the openings 40 . Therefore, the openings 40 are preferably filled with the ceramic component or the glass component, which is contained in the base ceramic layer 11 .
  • the first sintered layer and the second sintered layer can be formed in such a manner that the conductive paste films are formed on a surface of the sintered electronic component body and are fired.
  • the covering ceramic layer can be formed in such a manner that the covering ceramic green sheet is provided on the peripheral sections of the first and second sintered layers after sintering and is fired.
  • the first sintered layer, the second sintered layer, and the covering ceramic layer are preferably formed in such a manner that the conductive paste films and the covering ceramic green sheet are fired together with firing for obtaining the electronic component body as described above.
  • Forming the first sintered layer, the second sintered layer, and the covering ceramic layer by co-firing is advantageous in streamlining manufacturing steps and in reducing manufacturing costs and enables the bond strength between the electronic component body and the first sintered layer and the bond strength between the electronic component body and the covering ceramic layer to be increased.
  • the base ceramic layer which is included in the electronic component body, preferably contains the low-temperature co-fired ceramic material as described above.
  • a constraint green sheet mainly containing a metal oxide (Al 2 O 3 or the like) not substantially sintered at the sintering temperature of the unsintered multilayer body 100 is prepared.
  • the unsintered multilayer body 100 may be fired in such a state that the constraint green sheet is placed on a surface of the unsintered multilayer body 100 .
  • the constraint green sheet is not substantially sintered during firing, therefore does not shrink, and acts to suppress the shrinkage of the multilayer body in the principal surface direction.
  • the plating layer 23 is formed on the upper surface of the second sintered layer 22 by electroplating or electroless plating as shown in FIG. 2C .
  • the plating layer 23 it is preferable that a Ni plating film is formed on the second sintered layer 22 and an Au or Sn plating film is formed thereon.
  • forming the openings in the peripheral section of the surface electrode that is covered by the covering ceramic layer probably allows the liquid phase to be supplied to the covering ceramic layer from the base ceramic layer through the openings.
  • the sinterability of the covering ceramic layer on the surface electrode is increased and the bond strength between the covering ceramic layer and the surface electrode is increased. Therefore, even in the case where the ceramic electronic component is subjected to a surface treatment such as blasting, the covering ceramic layer is unlikely to be peeled from the surface electrode.
  • forming the openings in the peripheral section of the surface electrode increases the contact area between the covering ceramic layer and the surface electrode, therefore enhances an anchoring effect, and increases the bond strength between the covering ceramic layer and the surface electrode.
  • FIG. 3 is a schematic sectional view of an example of a ceramic electronic component according to a second embodiment of the present invention.
  • the ceramic electronic component 2 includes an electronic component body 10 including a superficial base ceramic layer 11 , a surface electrode 20 placed on a surface of the electronic component body 10 , and a covering ceramic layer 30 covering a peripheral section of the surface electrode 20 .
  • the peripheral section of the surface electrode 20 that is covered by the covering ceramic layer 30 has a thin portion 50 which is present on the peripheral side of the surface electrode 20 and which is thinner than a central section of the surface electrode 20 .
  • the electronic component body 10 has a multilayer structure composed of a plurality of laminated base ceramic layers 11 and an inner conductive film 12 and via-hole conductor 13 serving as inner wiring conductors are placed in the electronic component body 10 .
  • the inner conductive film 12 is electrically connected to the via-hole conductor 13 .
  • the via-hole conductor 13 is electrically connected to the surface electrode 20 .
  • the surface electrode 20 has a three-layer structure and includes a first sintered layer 21 placed on the upper surface of the base ceramic layer 11 located at a surface of the electronic component body 10 , a second sintered layer 22 placed on the upper surface of the first sintered layer 21 , and a plating layer 23 placed on the upper surface of the second sintered layer 22 .
  • a section of a surface electrode that is covered by a covering ceramic layer is referred to as a peripheral section of the surface electrode and a section of the surface electrode that is not covered by the covering ceramic layer is referred to as a central section of the surface electrode.
  • the peripheral section of the surface electrode 20 is covered by the covering ceramic layer 30 , which is placed on the base ceramic layer 11 and the second sintered layer 22 .
  • the whole of the peripheral section of the surface electrode 20 corresponds to the thin portion 50 , which is thinner than the central section of the surface electrode 20 .
  • the central section of the surface electrode 20 is provided with the plating layer 23 .
  • the plating layer 23 is not covered by the covering ceramic layer 30 .
  • FIG. 4 is a schematic sectional view of another example of the ceramic electronic component according to the second embodiment of the present invention.
  • a portion of a peripheral section of a surface electrode 20 is a thin portion 50 thinner than a central section of the surface electrode 20 .
  • a material for the base ceramic layers, which are included in the electronic component body; a conductive component in inner wiring conductors placed in the electronic component body; and the like are the same as those described in the first embodiment.
  • the covering ceramic layer which covers the peripheral section of the surface electrode, is placed on the base ceramic layer located at the surface of the electronic component body and the surface electrode.
  • a material contained in the covering ceramic layer, the thickness of the covering ceramic layer, and the like are the same as those described in the first embodiment.
  • the surface electrode which is placed on a surface of the electronic component body, is one connected to another electronic component such as a wiring board or a mounted component.
  • the surface electrode is connected to the other electronic component by soldering or the like.
  • a conductive component contained in the surface electrode is the same as that described in the first embodiment.
  • the peripheral section of the surface electrode that is covered by the covering ceramic layer has the thin portion, which is present on the peripheral side of the surface electrode and is thinner than the central section of the surface electrode.
  • a thin portion having a predetermined width is present from the peripheral side to central side of the surface electrode, with the periphery of the surface electrode being an end portion on the peripheral side.
  • the width (the length represented by W 1 in FIGS. 3 and 4 ) of the peripheral section of the surface electrode is not particularly limited and is preferably 15 ⁇ m to 1 mm.
  • the width of the peripheral section of the surface electrode refers to the distance from the periphery of the surface electrode to the inner edge of the covering ceramic layer.
  • the width (the length represented by W 2 in FIGS. 3 and 4 ) of the thin portion is preferably 10 ⁇ m or more, more preferably 15 ⁇ m or more, and further more preferably 20 ⁇ m or more.
  • the width of the thin portion refers to the distance from the periphery of the surface electrode to a portion having the same thickness as the thickness of the central section.
  • the width of the peripheral section of the surface electrode and the width of the thin portion can be both measured by cross-sectional observation using a scanning electron microscope (SEM).
  • the width of the thin portion is preferably 50% or more of the width of the peripheral section of the surface electrode that is covered by the covering ceramic layer. That is, it is characteristic that the ratio (W 2 /W 1 ) of the width W 2 of the thin portion to the width W 1 of the peripheral section of the surface electrode is 50% or more as shown in FIGS. 3 and 4 .
  • the width W 2 of the thin portion is the same as the width W 1 of the peripheral section of the surface electrode and therefore the width of the thin portion is 100% of the width of the peripheral section of the surface electrode.
  • the width of the thin portion is preferably 70% or more of the width of the peripheral section of the surface electrode that is covered by the covering ceramic layer, more preferably 90% or more, and particularly preferably 100%.
  • the case where the ratio of the width of the thin portion is 100% corresponds to a third embodiment of the present invention.
  • the width of the thin portion may exceed 100% of the width of the peripheral section of the surface electrode that is covered by the covering ceramic layer.
  • the central section of the surface electrode that is not covered by the covering ceramic layer has the thin portion.
  • the central section of the surface electrode that is not covered by the covering ceramic layer may have the thin portion as described above. Only the peripheral section of the surface electrode preferably has the thin portion.
  • the thin portion preferably has a thickness of 10 ⁇ m or less and more preferably 5 ⁇ m or less.
  • the thickness of the thin portion can be measured by cross-sectional observation using a scanning electron microscope (SEM).
  • the thickness of the thin portion is preferably constant over the whole thin portion as shown in FIGS. 3 and 4 .
  • the thickness of the thin portion may decrease stepwise from the central section of the surface electrode toward the peripheral section thereof or may decrease continuously.
  • the thin portion is preferably present over the whole of a region including the periphery of the surface electrode so as to surround the periphery of the surface electrode and a portion having the same thickness as the thickness of the central section may be present in a portion of the region including the periphery of the surface electrode.
  • the peripheral section of the surface electrode may have a plurality of thin portions.
  • the surface electrode may have a single-layer structure or a multilayer structure and preferably has the multilayer structure.
  • the surface electrode When the surface electrode has the single-layer structure, the surface electrode is preferably composed of a sintered layer only.
  • the multilayer structure is preferably an at least two-layer structure including a sintered layer placed on the upper surface of the base ceramic layer located at the surface of the electronic component body and a plating layer placed on the upper surface of the sintered layer and is more preferably an at least three-layer structure including a first sintered layer placed on the upper surface of the base ceramic layer located at the surface of the electronic component body, a second sintered layer placed on the upper surface of the first sintered layer, and a plating layer placed on the upper surface of the second sintered layer.
  • FIG. 5 is a schematic sectional view of another example of the ceramic electronic component according to the second embodiment of the present invention.
  • a peripheral section of a first sintered layer 21 has an exposed surface on which no second sintered layer 22 or plating layer 23 is placed.
  • the exposed surface is covered by a covering ceramic layer 30 placed on a base ceramic layer 11 located at a surface of an electronic component body 10 and the first sintered layer 21 .
  • the peripheral section of the first sintered layer 21 that is covered by the covering ceramic layer 30 is a thin portion 50 thinner than a central section of a surface electrode 20 .
  • the number of layers included in the thin portion may be different from the number of layers included in the surface electrode.
  • the ceramic electronic component 2 shown in FIG. 3 is preferably manufactured as described below.
  • FIGS. 6A to 6C are schematic sectional views showing an example of a method for manufacturing the ceramic electronic component 2 shown in FIG. 3 .
  • the manufacturing method shown in FIGS. 6A to 6C is the same as the manufacturing method shown in FIGS. 2A to 2C except a method for forming the surface electrode 20 and therefore common items are not described in detail.
  • an unsintered multilayer body 200 is prepared as shown in FIG. 6A .
  • a plurality of base ceramic green sheets 111 are prepared and, thereafter, a conductive paste body 113 to be converted into the via-hole conductor 13 or a conductive paste film 112 to be converted into the inner conductive film 12 is formed on a specific one of the base ceramic green sheets 111 as is the case with the first embodiment.
  • a covering ceramic green sheet 130 is separately prepared.
  • a conductive paste film 121 to be converted into the first sintered layer 21 is formed on the base ceramic green sheet 111 placed superficially after stacking and a conductive paste film 122 to be converted into the second sintered layer 22 is formed on the conductive paste film 121 .
  • the conductive paste film 121 and the conductive paste film 122 are formed by varying the amount of an applied conductive paste such that a thin portion 150 in which a peripheral section is thinner than a central section is formed.
  • the unsintered multilayer body 200 is prepared by stacking and then pressure-bonding the base ceramic green sheet 111 provided with the conductive paste body 113 to be converted into the via-hole conductor 13 or the conductive paste film 112 to be converted into the inner conductive film 12 , the base ceramic green sheet 111 provided with the conductive paste film 121 to be converted into the first sintered layer 21 and the conductive paste film 122 to be converted into the second sintered layer 22 , and the covering ceramic green sheet 130 .
  • the covering ceramic green sheet 130 is provided on the base ceramic green sheet 111 placed superficially after stacking and the conductive paste film 122 to be converted into the second sintered layer 22 so as to cover peripheral sections of the conductive paste films 121 and 122 that have a reduced thickness.
  • the unsintered multilayer body 200 is fired.
  • the plating layer 23 is formed on the upper surface of the second sintered layer 22 by electroplating or electroless plating as shown in FIG. 6C .
  • the above allows the ceramic electronic component 2 , in which the surface electrode 20 including the first sintered layer 21 , the second sintered layer 22 , and the plating layer 23 is placed on a surface of the electronic component body 10 and the covering ceramic layer 30 covers the peripheral section of the surface electrode 20 , to be obtained.
  • the covering ceramic layer in the peripheral section of the surface electrode that is covered by the covering ceramic layer, forming the thin portion, which is thinner than the central section of the surface electrode, on the peripheral side of the surface electrode and adjusting the width of the thin portion to 50% or more of the width of the peripheral section of the surface electrode probably allows a liquid phase to be supplied to the covering ceramic layer from the base ceramic layer through the thin portion.
  • the sinterability of the covering ceramic layer on the surface electrode is increased and the bond strength between the covering ceramic layer and the surface electrode is increased. Therefore, even in the case where the ceramic electronic component is subjected to a surface treatment such as blasting, the covering ceramic layer is unlikely to be peeled from the surface electrode.
  • FIG. 7 is a schematic sectional view of an example of a ceramic electronic component according to the third embodiment of the present invention.
  • the ceramic electronic component 5 of which the overall configuration is not shown in FIG. 7 , includes an electronic component body 10 including a superficial base ceramic layer 11 , a surface electrode 20 placed on a surface of the electronic component body 10 , and a covering ceramic layer 30 covering a peripheral section of the surface electrode 20 .
  • the peripheral section of the surface electrode 20 that is covered by the covering ceramic layer 30 has a thin portion 50 which is present on the central side of the surface electrode 20 and which is thinner than a central section of the surface electrode 20 .
  • the peripheral section of the surface electrode that is covered by the covering ceramic layer has the thin portion, which is present on the central side of the surface electrode and is thinner than the central section of the surface electrode.
  • a thin portion having a predetermined width is present from the central side to peripheral side of the surface electrode.
  • an end of the thin portion that is located on the central side of the surface electrode preferably coincides with the position of the inner edge of the covering ceramic layer.
  • the thickness of a portion other than the thin portion is preferably the same as the thickness of the central section of the surface electrode.
  • the width (the length represented by W 1 in FIG. 7 ) of the peripheral section of the surface electrode is not particularly limited and is preferably 15 ⁇ m to 1 mm.
  • the width (the length represented by W 3 in FIG. 7 ) of the thin portion is preferably 10 ⁇ m or more, more preferably 15 ⁇ m or more, and further more preferably 20 ⁇ m or more.
  • the width of the thin portion refers to the distance from an end portion (preferably the inner edge of the covering ceramic layer) on the center side of the surface electrode to a portion which is located on the peripheral side of the surface electrode and which has the same thickness as the thickness of the central section.
  • the width of the thin portion is 20% or more of the width of the peripheral section of the surface electrode that is covered by the covering ceramic layer. That is, it is characteristic that the ratio (W 3 /W 1 ) of the width W 3 of the thin portion to the width W 1 of the peripheral section of the surface electrode is 20% or more as shown in FIG. 7 .
  • the width of the thin portion is preferably 50% or more of the width of the peripheral section of the surface electrode that is covered by the covering ceramic layer, more preferably 70% or more, further more preferably 90% or more, and particularly preferably 100%.
  • the case where the ratio of the width of the thin portion is 100% corresponds to the second embodiment of the present invention.
  • the central section of the surface electrode that is not covered by the covering ceramic layer may have the thin portion. Only the peripheral section of the surface electrode preferably has the thin portion.
  • the thickness of the thin portion is preferably 10 ⁇ m or less and more preferably 5 ⁇ m or less.
  • a position where the thin portion is present and the width of the thin portion are different from those described in the second embodiment.
  • Other constituents of the ceramic electronic component are the same as those described in the second embodiment.
  • the covering ceramic layer in the peripheral section of the surface electrode that is covered by the covering ceramic layer, forming the thin portion, which is thinner than the central section of the surface electrode, on the central side of the surface electrode and adjusting the width of the thin portion to 20% or more of the width of the peripheral section of the surface electrode probably allows a liquid phase to be supplied to the covering ceramic layer from the base ceramic layer through the thin portion as is the case with the second embodiment.
  • the liquid phase is probably likely to be supplied to an end portion of the covering ceramic layer that is most likely to be peeled off as compared to the second embodiment.
  • the sinterability of the covering ceramic layer on the surface electrode is increased and the bond strength between the covering ceramic layer and the surface electrode is increased. Therefore, even in the case where the ceramic electronic component is subjected to a surface treatment such as blasting, the covering ceramic layer is unlikely to be peeled from the surface electrode.
  • ceramic electronic components 1 - 1 to 1 - 4 each including a surface electrode placed on a surface of a base ceramic layer and a covering ceramic layer covering a peripheral section of the surface electrode, the peripheral section of the surface electrode that was covered by the covering ceramic layer having openings.
  • FIG. 8 is a schematic plan view showing the shape of openings formed in the peripheral section of the surface electrode in the ceramic electronic component 1 - 1 .
  • the surface electrode 20 was formed on the base ceramic layer 11 by screen printing using a screen mask having gaps, placed at intervals of 0.05 mm, having a width of 0.05 mm such that a plurality of slits 41 with a size of 2 mm square were provided in the peripheral section, which was located 0.1 mm inside the periphery.
  • FIG. 9 is a schematic plan view showing the shape of openings formed in the peripheral section of the surface electrode in the ceramic electronic component 1 - 2 .
  • the surface electrode 20 was formed on the base ceramic layer 11 by screen printing using a screen mask having 0.02 mm square holes placed at intervals of 0.02 mm such that a plurality of holes 42 with a size of 2 mm square were provided in the peripheral section, which was located 0.1 mm inside the periphery.
  • the ceramic electronic component 1 - 3 after an electrode with a size of 2 mm square was formed, a laser was applied to the electrode so as to penetrate the electrode only, whereby the surface electrode was formed on the base ceramic layer so as to have holes, having a diameter of 0.015 mm, placed at intervals of 0.015 mm in the peripheral section 0.1 mm inside the periphery.
  • the surface electrode was formed on the base ceramic layer in such a manner that after an electrode with a size of 2 mm square was formed on a PET film and holes with a diameter of 0.01 mm were formed at intervals of 0.01 mm in a peripheral section located 0.1 mm inside the periphery of the electrode, using a puncher, the electrode provided with the holes was transferred to a base ceramic green sheet such that a plurality of holes were provided in the peripheral section.
  • a ceramic electronic component 1 - 5 including a surface electrode including a peripheral section having no opening was prepared separately from the ceramic electronic components 1 - 1 to 1 - 4 .
  • the ceramic electronic components 1 - 1 to 1 - 5 were blasted for the purpose of removing surface stains. After blasting, ten pieces of each ceramic electronic component were cross-sectionally polished and whether delamination occurred at the interface between a covering ceramic layer and a surface electrode was checked, whereby the bond strength between the covering ceramic layer and the surface electrode was evaluated.
  • the ceramic electronic component 1 - 5 which is asterisked, is outside the scope of the present invention.
  • the ceramic electronic component 1 - 5 in which the peripheral section of the surface electrode has no openings, delamination occurred at the interface between the covering ceramic layer and the surface electrode, whereas in the ceramic electronic components 1 - 1 to 1 - 4 , in which the peripheral section of the surface electrode has openings (slits or holes), no delamination occurred at the interface between the covering ceramic layer and the surface electrode and the bond strength between the covering ceramic layer and the surface electrode is high.
  • the openings after firing were filled with a liquid phase supplied from the base ceramic layer.
  • openings in a peripheral section of a surface electrode allows a liquid phase to be supplied from a base ceramic layer to a covering ceramic layer through the openings, thereby increasing the bond strength between the covering ceramic layer and the surface electrode.
  • ceramic electronic components 2 - 1 to 2 - 4 each including a surface electrode placed on a surface of a base ceramic layer and a covering ceramic layer covering a peripheral section of the surface electrode, the peripheral section of the surface electrode that was covered by the covering ceramic layer having a thin portion.
  • the width of the thin portion was fixed to 100% of the width of the surface electrode and the thickness of the thin portion was varied over values shown in Table 2.
  • the ceramic electronic components 2 - 1 to 2 - 4 were evaluated for the bond strength between the covering ceramic layer and the surface electrode by substantially the same method as the above. The results are shown in Table 2.
  • the ceramic electronic components 2 - 1 to 2 - 4 in which the peripheral section of the surface electrode has the thin portion, delamination can be prevented from occurring at the interface between the covering ceramic layer and the surface electrode.
  • the thickness of the thin portion is 10 ⁇ m or less, no delamination occurred at the interface between the covering ceramic layer and the surface electrode and the bond strength between the covering ceramic layer and the surface electrode is high.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
  • Ceramic Capacitors (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
US16/174,623 2016-05-16 2018-10-30 Ceramic electronic component Active 2037-05-11 US10729009B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US16/903,694 US11647581B2 (en) 2016-05-16 2020-06-17 Ceramic electronic component
US16/903,699 US11641712B2 (en) 2016-05-16 2020-06-17 Ceramic electronic component

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2016-098041 2016-05-16
JP2016098041 2016-05-16
PCT/JP2017/016377 WO2017199712A1 (ja) 2016-05-16 2017-04-25 セラミック電子部品

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2017/016377 Continuation WO2017199712A1 (ja) 2016-05-16 2017-04-25 セラミック電子部品

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US16/903,694 Division US11647581B2 (en) 2016-05-16 2020-06-17 Ceramic electronic component
US16/903,699 Division US11641712B2 (en) 2016-05-16 2020-06-17 Ceramic electronic component

Publications (2)

Publication Number Publication Date
US20190069402A1 US20190069402A1 (en) 2019-02-28
US10729009B2 true US10729009B2 (en) 2020-07-28

Family

ID=60326354

Family Applications (3)

Application Number Title Priority Date Filing Date
US16/174,623 Active 2037-05-11 US10729009B2 (en) 2016-05-16 2018-10-30 Ceramic electronic component
US16/903,694 Active 2038-01-27 US11647581B2 (en) 2016-05-16 2020-06-17 Ceramic electronic component
US16/903,699 Active 2038-01-24 US11641712B2 (en) 2016-05-16 2020-06-17 Ceramic electronic component

Family Applications After (2)

Application Number Title Priority Date Filing Date
US16/903,694 Active 2038-01-27 US11647581B2 (en) 2016-05-16 2020-06-17 Ceramic electronic component
US16/903,699 Active 2038-01-24 US11641712B2 (en) 2016-05-16 2020-06-17 Ceramic electronic component

Country Status (4)

Country Link
US (3) US10729009B2 (zh)
JP (1) JP6696567B2 (zh)
CN (1) CN109156080B (zh)
WO (1) WO2017199712A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN219181776U (zh) * 2020-06-17 2023-06-13 株式会社村田制作所 电子部件
CN112277493A (zh) * 2020-10-28 2021-01-29 中科传感技术(青岛)研究院 一种多层压电陶瓷片底面电极转印方法

Citations (57)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3465435A (en) * 1967-05-08 1969-09-09 Ibm Method of forming an interconnecting multilayer circuitry
US4067104A (en) * 1977-02-24 1978-01-10 Rockwell International Corporation Method of fabricating an array of flexible metallic interconnects for coupling microelectronics components
US5175609A (en) * 1991-04-10 1992-12-29 International Business Machines Corporation Structure and method for corrosion and stress-resistant interconnecting metallurgy
US5203078A (en) * 1985-07-17 1993-04-20 Ibiden Co., Ltd. Printed wiring board for IC cards
US5227812A (en) * 1990-02-26 1993-07-13 Canon Kabushiki Kaisha Liquid jet recording head with bump connector wiring
US5436411A (en) * 1993-12-20 1995-07-25 Lsi Logic Corporation Fabrication of substrates for multi-chip modules
US5869887A (en) * 1994-10-04 1999-02-09 Nec Corporation Semiconductor package fabricated by using automated bonding tape
US20010026888A1 (en) * 2000-03-29 2001-10-04 Rohm Co., Ltd. Battery pack and method of manufacturing the same
US20030096493A1 (en) * 2001-11-19 2003-05-22 Mark Vandermeulen Perimeter anchored thick film pad
US20050000728A1 (en) * 2003-07-03 2005-01-06 Shinko Electric Industries Co., Ltd. Wiring board provided with a resistor and process for manufacturing the same
US20050205293A1 (en) * 2004-03-22 2005-09-22 Mitsubishi Denki Kabushiki Kaisha Substrate
JP2006173222A (ja) * 2004-12-14 2006-06-29 Ngk Spark Plug Co Ltd 配線基板
US20060169484A1 (en) * 2004-12-17 2006-08-03 Ibiden Co., Ltd. Printed wiring board
US20060220246A1 (en) * 2004-12-07 2006-10-05 Kil-Soo Kim Bump land structure of circuit substrate for semiconductor package
US20060255102A1 (en) * 2005-05-11 2006-11-16 Snyder Rick B Technique for defining a wettable solder joint area for an electronic assembly substrate
US20070080449A1 (en) * 2005-10-07 2007-04-12 Nec Electronics Corporation Interconnect substrate and electronic circuit device
US20070093058A1 (en) * 2005-10-24 2007-04-26 Tomonari Ohtsuki Method for producing electric contact and electrical connector
US20070108619A1 (en) * 2005-11-15 2007-05-17 Hsu Jun C Bonding pad with high bonding strength to solder ball and bump
WO2007063692A1 (ja) 2005-11-30 2007-06-07 Murata Manufacturing Co., Ltd. セラミック基板、電子装置およびセラミック基板の製造方法
US20070161223A1 (en) * 2005-12-23 2007-07-12 Phoenix Precision Technology Corporation Conductive structures for electrically conductive pads of circuit board and fabrication method thereof
JP2008109062A (ja) 2006-09-29 2008-05-08 Mitsuboshi Belting Ltd メタライズされたセラミックス基板及びその製造方法
US20080157389A1 (en) * 2007-01-02 2008-07-03 Chang-Yong Park Semiconductor package and module printed circuit board for mounting the same
US20080157359A1 (en) * 2006-12-27 2008-07-03 Sharp Kabushiki Kaisha Crack-resistant solder joint, electronic component such as circuit substrate having the solder joint, semiconductor device, and manufacturing method of electronic component
US20080176035A1 (en) * 2007-01-24 2008-07-24 Phoenix Precision Technology Corporation Circuit board structure and fabrication method of the same
US20100208437A1 (en) * 2009-02-16 2010-08-19 Maeda Shinnosuke Multilayer wiring substrate and method for manufacturing the same
DE102010005465A1 (de) * 2009-01-26 2010-08-26 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Elektrisches oder elektronisches Bauelement und Verfahren zum Herstellen eines Anschlusses
US20110048782A1 (en) * 2009-08-26 2011-03-03 Jun-Chung Hsu Solder Pad Structure With High Bondability To Solder Ball
US20110079926A1 (en) * 2009-10-01 2011-04-07 Samsung Electro-Mechanics Co., Ltd. Method of manufacturing substrate for flip chip and substrate for flip chip manufactured using the same
WO2011047544A1 (zh) * 2009-10-19 2011-04-28 巨擘科技股份有限公司 柔性多层基板的金属层结构及其制造方法
US20110108313A1 (en) * 2009-11-06 2011-05-12 Via Technologies, Inc. Circuit substrate and fabricating process thereof
US20110108315A1 (en) * 2009-11-06 2011-05-12 Via Technologies, Inc. Process for fabricating circuit substrate, and circuit substrate
JP2011176188A (ja) * 2010-02-25 2011-09-08 Kyocera Corp ガラスセラミック配線基板
US20120055702A1 (en) * 2009-06-02 2012-03-08 Hsio Technologies, Llc Compliant printed flexible circuit
WO2012121141A1 (ja) 2011-03-07 2012-09-13 株式会社村田製作所 セラミック多層基板およびその製造方法
JP2012186269A (ja) 2011-03-04 2012-09-27 Murata Mfg Co Ltd セラミック多層基板
US20120276401A1 (en) * 2010-02-19 2012-11-01 Asahi Glass Company, Limited Substrate for mounting element and its production process
US20130003332A1 (en) * 2011-06-28 2013-01-03 Samsung Electro-Mechanics Co., Ltd. Electroless surface treatment plated layers of printed circuit board and method for preparing the same
US20140000946A1 (en) * 2012-06-29 2014-01-02 Kyocera Slc Technologies Corporation Wiring board and electronic device using the same
US20140332258A1 (en) * 2012-08-29 2014-11-13 Sumitomo Electric Printed Circuits, Inc. Double-sided printed wiring board and method for producing the same
US20140363927A1 (en) * 2013-06-07 2014-12-11 Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co., Ltd. Novel Terminations and Couplings Between Chips and Substrates
US20150000966A1 (en) * 2011-12-08 2015-01-01 Lg Innotek Co., Ltd. Printed circuit board and method of manufacturing the same
US20150264809A1 (en) * 2014-03-11 2015-09-17 Kabushiki Kaisha Toshiba Wiring substrate and semiconductor device using the same
US20150357277A1 (en) * 2013-03-26 2015-12-10 Ngk Spark Plug Co., Ltd. Wiring substrate
US20160005683A1 (en) * 2014-07-02 2016-01-07 Samsung Electronics Co., Ltd. Printed circuit board for semiconductor package
US20160014892A1 (en) * 2013-03-27 2016-01-14 Murata Manufacturing Co., Ltd. Insulating ceramic paste, ceramic electronic componet, and method for producing the same
US20160088737A1 (en) * 2014-09-24 2016-03-24 Fujitsu Limited Electronic device and method of manufacturing electronic device
US20160316558A1 (en) * 2015-04-24 2016-10-27 Ibiden Co., Ltd. Printed wiring board and method for manufacturing the same
US20160351525A1 (en) * 2010-02-18 2016-12-01 Amkor Technology, Inc. Shielded electronic component package
JP2016207961A (ja) * 2015-04-28 2016-12-08 富士通株式会社 プリント基板及びシールド板金固定方法
US20170013710A1 (en) * 2015-07-09 2017-01-12 Subtron Technology Co., Ltd. Circuit board and manufacturing method thereof
US20170118846A1 (en) * 2015-10-21 2017-04-27 Samsung Electronics Co., Ltd. Manufacturing method of test socket and test method for semiconductor package
US20170170282A1 (en) * 2015-12-15 2017-06-15 Infineon Technologies Austria Ag Semiconductor wafer and method
US20170280560A1 (en) * 2016-03-22 2017-09-28 Samsung Electronics Co., Ltd. Printed circuit board and semiconductor package including the same
US20170325330A1 (en) * 2016-05-06 2017-11-09 Subtron Technology Co., Ltd. Manufacturing method of circuit substrate
US20180019220A1 (en) * 2016-07-15 2018-01-18 Samsung Display Co., Ltd. Display device and manufacturing method thereof
US20180042110A1 (en) * 2016-08-04 2018-02-08 X-Celeprint Limited Printable 3d electronic structure
US20190350088A1 (en) * 2016-12-23 2019-11-14 Atotech Deutschland Gmbh Method of forming a solderable solder deposit on a contact pad

Family Cites Families (63)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5828846A (ja) * 1981-08-14 1983-02-19 Nec Corp ボンデイング端子電極
JPS63261790A (ja) * 1987-04-20 1988-10-28 株式会社日立製作所 混成集積回路基板
JPH0680880B2 (ja) * 1988-03-15 1994-10-12 松下電工株式会社 抵抗体付セラミック回路板の製法
JPH05136565A (ja) * 1991-11-15 1993-06-01 Du Pont Japan Ltd 厚膜多層セラミツクス基板
US5163605A (en) 1992-04-30 1992-11-17 Allied-Signal Inc. Method for mounting components to a circuit board
JPH06112628A (ja) * 1992-09-24 1994-04-22 Tdk Corp 配線パターンを有する回路基板の製造方法
DE4318241C2 (de) * 1993-06-02 1995-06-29 Schulz Harder Juergen Metallbeschichtetes Substrat mit verbesserter Widerstandsfähigkeit gegen Temperaturwechselbeanspruchung
JPH0794633A (ja) 1993-09-24 1995-04-07 Ngk Spark Plug Co Ltd 金属部材を接合したセラミック基板
US5523920A (en) 1994-01-03 1996-06-04 Motorola, Inc. Printed circuit board comprising elevated bond pads
KR100216839B1 (ko) 1996-04-01 1999-09-01 김규현 Bga 반도체 패키지의 솔더 볼 랜드 메탈 구조
JP3512977B2 (ja) * 1996-08-27 2004-03-31 同和鉱業株式会社 高信頼性半導体用基板
DE19927046B4 (de) * 1999-06-14 2007-01-25 Electrovac Ag Keramik-Metall-Substrat als Mehrfachsubstrat
JP4649027B2 (ja) * 1999-09-28 2011-03-09 株式会社東芝 セラミックス回路基板
JP3740374B2 (ja) * 2001-02-26 2006-02-01 京セラ株式会社 多数個取り配線基板
US6649506B2 (en) * 2001-07-27 2003-11-18 Phoenix Precision Technology Corporation Method of fabricating vias in solder pads of a ball grid array (BGA) substrate
US6780494B2 (en) * 2002-03-07 2004-08-24 Tdk Corporation Ceramic electronic device and method of production of same
JP3863067B2 (ja) 2002-06-04 2006-12-27 Dowaホールディングス株式会社 金属−セラミックス接合体の製造方法
US20040124006A1 (en) 2002-12-31 2004-07-01 Pearson Tom E. Built up lands
US7005325B2 (en) * 2004-02-05 2006-02-28 St Assembly Test Services Ltd. Semiconductor package with passive device integration
US20050252681A1 (en) 2004-05-12 2005-11-17 Runyon Ronnie J Microelectronic assembly having variable thickness solder joint
JP2005347354A (ja) * 2004-05-31 2005-12-15 Sanyo Electric Co Ltd 回路装置およびその製造方法
JP5022576B2 (ja) * 2005-07-08 2012-09-12 株式会社ジャパンディスプレイイースト 表示パネルおよび表示装置
WO2007026455A1 (ja) * 2005-08-29 2007-03-08 Murata Manufacturing Co., Ltd. セラミック電子部品及びその製造方法
CN100586256C (zh) * 2005-11-30 2010-01-27 株式会社村田制作所 陶瓷基板、电子器件及陶瓷基板的制造方法
JP4759384B2 (ja) * 2005-12-20 2011-08-31 昭和電工株式会社 半導体モジュール
CN101132169A (zh) * 2007-09-19 2008-02-27 杨绍华 一种smd晶体谐振器用陶瓷封装件及其生产工艺
KR100914440B1 (ko) 2007-09-28 2009-08-28 삼성전기주식회사 단차가 형성된 전도층을 갖는 인쇄회로기판
JP5056325B2 (ja) * 2007-10-04 2012-10-24 富士電機株式会社 半導体装置の製造方法および半田ペースト塗布用のメタルマスク
JP2009129490A (ja) 2007-11-21 2009-06-11 Nitto Denko Corp 配線回路基板
TW201011936A (en) 2008-09-05 2010-03-16 Advanced Optoelectronic Tech Light emitting device and fabrication thereof
US8592691B2 (en) 2009-02-27 2013-11-26 Ibiden Co., Ltd. Printed wiring board
US20100236822A1 (en) * 2009-03-23 2010-09-23 Ibiden Co., Ltd. Wiring board and method for manufacturing the same
CN101965096A (zh) * 2009-07-24 2011-02-02 鸿富锦精密工业(深圳)有限公司 软性电路板
KR101051551B1 (ko) * 2009-10-30 2011-07-22 삼성전기주식회사 요철 패턴을 갖는 비아 패드를 포함하는 인쇄회로기판 및 그 제조방법
US8499200B2 (en) * 2010-05-24 2013-07-30 Ncr Corporation Managing code-tracing data
JP5498864B2 (ja) 2010-06-07 2014-05-21 新光電気工業株式会社 配線基板及び配線基板の製造方法
JP2012033855A (ja) 2010-07-01 2012-02-16 Hitachi Cable Ltd Ledモジュール、ledパッケージ、並びに配線基板およびその製造方法
JP5737388B2 (ja) * 2011-03-28 2015-06-17 株式会社村田製作所 ガラスセラミック基板およびその製造方法
JP2013026361A (ja) 2011-07-20 2013-02-04 Panasonic Corp 半導体装置及び半導体装置の製造方法
JP6078948B2 (ja) 2012-01-20 2017-02-15 日亜化学工業株式会社 発光装置用パッケージ成形体及びそれを用いた発光装置
JP6230777B2 (ja) 2012-01-30 2017-11-15 新光電気工業株式会社 配線基板、配線基板の製造方法、及び発光装置
JP6028793B2 (ja) * 2012-03-15 2016-11-16 富士電機株式会社 半導体装置
JP6119108B2 (ja) * 2012-04-10 2017-04-26 セイコーエプソン株式会社 電子デバイス、電子機器、ベース基板の製造方法および電子デバイスの製造方法
US8934257B1 (en) 2012-05-30 2015-01-13 Juniper Networks, Inc. Apparatus and methods for coplanar printed circuit board interconnect
WO2014027486A1 (ja) * 2012-08-13 2014-02-20 株式会社村田製作所 電子部品およびその製造方法
JP6183166B2 (ja) 2013-01-30 2017-08-23 三菱マテリアル株式会社 ヒートシンク付パワーモジュール用基板及びその製造方法
DE102013104739B4 (de) * 2013-03-14 2022-10-27 Rogers Germany Gmbh Metall-Keramik-Substrate sowie Verfahren zum Herstellen eines Metall-Keramik-Substrates
CN103237412B (zh) * 2013-03-27 2016-03-23 苏州远创达科技有限公司 一种电子件安装结构及制作方法、电子件产品
CN105247972A (zh) * 2013-04-26 2016-01-13 株式会社电装 多层基板、使用多层基板的电子装置、多层基板的制造方法、基板以及使用基板的电子装置
JP6140834B2 (ja) * 2013-10-23 2017-05-31 京セラ株式会社 配線基板および電子装置
JP6516399B2 (ja) * 2013-10-25 2019-05-22 セイコーインスツル株式会社 電子デバイス
JP6206266B2 (ja) 2014-03-14 2017-10-04 東芝ライテック株式会社 車両用発光モジュール、車両用照明装置、および車両用灯具
JP6424334B2 (ja) * 2014-12-01 2018-11-21 パナソニックIpマネジメント株式会社 スクリーン印刷装置及び部品実装ライン
DE112015005654T5 (de) * 2014-12-18 2017-08-31 Mitsubishi Electric Corporation Isolierte Leiterplatte, Leistungsmodul und Leistungseinheit
US9871013B2 (en) * 2014-12-29 2018-01-16 Taiwan Semiconductor Manufacturing Company, Ltd. Contact area design for solder bonding
JP2016152262A (ja) 2015-02-16 2016-08-22 イビデン株式会社 プリント配線板
KR102043406B1 (ko) * 2015-04-22 2019-12-02 가부시키가이샤 무라타 세이사쿠쇼 전자 장치 및 전자 장치의 제조 방법
KR102468796B1 (ko) 2015-08-28 2022-11-18 삼성전자주식회사 인쇄 회로 기판 및 이를 포함하는 반도체 패키지
CN208159009U (zh) 2015-11-10 2018-11-27 株式会社村田制作所 树脂多层基板
JP2017162913A (ja) 2016-03-08 2017-09-14 イビデン株式会社 配線板及びその製造方法
JP6721829B2 (ja) 2016-07-26 2020-07-15 富士通株式会社 配線基板及び電子機器
JP2018074147A (ja) * 2016-10-24 2018-05-10 京セラ株式会社 回路基板および電子装置
KR102356748B1 (ko) * 2017-10-30 2022-01-27 니뽄 도쿠슈 도교 가부시키가이샤 전극 매설 부재

Patent Citations (59)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3465435A (en) * 1967-05-08 1969-09-09 Ibm Method of forming an interconnecting multilayer circuitry
US4067104A (en) * 1977-02-24 1978-01-10 Rockwell International Corporation Method of fabricating an array of flexible metallic interconnects for coupling microelectronics components
US5203078A (en) * 1985-07-17 1993-04-20 Ibiden Co., Ltd. Printed wiring board for IC cards
US5227812A (en) * 1990-02-26 1993-07-13 Canon Kabushiki Kaisha Liquid jet recording head with bump connector wiring
US5175609A (en) * 1991-04-10 1992-12-29 International Business Machines Corporation Structure and method for corrosion and stress-resistant interconnecting metallurgy
US5436411A (en) * 1993-12-20 1995-07-25 Lsi Logic Corporation Fabrication of substrates for multi-chip modules
US5869887A (en) * 1994-10-04 1999-02-09 Nec Corporation Semiconductor package fabricated by using automated bonding tape
US20010026888A1 (en) * 2000-03-29 2001-10-04 Rohm Co., Ltd. Battery pack and method of manufacturing the same
US20030096493A1 (en) * 2001-11-19 2003-05-22 Mark Vandermeulen Perimeter anchored thick film pad
US20050000728A1 (en) * 2003-07-03 2005-01-06 Shinko Electric Industries Co., Ltd. Wiring board provided with a resistor and process for manufacturing the same
US20050205293A1 (en) * 2004-03-22 2005-09-22 Mitsubishi Denki Kabushiki Kaisha Substrate
US20060220246A1 (en) * 2004-12-07 2006-10-05 Kil-Soo Kim Bump land structure of circuit substrate for semiconductor package
JP2006173222A (ja) * 2004-12-14 2006-06-29 Ngk Spark Plug Co Ltd 配線基板
US20060169484A1 (en) * 2004-12-17 2006-08-03 Ibiden Co., Ltd. Printed wiring board
US20060255102A1 (en) * 2005-05-11 2006-11-16 Snyder Rick B Technique for defining a wettable solder joint area for an electronic assembly substrate
US20070080449A1 (en) * 2005-10-07 2007-04-12 Nec Electronics Corporation Interconnect substrate and electronic circuit device
US20070093058A1 (en) * 2005-10-24 2007-04-26 Tomonari Ohtsuki Method for producing electric contact and electrical connector
US20070108619A1 (en) * 2005-11-15 2007-05-17 Hsu Jun C Bonding pad with high bonding strength to solder ball and bump
WO2007063692A1 (ja) 2005-11-30 2007-06-07 Murata Manufacturing Co., Ltd. セラミック基板、電子装置およびセラミック基板の製造方法
US20070224400A1 (en) * 2005-11-30 2007-09-27 Murata Manufacturing Co., Ltd. Ceramic substrate, electronic apparatus, and method for producing ceramic substrate
US20070161223A1 (en) * 2005-12-23 2007-07-12 Phoenix Precision Technology Corporation Conductive structures for electrically conductive pads of circuit board and fabrication method thereof
JP2008109062A (ja) 2006-09-29 2008-05-08 Mitsuboshi Belting Ltd メタライズされたセラミックス基板及びその製造方法
US20080157359A1 (en) * 2006-12-27 2008-07-03 Sharp Kabushiki Kaisha Crack-resistant solder joint, electronic component such as circuit substrate having the solder joint, semiconductor device, and manufacturing method of electronic component
US20080157389A1 (en) * 2007-01-02 2008-07-03 Chang-Yong Park Semiconductor package and module printed circuit board for mounting the same
US20080176035A1 (en) * 2007-01-24 2008-07-24 Phoenix Precision Technology Corporation Circuit board structure and fabrication method of the same
DE102010005465A1 (de) * 2009-01-26 2010-08-26 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Elektrisches oder elektronisches Bauelement und Verfahren zum Herstellen eines Anschlusses
US20100208437A1 (en) * 2009-02-16 2010-08-19 Maeda Shinnosuke Multilayer wiring substrate and method for manufacturing the same
US20120055702A1 (en) * 2009-06-02 2012-03-08 Hsio Technologies, Llc Compliant printed flexible circuit
US20110048782A1 (en) * 2009-08-26 2011-03-03 Jun-Chung Hsu Solder Pad Structure With High Bondability To Solder Ball
US20110079926A1 (en) * 2009-10-01 2011-04-07 Samsung Electro-Mechanics Co., Ltd. Method of manufacturing substrate for flip chip and substrate for flip chip manufactured using the same
WO2011047544A1 (zh) * 2009-10-19 2011-04-28 巨擘科技股份有限公司 柔性多层基板的金属层结构及其制造方法
US20110108313A1 (en) * 2009-11-06 2011-05-12 Via Technologies, Inc. Circuit substrate and fabricating process thereof
US20110108315A1 (en) * 2009-11-06 2011-05-12 Via Technologies, Inc. Process for fabricating circuit substrate, and circuit substrate
US20160351525A1 (en) * 2010-02-18 2016-12-01 Amkor Technology, Inc. Shielded electronic component package
US20120276401A1 (en) * 2010-02-19 2012-11-01 Asahi Glass Company, Limited Substrate for mounting element and its production process
JP2011176188A (ja) * 2010-02-25 2011-09-08 Kyocera Corp ガラスセラミック配線基板
JP2012186269A (ja) 2011-03-04 2012-09-27 Murata Mfg Co Ltd セラミック多層基板
WO2012121141A1 (ja) 2011-03-07 2012-09-13 株式会社村田製作所 セラミック多層基板およびその製造方法
US20130330509A1 (en) 2011-03-07 2013-12-12 Murata Manufacturing Co., Ltd. Ceramic multilayer substrate and manufacturing method therefor
US20130003332A1 (en) * 2011-06-28 2013-01-03 Samsung Electro-Mechanics Co., Ltd. Electroless surface treatment plated layers of printed circuit board and method for preparing the same
US20150000966A1 (en) * 2011-12-08 2015-01-01 Lg Innotek Co., Ltd. Printed circuit board and method of manufacturing the same
US20140000946A1 (en) * 2012-06-29 2014-01-02 Kyocera Slc Technologies Corporation Wiring board and electronic device using the same
US20140332258A1 (en) * 2012-08-29 2014-11-13 Sumitomo Electric Printed Circuits, Inc. Double-sided printed wiring board and method for producing the same
US20150357277A1 (en) * 2013-03-26 2015-12-10 Ngk Spark Plug Co., Ltd. Wiring substrate
US20160014892A1 (en) * 2013-03-27 2016-01-14 Murata Manufacturing Co., Ltd. Insulating ceramic paste, ceramic electronic componet, and method for producing the same
US20140363927A1 (en) * 2013-06-07 2014-12-11 Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co., Ltd. Novel Terminations and Couplings Between Chips and Substrates
US20150264809A1 (en) * 2014-03-11 2015-09-17 Kabushiki Kaisha Toshiba Wiring substrate and semiconductor device using the same
US20160005683A1 (en) * 2014-07-02 2016-01-07 Samsung Electronics Co., Ltd. Printed circuit board for semiconductor package
US20160088737A1 (en) * 2014-09-24 2016-03-24 Fujitsu Limited Electronic device and method of manufacturing electronic device
US20160316558A1 (en) * 2015-04-24 2016-10-27 Ibiden Co., Ltd. Printed wiring board and method for manufacturing the same
JP2016207961A (ja) * 2015-04-28 2016-12-08 富士通株式会社 プリント基板及びシールド板金固定方法
US20170013710A1 (en) * 2015-07-09 2017-01-12 Subtron Technology Co., Ltd. Circuit board and manufacturing method thereof
US20170118846A1 (en) * 2015-10-21 2017-04-27 Samsung Electronics Co., Ltd. Manufacturing method of test socket and test method for semiconductor package
US20170170282A1 (en) * 2015-12-15 2017-06-15 Infineon Technologies Austria Ag Semiconductor wafer and method
US20170280560A1 (en) * 2016-03-22 2017-09-28 Samsung Electronics Co., Ltd. Printed circuit board and semiconductor package including the same
US20170325330A1 (en) * 2016-05-06 2017-11-09 Subtron Technology Co., Ltd. Manufacturing method of circuit substrate
US20180019220A1 (en) * 2016-07-15 2018-01-18 Samsung Display Co., Ltd. Display device and manufacturing method thereof
US20180042110A1 (en) * 2016-08-04 2018-02-08 X-Celeprint Limited Printable 3d electronic structure
US20190350088A1 (en) * 2016-12-23 2019-11-14 Atotech Deutschland Gmbh Method of forming a solderable solder deposit on a contact pad

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
International Search Report issued for PCT/JP2017/016377, dated Aug. 8, 2017.
Written Opinion of the International Searching Authority issued for PCT/JP2017/016377, dated Aug. 8, 2017.

Also Published As

Publication number Publication date
CN109156080A (zh) 2019-01-04
US20190069402A1 (en) 2019-02-28
US20200315006A1 (en) 2020-10-01
JP6696567B2 (ja) 2020-05-20
US20200315005A1 (en) 2020-10-01
WO2017199712A1 (ja) 2017-11-23
US11647581B2 (en) 2023-05-09
CN109156080B (zh) 2021-10-08
JPWO2017199712A1 (ja) 2019-02-14
US11641712B2 (en) 2023-05-02

Similar Documents

Publication Publication Date Title
JP2014123707A (ja) 基板内蔵用積層セラミック電子部品及びその製造方法、並びに基板内蔵用積層セラミック電子部品を備えるプリント基板
US11641712B2 (en) Ceramic electronic component
US10178774B2 (en) Ceramic electronic component and manufacturing method thereof
US20110036622A1 (en) Laminated ceramic electronic component and method for manufacturing the same
JP2020167231A (ja) 積層セラミックコンデンサおよび積層セラミックコンデンサの製造方法
US10638603B2 (en) Multilayer ceramic substrate
KR20080060184A (ko) 다층 세라믹 기판
WO2018037842A1 (ja) セラミック基板及び電子部品内蔵モジュール
JP5582069B2 (ja) セラミック多層基板
EP2690678A1 (en) Layered components and method for producing same
WO2018105333A1 (ja) 多層セラミック基板及び電子装置
WO2018030192A1 (ja) セラミック電子部品
JP2008112787A (ja) 多層セラミックス基板及びその製造方法
US12022622B2 (en) Ceramic electronic component
WO2023002894A1 (ja) セラミック電子部品
JPH04329691A (ja) 導体ぺーストおよび配線基板
JP6773114B2 (ja) セラミック電子部品
JP6455633B2 (ja) 多層セラミック基板及び電子装置
WO2023058497A1 (ja) 電子部品
JP2019078658A (ja) セラミック配線基板およびプローブ基板
JP2012244050A (ja) 多数個取り配線基板の製造方法、多数個取り配線基板および配線基板ならびに電子装置
JP2006210673A (ja) コンデンサ内蔵配線基板

Legal Events

Date Code Title Description
AS Assignment

Owner name: MURATA MANUFACTURING CO., LTD., JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:TAKEMORI, YUKI;REEL/FRAME:047354/0672

Effective date: 20181022

FEPP Fee payment procedure

Free format text: ENTITY STATUS SET TO UNDISCOUNTED (ORIGINAL EVENT CODE: BIG.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

STPP Information on status: patent application and granting procedure in general

Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION

STPP Information on status: patent application and granting procedure in general

Free format text: NON FINAL ACTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: RESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINER

STPP Information on status: patent application and granting procedure in general

Free format text: NOTICE OF ALLOWANCE MAILED -- APPLICATION RECEIVED IN OFFICE OF PUBLICATIONS

STPP Information on status: patent application and granting procedure in general

Free format text: PUBLICATIONS -- ISSUE FEE PAYMENT VERIFIED

STCF Information on status: patent grant

Free format text: PATENTED CASE

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 4