JP5056325B2 - 半導体装置の製造方法および半田ペースト塗布用のメタルマスク - Google Patents
半導体装置の製造方法および半田ペースト塗布用のメタルマスク Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 123
- 229910000679 solder Inorganic materials 0.000 title claims abstract description 101
- 239000002184 metal Substances 0.000 title claims description 33
- 229910052751 metal Inorganic materials 0.000 title claims description 33
- 238000004519 manufacturing process Methods 0.000 title claims description 19
- 239000004020 conductor Substances 0.000 claims abstract description 78
- 239000000758 substrate Substances 0.000 claims abstract description 44
- 239000000919 ceramic Substances 0.000 claims abstract description 22
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 25
- 239000011889 copper foil Substances 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 12
- 229910052802 copper Inorganic materials 0.000 claims description 11
- 239000010949 copper Substances 0.000 claims description 11
- 238000005476 soldering Methods 0.000 claims description 7
- 239000000463 material Substances 0.000 abstract description 17
- 230000002040 relaxant effect Effects 0.000 abstract 1
- 230000035882 stress Effects 0.000 description 13
- 238000010438 heat treatment Methods 0.000 description 12
- 238000000576 coating method Methods 0.000 description 9
- 239000011248 coating agent Substances 0.000 description 8
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- 238000006073 displacement reaction Methods 0.000 description 6
- 239000007787 solid Substances 0.000 description 6
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
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- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 230000035939 shock Effects 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
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- 230000001502 supplementing effect Effects 0.000 description 1
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- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
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- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/3205—Shape
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
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Description
図3は、半導体装置の製造工程を示すフローチャートである。
次に、導体パターン23〜29の所定位置に半田層3を塗布する(ステップS3)。この半田塗布工程では、後述するメタルマスクを用いて実施されるが、メタルマスク以外であっても、例えばディスペンサ(注射器)を用いて半田層3を塗布することも可能である。従来は、半導体チップ下にチップ形状にあわせて半田をベタ塗りしていたため、メタルマスクしか使用できなかった。しかし、本発明の塗布形状を採用し、ディスペンサを使用することで、チップの形状等にあわせてマスクを用意する必要がなくなり、汎用性の高い製造方法が可能になる。
そして、半田層3の加熱処理を行い(ステップS5)、パワー半導体チップ41〜52と導体パターン23〜29とを半田層3を介して接合させる(ステップS6)。
図4は、加熱処理工程におけるパワー半導体チップの位置ずれを説明する図であって、(A),(B)はそれぞれ正常な接合状態を示す断面図および平面図、(C),(D)はそれぞれずれた接合状態を示す断面図および平面図である。
図5(A)〜(C)は、それぞれ半田材塗布工程における半田ペーストの塗布パターンを示す図である。
図5(B)に示す塗布パターン7Bは、二点鎖線で示す配置領域内の中心部分に円形状に半田ペーストを塗布し、さらにその周囲の4箇所の小円と併せて5点塗布するパターンである。
これらの塗布パターンでは、半導体素子40を導体パターン20に接合するための半田層の厚みが100μm以上となるように、半田ペーストを塗布することが好ましい。その場合に、塗布された半田ペースト同士が、その上に載置された半導体素子40を互いに引き合うから、半田材30によって不規則な位置ずれが生じにくい。
このメタルマスク8は、図1の半導体装置に半田ペーストを塗布する際に用いられるものであって、図5(A)に示す4点塗布の塗布パターン7Aが適用されている。図6には、メタルマスク8とともに図1の導体パターン23〜29を二点鎖線で示している。
2 DBC基板
3 半田層
6 ディンプル
7A〜7C 塗布パターン
8 メタルマスク
20,23〜29 導体パターン
21 セラミック基板
22 銅箔
30 半田材
40 半導体素子
41〜52 パワー半導体チップ
53,54 パワー半導体チップ以外の機能素子
91a,91b,91c,92a,93a ディンプル潰しパターン
91〜93 開口部
Claims (5)
- パワー半導体チップを回路配線用導体の所定位置に半田接合してなる半導体装置の製造方法において、
応力緩和用の複数のディンプルを主面の縁部に備えた島状の導体パターンの前記主面の反対側面に接合した絶縁板を用意する工程と、
前記導体パターン上の前記パワー半導体チップが配置される領域、および前記複数のディンプル内に半田ペーストを塗布する工程と、
前記パワー半導体チップを前記導体パターン上に載置して前記半田ペーストを加熱処理することによって半田接合する工程と、
を備えたことを特徴とする半導体装置の製造方法。 - 前記絶縁板は、セラミック基板の一方の主面に放熱用の銅箔が直接接合され、他方の主面に回路配線用導体として複数の銅箔パターンが島状に直接接合されたDBC(Direct Bond Copper)基板であることを特徴とする請求項1記載の半導体装置の製造方法。
- 前記導体パターン上に前記半田ペーストを塗布する工程は、半田塗布用メタルマスクを用いて、前記パワー半導体チップが配置される領域、および前記複数のディンプル内に同時に塗布するようにしたことを特徴とする請求項1記載の半導体装置の製造方法。
- パワー半導体チップを複数のディンプルが形成された回路配線用の導体パターンの所定位置に半田接合する際に用いる半田ペースト塗布用のメタルマスクにおいて、
前記導体パターン上での前記パワー半導体チップの配置領域に対応する第1の開口部と、
前記導電パターンの前記パワー半導体チップが配置される主面の縁部に形成された前記複数のディンプルに対応する第2の開口部と、
を備えたことを特徴とする半田ペースト塗布用のメタルマスク。 - 前記第1の開口部は、前記パワー半導体チップを前記導体パターンに接合するための半田層の厚みが100μm以上となるように、前記パワー半導体チップの配置領域のうち一部領域のみに形成されていることを特徴とする請求項4記載の半田ペースト塗布用のメタルマスク。
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JP5863234B2 (ja) * | 2010-12-01 | 2016-02-16 | デンカ株式会社 | セラミックス回路基板およびこれを用いたモジュール |
KR101904538B1 (ko) * | 2011-11-07 | 2018-10-05 | 주식회사 케이씨씨 | 세라믹회로기판 및 이의 제조 방법 |
EP2827364B1 (en) | 2012-03-15 | 2019-11-27 | Fuji Electric Co., Ltd. | Semiconductor device |
JP6395530B2 (ja) * | 2014-09-11 | 2018-09-26 | 三菱電機株式会社 | 半導体装置 |
JP6333693B2 (ja) | 2014-09-30 | 2018-05-30 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP6430843B2 (ja) * | 2015-01-30 | 2018-11-28 | 株式会社ジェイデバイス | 半導体装置 |
WO2017199712A1 (ja) | 2016-05-16 | 2017-11-23 | 株式会社村田製作所 | セラミック電子部品 |
DE112017007599T5 (de) * | 2017-06-02 | 2020-02-20 | Mitsubishi Electric Corporation | Halbleiterelement-Bondingplatine, Halbleitervorrichtung und Leistungsumwandlungsvorrichtung |
WO2019011654A1 (en) | 2017-07-10 | 2019-01-17 | Abb Schweiz Ag | POWER SEMICONDUCTOR MODULE WITH ALVEOLES IN A METALLIC LAYER UNDER THE FOOT OF A TERMINAL |
CN108321134A (zh) * | 2018-04-09 | 2018-07-24 | 黄山宝霓二维新材科技有限公司 | 高功率密度塑封式ipm模块的封装结构及加工工艺 |
JP2020013908A (ja) | 2018-07-18 | 2020-01-23 | 住友電工デバイス・イノベーション株式会社 | 電子部品の実装構造 |
JP7006812B2 (ja) * | 2018-12-10 | 2022-01-24 | 富士電機株式会社 | 半導体装置 |
EP3696851B1 (en) * | 2019-02-18 | 2022-10-12 | Infineon Technologies AG | Semiconductor arrangement and method for producing the same |
JP2022179872A (ja) | 2021-05-24 | 2022-12-06 | 富士電機株式会社 | 半導体装置 |
JP2022188583A (ja) * | 2021-06-09 | 2022-12-21 | Ngkエレクトロデバイス株式会社 | 半導体装置用基板 |
JP2023074611A (ja) * | 2021-11-18 | 2023-05-30 | 三菱電機株式会社 | 半導体装置および半導体装置の製造方法 |
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JP3115238B2 (ja) * | 1996-09-09 | 2000-12-04 | 株式会社東芝 | 窒化けい素回路基板 |
JP2002299495A (ja) * | 2001-03-30 | 2002-10-11 | Fuji Electric Co Ltd | 半導体回路基板 |
JP2004119568A (ja) * | 2002-09-25 | 2004-04-15 | Kyocera Corp | セラミック回路基板 |
JP2007134395A (ja) * | 2005-11-08 | 2007-05-31 | Rohm Co Ltd | 半導体装置 |
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