TW201839939A - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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Publication number
TW201839939A
TW201839939A TW107107871A TW107107871A TW201839939A TW 201839939 A TW201839939 A TW 201839939A TW 107107871 A TW107107871 A TW 107107871A TW 107107871 A TW107107871 A TW 107107871A TW 201839939 A TW201839939 A TW 201839939A
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Taiwan
Prior art keywords
pad
pads
wiring
semiconductor device
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Prior art date
Application number
TW107107871A
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English (en)
Inventor
小林達也
Original Assignee
日商瑞薩電子股份有限公司
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Application filed by 日商瑞薩電子股份有限公司 filed Critical 日商瑞薩電子股份有限公司
Publication of TW201839939A publication Critical patent/TW201839939A/zh

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Abstract

本發明之課題在於提高構成半導體裝置之配線基板之配線設計之自由度。 於構成BGA封裝構造之半導體裝置1之配線基板WCB之安裝面之外周側，在透視俯視下不與配置於配線基板WCB之晶片搭載面之複數根引線LA重疊的位置，配置有NSMD構造且為焊盤上通孔構造之焊盤LD1。另一方面，於配線基板WCB之安裝面，於較一群焊盤LD1靠內側，在透視俯視下與配置於配線基板WCB之晶片搭載面之複數根引線LA重疊的位置，配置有NSMD構造且與引出用之配線部WB連接之焊盤部LD2。

Description

半導體裝置
本發明係關於一種半導體裝置技術，例如關於一種應用於具備突起電極之半導體裝置技術較為有效之技術。
例如，於日本專利特開2009-302227號公報(專利文獻1)及日本專利特開2010-93109號公報(專利文獻2)中，記載有如下構造，即：將搭載於配線基板之半導體晶片之電極通過配置於配線基板之安裝面之突起電極引出至外部。 於專利文獻1中，揭示有：焊盤上導通孔(Land On Via)構造，其係將貫通上述配線基板之導通孔直接連接於形成突起電極之焊盤；NSMD(Non Solder Mask Defined，非阻焊層限定)構造，其係在形成於配線基板之安裝面之阻焊層之開口部內內包焊盤；及SMD(Solder Mask Defined，阻焊層限定)構造，其係藉由形成於配線基板之安裝面之阻焊層覆蓋焊盤之周緣部。 又，於專利文獻2中，揭示有如下構造，即：將於配線基板之安裝面之外周側呈複數行環繞排列之焊料球群、及於配線基板之安裝面之中央側呈複數行環繞排列之焊料球群設置於配線基板之安裝面。 [先前技術文獻] [專利文獻] [專利文獻1]日本專利特開2009-302227號公報 [專利文獻2]日本專利特開2010-93109號公報
[發明所欲解決之問題] 但，BGA(Ball Grid Array，球狀柵格陣列)型及LGA(Land Grid Array，焊盤柵格陣列)型等之半導體裝置中所使用的配線基板之焊盤(供成為外部端子之焊料材接合之部分)之構造多種多樣。 例如，於NSMD構造(參照專利文獻1之圖10及圖11)中，不藉由絕緣膜(阻焊膜)覆蓋焊盤之周緣部，且自形成於該絕緣膜之開口部露出了焊盤及與該焊盤相連之配線(引出配線)之一部分。又，例如，於SMD構造(參照專利文獻1之圖12及圖13)中，藉由絕緣膜(阻焊膜)覆蓋焊盤之周緣部及與該焊盤相連之配線。於NSMD構造及SMD構造中，配線基板之貫通孔形成於不與焊盤重疊之位置。進而，例如，如專利文獻1之圖18及圖19所示，亦有：由不藉由絕緣膜覆蓋焊盤之周緣部之NSMD構造，且配線基板之貫通孔(導通孔(Via)、通孔(through hole))形成於與焊盤重疊之位置之所謂焊盤上通孔構造(焊盤上導通孔構造)構成的焊盤；及由藉由絕緣膜覆蓋焊盤之周緣部之SMD構造，且配線基板之貫通孔形成於與焊盤重疊之位置之所謂焊盤上通孔構造構成的焊盤等。 此處，於焊盤上導通孔構造之情形時，在與焊盤相同之層不存在與焊盤相連之配線，因此與該焊盤接合之焊料材不僅能與焊盤之上表面接觸，而且能與和該上表面交叉之焊盤之側面接觸，故而於上述構造案之中，其熱應力耐性最優異。但，根據本發明人之研究可知：若對所有焊盤均採用焊盤上導通孔構造，則難以實施將配置於配線基板之上表面(半導體晶片之搭載面)之複數根引線(接合引線、接合指件)與配置於配線基板之下表面(安裝面)之複數個焊盤相連之複數根配線之牽引。 其他問題及新穎特徵將藉由本說明書之記述及隨附圖式得以明瞭。 [解決問題之技術手段] 於一實施形態之半導體裝置中，在配線基板之安裝面之外周側，且透視俯視下不與配置於配線基板之晶片搭載面之複數根引線重疊的位置，配置有NSMD構造且為焊盤上通孔構造之焊盤。另一方面，於較配置於配線基板之安裝面之焊盤上通孔構造之一群焊盤靠內側，在透視俯視下與配置於配線基板之晶片搭載面之複數根引線重疊的位置，配置有NSMD構造且與引出用之配線部連接之焊盤部。 又，於一實施形態之半導體裝置中，在配線基板之安裝面之外周側，且透視俯視下不與配置於配線基板之晶片搭載面之複數根引線重疊的第1區域，配置有NSMD構造且為焊盤上通孔構造之焊盤。另一方面，於較配線基板之安裝面之第1區域靠內側，在透視俯視下與配置於配線基板之晶片搭載面之複數根引線重疊的第2區域，配置有NSMD構造且與引出用之配線部連接之焊盤部。 [發明之效果] 根據一實施形態，能提高構成半導體裝置之配線基板之配線設計之自由度。
於以下實施形態中，為方便起見，必要時會分割成複數個部分或實施形態而進行說明，除非特別明確指出時，否則其等並非互無關係者，而是存在一方為另一方之一部分或全部之變化例、詳細說明、補充說明等關係。 又，於以下實施形態中，在提及要素之數等(包括個數、數值、量、範圍等)之情形時，除非特別明確指出時及原理上明確限定於特定數時等，否則並不限定於該特定數，而亦可為特定數以上或以下。 進而，於以下實施形態中，關於其構成要素(亦包括要素步驟等)，除非特別明確指出時及原理上明確認為必要時等，否則未必必要，此點不言自明。 同樣地，於以下實施形態中，在提及構成要素等之形狀、位置關係等時，除非特別明確指出時及原理上明確認為並非如此時等，否則包括實質上與該形狀等近似或類似者等。關於上述數值及範圍，亦同樣如此。 又，於用以說明實施形態之所有圖式中，對同一構件原則上標註相同符號，並省略其之重複說明。再者，為使圖式容易看懂，有時即便對俯視圖亦標附影線。 (實施形態1) 《半導體裝置》 圖1係本實施形態1之半導體裝置之安裝面之俯視圖，圖2係圖1之I-I線之剖視圖，圖3係圖2之以虛線包圍之區域A1之放大剖視圖。又，圖4係構成圖1之半導體裝置之配線基板之晶片搭載面的主要部分放大俯視圖，圖5係配置於圖4之晶片搭載面之複數根引線之放大俯視圖。進而，圖6係圖1之半導體裝置之安裝面之將焊料球除去後所示的俯視圖，圖7係圖6之以虛線包圍之區域A2之放大俯視圖。 本實施形態1之半導體裝置1例如係以MAP(Mold Array Package，塑模陣列封裝)方式形成之BGA(Ball Grid Array)封裝構造之半導體裝置，具備配線基板WCB、及搭載於配線基板WCB之晶片搭載面之大致中央之晶片搭載區域的半導體晶片(以下，簡稱為晶片)CHP。 配線基板WCB係形成有將晶片CHP之積體電路之電極引出至外部之配線的構造體。該配線基板WCB例如俯視下形成為四邊形，其外形尺寸例如為20×20 mm以上，作為具體例，設定為25×25 mm。 構成該配線基板WCB之基材SB例如由俯視下形成為四邊形之絕緣薄板形成，具有晶片搭載面(第1面)、其相反側之安裝面(第2面)、及積層於其等之間之複數個絕緣層IF。各絕緣層IF例如由環氧樹脂形成。再者，關於對配線基板WCB(或基材SB)所謂之四邊形，亦包括藉由在配線基板WCB(或基材SB)之角部形成錐度(taper)等而形成為多邊形或圓角四邊形之情況。 如圖3及圖4所示，於該基材SB之晶片搭載面，配置有複數根引線(接合指件、接合引線)LA、複數個通孔焊盤TLA、及將其等電性連接之複數個配線部WA。該引線LA、通孔焊盤TLA及配線部WA例如由銅(Cu)等金屬形成為一體。 引線LA係以包圍晶片CHP之方式沿著晶片CHP之外周並列而配置有複數個。此處，如圖4所示，引線LA例如以呈2行排列之狀態沿著晶片CP之外周(四邊)而配置。該2行引線LA(LA1、LA2)係以相互隔開之狀態呈鋸齒狀而配置。即，2行引線LA(LA1、LA2)係以沿著晶片CHP之外周而位置錯開之狀態配置。如圖5所示，各引線LA之寬度Lw例如為85 μm左右。引線LA之最小間隔Ld例如為50 μm左右。引線LA之最小間距Lp例如為370 μm左右。 如圖4所示，通孔焊盤TLA係以寬度大於引線LA及配線部WA且俯視下呈大致圓形之圖案形成。該通孔焊盤TLA之直徑例如為300 μm左右，通孔焊盤TLA之最小間距例如為370 μm左右。 又，於基材SB之晶片搭載面，以覆蓋上述複數個通孔焊盤TLA及複數個配線部WA之方式，形成有阻焊層(第1絕緣膜)SR1。阻焊層SR1例如由環氧系樹脂與丙烯酸系樹脂之混合樹脂形成。如圖4所示，於阻焊層SR1之一部分，形成有供上述配線部WA之一部分露出之開口部KA。自該開口部KA露出之配線部WA之一部分成為引線LA。再者，於圖4中，為使圖式容易看懂，對阻焊層SR1標附有影線。 又，如圖2及圖3所示，於基材SB之晶片搭載面，晶片CHP以其主面(第3面)朝上，且晶片CHP之背面(第4面)朝向基材SB之晶片搭載面之狀態，隔著黏晶材DB及阻焊層SR1搭載於基材SB(配線基板WCB)上。再者，黏晶材DB例如由膏材或膜材等形成。 晶片CHP例如俯視下形成為四邊形，其外形尺寸例如為7×7 mm左右。如圖4所示，於該晶片CHP之主面之外周(四邊)附近，沿著晶片CHP之外周(四邊)並列而配置有複數個焊墊(電極)PD。焊墊PD與晶片CHP之積體電路電性連接，並且如圖3所示，經由接合導線(以下，簡稱為導線)BW與配線基板WCB之引線LA電性連接。 又，如圖3所示，於基材SB之晶片搭載面上，以覆蓋晶片CHP、導線BW、引線LA及阻焊層SR1之方式，形成有樹脂密封體MD。樹脂密封體MD例如由熱硬化性之環氧樹脂形成。樹脂密封體MD之側面與配線基板WCB之側面一致，以相對於配線基板WCB之晶片搭載面大致垂直之狀態形成。 另一方面，如圖3及圖6所示，於基材SB之安裝面，配置有複數個焊盤(凸塊焊盤、焊墊、端子)LD(LD1、LD2、LD3)、複數個通孔焊盤TLB、及複數個配線部WB。焊盤LD(LD1、LD2、LD3)、通孔焊盤TLB及配線部WB例如由銅(Cu)等金屬形成。 焊盤(第1焊盤)LD1例如以呈2行排列之狀態沿著基材SB之外周(四邊：緣)而配置。又，被一群焊盤LD1包圍之內側之焊盤(第2焊盤)LD2、LD3亦分別以呈2行排列之狀態沿著基材SB之外周(四邊：緣)而配置。一群焊盤LD1與一群焊盤LD2之間(最短距離)、及一群焊盤LD2與一群焊盤LD3之間(最短距離)空開有1行焊盤LD量(1個焊盤LD量)以上之間隔。藉此，能容易地實施安裝半導體裝置1之母板側之配線之牽引。 各焊盤LD(LD1~LD3)例如俯視下形成為圓形，其直徑例如為400 μm左右。又，如圖7所示，相鄰之焊盤LD(LD1~LD3)之間距Dp例如為800 μm左右。 又，如圖2及圖3所示，於各焊盤LD(LD1~LD3)接合有焊料球(焊料凸塊、外部端子、突起電極)BE。焊料球BE例如由錫(Sn)-銀(Ag)-銅(Cu)合金等無鉛合金形成。 如圖3所示，通孔焊盤TLB配置於晶片搭載區域內。通孔焊盤TLB係以寬度大於配線部WB，且直徑小於焊盤LD(LD1~LD3)之直徑之大致圓形之圖案形成。通孔焊盤TLB之直徑例如為300 μm左右，通孔焊盤TLB之最小之相鄰間距例如為370 μm左右。 配線部WB係將焊盤LD2、LD3之各者與通孔焊盤TLB電性連接之引出配線部分，與焊盤LD2、LD3及通孔焊盤TLB形成為一體。配線部WB之寬度例如為300 μm左右。 又，於基材SB之安裝面，以覆蓋配線部WB之一部分及通孔焊盤TLB之方式，形成有阻焊層(第2絕緣膜)SR2。阻焊層SR2例如由環氧系樹脂與丙烯酸系樹脂之混合樹脂形成。於該阻焊層SR2之一部分，形成有使上述焊盤LD(LD1~LD3)及配線部WB之一部分露出之複數個開口部KB。 該開口部KB俯視下形成為直徑大於焊盤LD(LD1~LD3)之直徑之圓形，以內包各焊盤LD(LD1~LD3)整體之狀態配置。即，於本實施形態之半導體裝置1中，該安裝面之所有焊盤LD均為NSMD(Non Solder Mask Defined)構造之焊盤LD。開口部KB之直徑例如為520 μm左右。關於該焊盤構造將於下文敍述。 又，如圖2及圖3所示，於基材SB之晶片搭載面與安裝面之間形成有複數個配線層，於各配線層形成有內層配線WI。內層配線WI例如由銅(Cu)等金屬形成。配線層之層數例如為2層、4層或4層以上。再者，基材SB於為具有2層配線層之雙層基板之情形時，相當於核心材料，於為具有4層或4層以上之配線層之多層基板之情形時，相當於被阻焊層SR1、SR2所夾之所有絕緣層IF之集合體。即，此處所謂之「基材」包含複數個絕緣層IF。 又，如圖3所示，將該晶片搭載面及其背面之安裝面貫通之複數個通孔(貫通孔)TH(TH1、TH2)相對於晶片搭載面及安裝面大致垂直地形成於基材SB。於各通孔TH(TH1、TH2)內部設置有通孔配線WT(WT1、WT2)。各通孔TH(TH1、TH2)之直徑例如為150 μm左右。 一通孔(第1貫通孔)TH1在基材SB之晶片搭載面之外周側之通孔焊盤TLA及基材SB之安裝面之外周側之焊盤LD1上，配置於俯視下重疊之位置。藉此，基材SB之晶片搭載面之外周側之通孔焊盤TLA與基材SB之安裝面之外周側之焊盤LD1通過通孔配線(第1通孔配線)WT1而電性連接。即，基材SB之晶片搭載面之外周側之通孔焊盤TLA通過通孔配線WT1而與基材SB之安裝面之外周側之焊盤LD1直接電性連接。 另一通孔(第2貫通孔)TH2在配置於基材SB之晶片搭載面之中央側(晶片搭載區域內)之通孔焊盤TLA、及配置於基材SB之安裝面之中央側(晶片搭載區域內)之通孔焊盤TLB上，配置於俯視下重疊之位置。藉此，基材SB之晶片搭載面之中央側(晶片搭載區域內)之通孔焊盤TLA與基材SB之安裝面之中央側(晶片搭載區域內)之通孔焊盤TLB通過通孔配線(第2通孔配線)WT2而電性連接。即，基材SB之晶片搭載面之通孔焊盤TLA經過通孔配線WT2而與基材SB之安裝面之通孔焊盤TLB電性連接，進而經過一體形成(連接)於該通孔焊盤TLB之配線部WB而與焊盤LD2、LD3電性連接。 其次，對配置於半導體裝置之安裝面之焊盤構造，就本發明人所發現之問題進行說明。 圖8之左圖係SMD構造之焊盤之俯視圖，圖8之右圖係圖8之左圖之II-II線之局部剖視圖。SMD(Solder Mask Defined)構造之情形時，形成於阻焊層SR2之開口部KC之直徑小於焊盤LD之直徑，開口部KC內包於焊盤LD之上表面(與母板對向之面)內。因此，焊盤LD之上表面之外周附近部分遍及全周地由阻焊層SR2覆蓋。於該情形時，焊料球BE與焊盤LD之接觸面平坦(直線性)，焊料球BE與焊盤LD之接合面積與NSMD構造之焊盤LD相比變小。因此，於溫度週期試驗等伴有熱之試驗中，在阻焊層SR2之開口部KC之內周附近，焊料球BE易產生裂痕CK。即，於SMD構造之情形時，有焊料球BE與焊盤LD之接合可靠性降低之問題。 另一方面，圖9之左圖係NSMD構造之焊盤之俯視圖，圖9之右圖係圖9之左圖之III-III線之局部剖視圖。NSMD構造之情形時，形成於阻焊層SR2之開口部KB之直徑大於焊盤LD之直徑，開口部KB內包焊盤LD。因此，於NSMD構造之情形時，自阻焊層SR2之開口部KB露出焊盤LD之上表面及與該上表面交叉之側面。因此，焊料球BE與焊盤LD之上表面及側面接合，故而NSMD構造之焊盤LD比起SMD構造之焊盤LD，焊料球BE與焊盤LD之接合可靠性更高。但，即便於為NSMD構造之情形，亦存在自焊盤LD之外周之一部分向外側延伸之配線部WB，而於該配線部WB重疊開口部KB之外周。因此，於溫度週期試驗等伴有熱之試驗中，應力集中於與開口部KB之外周所重疊之配線部WB部分，使得焊料球BE產生裂痕CK。即，即便於NSMD構造之情形，在連接有引出用之配線部之情形時，亦有焊料球BE與焊盤LD之接合可靠性降低之問題。根據本發明人之研究，即便於使用NSMD構造之焊盤之情形下，當在焊盤連接有引出至用之配線部之情形時，例如，若配線基板WCB之外形尺寸為20×20 mm以上，則在熱應力相對較大之配線基板WCB之外周部側，焊料球BE產生裂痕CK之問題便會變得顯著。 其次，圖10之左圖係NSMD構造且為焊盤上通孔構造(焊盤上導通孔構造)之焊盤之俯視圖，圖10之右圖係圖10之左圖之IV-IV線之局部剖視圖。本實施形態1之焊盤為焊盤上通孔構造(焊盤上導通孔構造)，且為NSMD構造。即，以形成於阻焊層SR2之開口部KB之直徑大於焊盤LD之直徑、且開口部KB內包焊盤LD之狀態配置。但，於焊盤上通孔構造之情形時，通孔TH在俯視下與焊盤LD重疊，在與焊盤LD相同之層不存在與焊盤LD相連之配線部。因此，焊料球BE與焊盤LD之上表面及全周之側面接合，故而焊料球BE之接合強度提高，焊料球BE難以產生裂痕。因此，焊盤上通孔構造於上述焊盤構造之中，熱應力耐性最優異。 但，根據本發明人之研究清楚瞭解到：若對配線基板WCB之安裝面內之所有焊盤LD均採用焊盤上通孔構造，則難以實施將配置於配線基板WCB之晶片搭載面之複數根引線LA與配置於配線基板WCB之安裝面之複數個焊盤LD相連之複數根配線之牽引。圖11係將配線基板之晶片搭載面之引線與配線基板之安裝面之焊盤重疊所示的局部俯視圖。引線LA與導線BW(參照圖3)連接，故而其係對照晶片CHP之焊墊PD之尺寸(間距或相鄰間隔)而形成。因此，引線LA之相鄰間隔較窄，係以高密度而配置。另一方面，焊盤LD自確保與焊料球BE之接合可靠性之觀點而言不能設定得太小，自與母板之焊盤(端子、電極)連接之觀點而言不能使間隔較窄而配置。因此，若於配置有引線LA之區域(透視俯視下重疊之區域)配置了焊盤上通孔構造之焊盤LD，則引線LA之配置本身即會變得困難，將引線LA與焊盤LD連接之配線之牽引亦會變得困難。因此，難以進行配線基板WCB之配線之佈局設計，故而不僅配線基板WCB之開發耗費時間，而且半導體裝置1之成本增高。又，因難以進行配線之佈局，故亦有導致配線基板WCB大型化之情形。 因此，於本實施形態之半導體裝置1中，如圖3等所示，對在配線基板WCB之安裝面之外周側，配置於透視俯視下不與引線LA重疊之位置之焊盤LD1，採用了NSMD構造且引出用之配線部不與焊盤LD1連接之焊盤上通孔構造。另一方面，對在配線基板WCB之安裝面之中央側，透視俯視下與引線AL重疊之焊盤LD2，不採用焊盤上通孔構造，而採用了NSMD構造且與引出用之配線部WB連接之焊盤構造。 具體而言，例如，按以下方式進行設置。圖12係對圖6之半導體裝置之安裝面表示周邊區域及中央區域之俯視圖，圖13係圖12之V-V線之剖視圖，圖14係圖12之半導體裝置之配線基板之安裝面的主要部分放大俯視圖，圖15係圖12之半導體裝置之配線基板之晶片搭載面的主要部分放大俯視圖。再者，於圖12中，亦透視示出了配置於配線基板WCB之安裝面之晶片CHP及複數根引線LA。又，於圖15中，為使圖式容易看懂，對阻焊層SR1標附有影線。 於本實施形態1中，如圖12及圖13所示，在配線之佈局設計上，將配線基板WCB之安裝面分為周邊區域(第1區域)PA、及其內側之中央區域(第2區域)CA。再者，於圖12中，為使圖式容易看懂，對周邊區域PA及中央區域CA標附有影線。 周邊區域PA係配置NSMD構造且不與引出用之配線部WB連接之焊盤上通孔構造之焊盤的區域，其係自配線基板WCB之外周向中央具有寬度地配置。配置於配線基板WCB之晶片搭載面內之複數根引線LA配置在透視俯視下不與周邊區域PA重疊之位置。即，配置於配線基板WCB之晶片搭載面之複數根引線LA與配置於配線基板WCB之安裝面之外周側之複數個焊盤LD1在透視俯視下不重疊。再者，關於配置在該周邊區域PA之焊盤上通孔構造之焊盤之具體例，將於下文敍述。 另一方面，中央區域CA係配置NSMD構造且與引出用之配線部連接之焊盤的區域，其係以被周邊區域PA包圍之狀態配置於較周邊區域PA靠內側。配線基板WCB之晶片搭載面內之複數根引線LA配置於透視俯視下與中央區域CA重疊之位置。即，配置於配線基板WCB之晶片搭載面之複數根引線LA與配置於配線基板WCB之安裝面之中央側之複數個焊盤LD2在透視俯視下重疊。再者，關於配置在該中央區域CA之NSMD構造且與引出用之配線部連接之焊盤之具體例，將於下文敍述。 進而，如圖12~圖15所示，於周邊區域PA與中央區域CA之間配置有空閒區域FA。空閒區域FA不屬於周邊區域PA及中央區域CA任何一者。該空閒區域FA之間隔(周邊區域PA之內周與中央區域CA之外周之最短距離：第3間隔)Fd大於焊盤LD(LD1、LD2)之直徑。 又，空閒區域FA之間隔Fd大於焊盤LD之間隔Dd(沿著配線基板WCB之緣配置之焊盤LD1、LD1彼此之間隔Dd1，或沿著配線基板WCB之緣配置之焊盤LD2、LD2彼此之間隔Dd2)。再者，此處間隔Dd1、Dd2相等。 又，空閒區域FA之間隔Fd大於焊盤LD之相鄰間距Dp(沿著配線基板WCB之緣配置之焊盤LD1、LD1彼此之相鄰間距Dp1，或沿著配線基板WCB之緣配置之焊盤LD2、LD2彼此之相鄰間距Dp2)。再者，此處相鄰間距Dp1、Dp2相等。 又，換種看法而言，例如成為如下情況。即，焊盤LD1、LD2中相互以於最近位置相鄰之狀態配置之焊盤(第1基準焊盤、第2基準焊盤)LD1、LD2之間隔(第1間隔)Dsd大於焊盤LD之間隔Dd(沿著配線基板WCB之外周方向相鄰之2個焊盤LD1、LD1彼此之間隔Dd1，或沿著配線基板WCB之外周方向相鄰之2個焊盤LD2、LD2彼此之間隔Dd2)。 又，焊盤LD1、LD2之間隔Dsd大於焊盤LD(LD1、LD2)之直徑。又，焊盤LD1、LD2之間隔Dsd大於焊盤LD之相鄰間距Dp(沿著配線基板WCB之外周方向相鄰之2個LD1、LD1彼此之相鄰間距Dp1，或沿著配線基板WCB之外周方向相鄰之2個焊盤LD2、LD2彼此之相鄰間距Dp2)。 此處，參照圖15對中央區域CA之外周位置(範圍設定)進行說明。如上所述，若將焊盤上通孔構造之焊盤LD1(參照圖14)配置於透視俯視下與引線LA重疊之位置，則難以實施配線牽引。自該觀點而言，可認為能將焊盤上通孔構造之焊盤LD1配置於透視俯視下不與引線LA重疊之位置、即較引線LA1(LA)靠外側(配線基板WCB之外周側：圖15之右側)。但，實際上，因較引線LA1靠外側之配線部WA亦係以密集之狀態配置，故若於該配線部WA之密集區域以透視俯視下重疊之狀態配置焊盤上通孔構造之焊盤LD1，則與引線LA之配置區域同樣地，難以實施配線基板WCB之配線之牽引。 因此，於本實施形態中，將中央區域CA擴展至較引線LA1靠外側之配線部WA之配置區域之一部分為止。即，將中央區域CA之外周位置設定為自晶片CHP之中心位置X0至引線LA1之最外端之位置X1為止之長度Rc1加上長度Rc2所達之位置X2。該長度Rc2例如大於等於焊盤LD(LD1、LD2)之直徑。該長度Rc2之條件可為與上述間隔Fd中所說明者相同之長度之條件。藉由如此設定，能使較引線LA1靠外側之配線部WA之密集區域亦成為NSMD構造且與引出用之配線部連接之焊盤LD2、LD3之配置區域。因此，能容易地實施配線基板WCB之配線之牽引。 另一方面，根據與上述相同之理由，若周邊區域PA(即，配置焊盤上通孔構造之焊盤LD1之區域)進入配線基板WCB之晶片搭載面側之配線部WA之密集區域，則難以實施配線基板WCB之配線之牽引。 因此，於本實施形態中，規定要將周邊區域PA之內周配置於中央區域CA之外周之自位置X2隔開上述間隔Fd之位置X3。即，將周邊區域PA設定於自配線基板WCB之外周之位置X4至中央區域CA之外周之位置X2為止之長度Rc3減去間隔Fd所達之位置X3。藉由如此設定，焊盤上通孔構造之焊盤LD1不會被配置於引線LA之外側之配線部WA之密集區域，故而能容易地實施配線基板WCB之配線之牽引。再者，上述例中，於設定周邊區域PA及中央區域CA之邊界(外周及內周)位置時，係以晶片CHP之中心為基準，但並不限定於此。例如，亦可將配線基板WCB之中心之位置、配線基板WCB之外周之位置、或者既已決定之周邊區域PA或中央區域CA之邊界位置作為基準。 其次，對配置於本實施形態1中之半導體裝置1之安裝面之中央區域CA及周邊區域PA的焊盤LD(LD1~LD3)之構造例進行說明。圖16之左圖係配置於半導體裝置之安裝面之中央區域之焊盤的主要部分俯視圖，圖16之右圖係配置於半導體裝置之安裝面之周邊區域之焊盤的主要部分俯視圖，圖17之左圖係圖16之左圖之VI-VI線之剖視圖，圖17之右圖係圖16之右圖之VII-VII線之剖視圖。再者，於圖16中，為使圖式容易看懂，對阻焊層SR2標附有影線。 如圖16及圖17之左圖所示，於半導體裝置1之配線基板WCB之中央區域CA，配置有NSMD構造且與引出用之配線部WB連接之焊盤LD2、LD3。即，於阻焊層SR2，形成有直徑大於焊盤LD2、LD3且內包焊盤LD2、LD3之開口部(第2開口部)KB2(KB)。而且，自開口部KB2露出了焊盤LD2、LD3、及與其等連接之配線部WB之一部分。再者，開口部KB2之直徑與開口部KB、KB1相同。 焊盤LD2、LD3通過形成於基材SB之安裝面之引出用之配線部WB，而與形成於基材SB之安裝面之通孔焊盤TLB電性連接。該通孔焊盤TLB經由通孔配線WT2，而與形成於基材SB之晶片搭載面之通孔焊盤TLA電性連接。通孔配線WT2係藉由被例如銅(Cu)等導體膜被覆而形成於對基材SB穿孔而成之通孔TH2之整個內壁面。於該通孔TH2內之較通孔配線WT2用之導體膜靠內側，填充有絕緣膜Fi。絕緣膜Fi例如由樹脂形成。 如此，藉由於配線基板WCB之中央區域CA配置NSMD構造且與引出用之配線部WB連接之焊盤LD，能使引線LA與焊盤LD免於令配線之牽引混亂地良好連接。因此，能提高配置高密度配線之配線基板WCB之配線設計之自由度。因此，能縮短半導體裝置1之開發時間。又，能高密度地配置配線基板WCB之配線，故而能推進半導體裝置1之小型化。進而，能降低半導體裝置1之成本。 繼而，如圖16及圖17之右圖所示，於半導體裝置1之配線基板WCB之周邊區域PA，配置有NSMD構造且引出用之配線部WB不與焊盤連接之焊盤上通孔構造之焊盤LD1。即，於阻焊層SR2，形成有直徑大於焊盤LD1且內包焊盤LD1之開口部(第1開口部)KB1(KB)。因於焊盤LD1未連接引出用之配線部WB，故焊盤LD1之上表面及整個側面自開口部KB1露出。 又，形成於基材SB之安裝面之焊盤LD1經由通孔配線WT1，而與形成於基材SB之晶片搭載面之通孔焊盤TLA電性連接。該通孔配線WT1亦係藉由被例如銅(Cu)等導體膜被覆而形成於對基材SB穿孔而成之通孔TH1之整個內壁面。又，該情形時，亦為於該通孔TH1內之較通孔配線WT1用之導體膜靠內側，填充有由樹脂等形成之絕緣膜Fi。 如此地，於配線基板WCB之被施加相對較大熱應力之周邊區域PA，配置NSMD構造且不與引出用之配線部WB連接之焊盤上通孔構造之焊盤LD1。藉此，能提高配線基板WCB之安裝面之外周側之焊盤LD1與焊料球BE之接合強度，故而能抑制或防止焊料球BE之裂痕之產生。因此，能提高半導體裝置1與母板之連接可靠性。 但，通孔配線WT之構造並不限定於上述者。圖18之左圖係通孔配線之變化例且相當於圖16之左圖之VI-VI線之部位的剖視圖，圖18之右圖係通孔配線之變化例且相當於圖16之右圖之VII-VII線之部位的剖視圖。此處，於通孔TH1、TH2內未填充絕緣膜Fi，而是填充有例如銅(Cu)等金屬膜。即，圖18之通孔配線WT1、WT2係藉由向通孔TH1、TH2內僅埋入金屬膜而形成。 《半導體裝置之製造方法》 其次，依循圖19之步驟圖，參照圖20~圖28對用以製造本實施形態1之半導體裝置1之MAP方式(封裝塑模方式)之一例進行說明。 1.背面研磨 首先，使用通常之半導體製造技術，對具有晶片區域之半導體晶圓(以下，簡稱為晶圓WF)之背面，如圖20所示般進行研磨(背面研磨：圖19之S101)，上述晶片區域係藉由形成電晶體(MISFET(Metal Insulator Semiconductor Field Effect Transistor，金屬絕緣半導體場效應管))等積體電路元件或多層配線而形成有積體電路。即，於以保護帶PT覆蓋晶圓WF之元件形成面(正面)後，將晶圓WF之與元件形成面(正面)為相反側之背面朝上而配置於載台上。繼而，利用研磨機G對晶圓WF之背面進行研磨，藉此將晶圓WF之厚度打薄。由此，進行晶圓WF之研磨。 2.晶圓切割 其後，如圖21所示，藉由切割晶圓WF，而將晶圓WF單片化為各個晶片(圖19之S102)。即，首先，對同心圓狀之切晶框架DFM貼附切晶帶DT後，將晶圓WF配置於該切晶帶DT上。繼而，使用旋轉之切晶刀DS，沿著切晶線將晶圓WF切斷，藉此將晶圓WF單片化為晶片。 3.黏晶 繼而，如圖22所示，將單片化而成之晶片CHP搭載於配線基板WCB上(黏晶：圖19之S103)。即，利用吸嘴C1吸附晶片CHP後，經由黏晶材DB將晶片CHP搭載於配線基板WCB上。此時，配線基板WCB已被以能形成複數個半導體裝置之方式一體化，將晶片CHP分別搭載於各個半導體裝置之取得區域。其後，為提高晶片CHP與配線基板WCB之接著強度而進行熱處理(烘烤)。 4.電漿清洗 繼而，對搭載有晶片CHP之配線基板WCB之表面(晶片搭載面)實施電漿清洗(圖19之S104)。進行電漿清洗之目的在於：提高其後所要實施之塑模步驟中之樹脂與配線基板WCB之密接性等。再者，於使用與配線基板WCB之密接性較佳(較高)之樹脂之情形時，亦可省略本電漿清洗步驟。 5.導線接合 其後，如圖23所示，將形成於配線基板WCB之引線與晶片CHP之焊墊藉由例如由金線構成之導線BW連接(圖19之S105)。具體而言，將導線BW以毛細管C2快速接合於晶片CHP之焊墊後，使毛細管C2移動，藉此將導線BW第二接合於配線基板WCB之引線。由此，將配線基板WCB之引線與晶片CHP之焊墊藉由導線BW電性連接。再者，所使用之導線BW並不限於金(Au)，而亦可為例如由以銅(Cu)為主成分之材料構成之導線。 6.塑模 繼而，如圖24所示，將配線基板WCB之整個晶片搭載面以樹脂M密封(圖19之S106)。具體而言，以使搭載於配線基板WCB上之複數個晶片CHP位於形成在下模具BK之1個模腔(凹穴)內之方式，自上下利用上模具UK與下模具BK夾住搭載有晶片CHP之配線基板WCB，並使樹脂M自插入口流入下模具BK之塑模空間內。藉此，將配線基板WCB上之複數個晶片CHP一次性地以樹脂M密封。其後，為使樹脂M硬化，而對配線基板WCB進行熱處理(烘烤)。再者，上述模腔亦可使用設置於上模具UK而非設置於下模具BK之成形模具。 7.焊料印刷 繼而，如圖25所示，於配線基板WCB之背面以焊料印刷方式塗佈焊料膏SP(圖19之S107)。具體而言，於配線基板WCB之背面配置金屬遮罩MSK，利用刮漿板S1於該金屬遮罩MSK上印刷焊料膏SP。藉此，如圖26所示，於配線基板WCB之焊盤LD(焊盤LD1~LD3：參照圖3等)上形成焊料膏SP。其後，如圖27所示，對配線基板WCB實施回焊，藉此使形成於配線基板WCB之背面之焊料膏SP成為半球狀之焊料球BE。以此方式於配線基板WCB之背面形成由焊料球BE構成之外部連接端子。再者，外部連接端子(焊料球BE)之形成方法並不限於上述焊料印刷方式，而亦可採用所謂之球供給方式，即：將形成為球體狀之焊料球供給至焊盤上，藉由加熱而使焊料球熔融，以此將焊料球連接於焊盤。 8.封裝切割 其後，如圖28所示，切割配線基板WCB(封裝切割：圖19之S108)。即，首先，對同心圓狀之切晶框架DFM貼附切晶帶DT後，將封裝塑模後之配線基板WCB配置於該切晶帶DT上。繼而，使用高速旋轉之切晶刀DS將配線基板WCB切斷，藉此取得各個半導體裝置1。以此方式能製造出圖1及圖2等所示之BGA封裝構造之半導體裝置1。半導體裝置1之配線基板WCB之晶片搭載面由以樹脂M構成之樹脂密封體MD密封。另一方面，於配線基板WCB之與晶片搭載面為相反側之安裝面，形成有由焊料球BE構成之外部連接端子。其後，將BGA封裝構造之半導體裝置1收納並出貨。 《半導體裝置之安裝構造例》 其次，參照圖29對以上述方式製造出之半導體裝置1之安裝例進行說明。圖29係圖1之半導體裝置及搭載有半導體裝置之母板之主要部分剖視圖。 首先，在形成於母板MCB之焊盤MLD上形成焊料膏(助焊劑)。母板MCB側之焊盤構造例如成為圖8所示之SMD構造。即，在形成於母板MCB之裝置搭載面之阻焊層SR3，以被內包於焊盤MLD之狀態形成有較母板MCB之焊盤MLD之直徑小之開口部KC。 繼而，以使半導體裝置1之安裝面朝向母板MCB之狀態，將半導體裝置1之安裝面之焊料球BE與母板MCB之焊盤MLD經由焊料膏而連接。其後，對母板MCB及半導體裝置1進行回焊(熱處理)，藉此使半導體裝置1之焊料球BE與母板MCB之焊盤MLD上之焊料膏一體化，而將半導體裝置1安裝於母板MCB上。 於此種安裝步驟後，對半導體裝置1實施溫度週期試驗等。溫度週期試驗時之條件例如為：-55℃(或-40℃)~125℃之範圍，2000個週期。此時，於本實施形態之半導體裝置1中，將熱應力相對較大之半導體裝置1之安裝面之外周側的焊盤構造設定為焊盤上通孔構造，藉此能遊刃有餘地應對溫度週期試驗之溫度環境。即，於本實施形態1之半導體裝置1中，能抑制或防止半導體裝置1之安裝面之外周側之焊料球BE之裂痕，故而能提高半導體裝置1之焊料球BE與母板MCB之焊盤MLD之接合強度。因此，能提高半導體裝置1之良率。 又，於本實施形態中，如上所述半導體裝置1之安裝面之焊盤LD1與焊盤LD2之間、及焊盤LD2與焊盤LD3之間空開有間隔。因此，於母板MCB中，在和半導體裝置1之焊盤LD1與焊盤LD2之間隔、及焊盤LD2與焊盤LD3之間隔對向之區域(位置)，能引出與母板MCB之焊盤MLD連接之配線部WD。因此，能提高母板MCB側之配線之牽引自由度。此處，於母板MCB中，在和半導體裝置1之焊盤LD1與焊盤LD2之間、及焊盤LD2與焊盤LD3之間對向之區域(位置)，配置有與母板MCB之上下表面正交之通孔MTH、及形成於其內部之通孔配線MWT。 此處，本實施形態1之構成例如亦可應用於以單片塑模方式製造出之半導體裝置。但，如圖30所示，於單片塑模方式之情形時，若樹脂密封體MD0未形成至半導體裝置1之配線基板WCB之安裝面內之外側的焊料球BE為止，則與以MAP塑模方式製造出之半導體裝置相比，於溫度週期試驗時等施加至配線基板WCB之外周側之應力更小。於該圖30之以單片塑模方式製造出之半導體裝置之情形時，即便熱應力施加至配線基板WCB之外周側，對於該熱應力而言亦有如箭頭P1所示之遁所。與此相對地，於圖31所示之以MAP塑模方式製造出之半導體裝置1中，配線基板WCB之晶片搭載面之整個區域被樹脂密封體MD覆蓋，故而對熱應力之散逸性較小，導致熱應力集中於焊料球BE部分。因此，本實施形態1之構成雖亦可應用於以單片塑模方式製造之半導體裝置，但於以MAP塑模方式製造之半導體裝置1中尤其能發揮效果。 又，本實施形態1之構成例如亦可應用於LGA(Land Grid Array)封裝構造之半導體裝置。於LGA中，焊盤LD之表面被薄於焊料球之焊料材覆蓋。惟焊料球之接合不良之問題於BGA封裝構造之半導體裝置中最為嚴重。因此，本實施形態1之構成雖亦可應用於LGA封裝構造之半導體裝置，但於BGA封裝構造之半導體裝置中尤其能發揮效果。 (實施形態2) 圖32係對圖6之半導體裝置之安裝面顯示周邊區域、第1中央區域及第2中央區域之俯視圖，圖33係圖32之VIII-VIII線之剖視圖，圖34係圖33之半導體裝置之主要部分放大剖視圖，圖35係圖32之半導體裝置之配線基板之晶片搭載面的主要部分放大俯視圖。 於本實施形態2中，如圖32及圖33所示，在配線之佈局設計上，將配線基板WCB之安裝面分為周邊區域(第1區域)PA、其內側之第1中央區域(第2區域)CA1、及其更內側之第2中央區域(第3區域)CA2。再者，於圖32中，亦透視示出了配置於配線基板WCB之安裝面之晶片CHP及複數根引線LA。又，於圖32中，為使圖式容易看懂，對周邊區域PA、第1中央區域CA1及第2中央區域CA2標附有影線。又，周邊區域PA與上述實施形態1中所說明者相同，故而省略說明。 第1中央區域CA1係配置NSMD構造且連接引出用之配線部WB之焊盤LD2的區域，且係以被周邊區域PA包圍之狀態配置於較周邊區域PA靠內側。第1中央區域CA1配置於周邊區域PA與第2中央區域CA2之間。配線基板WCB之晶片搭載面內之複數根引線LA配置於透視俯視下與第1中央區域CA1重疊之位置。即，配置於配線基板WCB之晶片搭載面之複數根引線LA與配置於配線基板WCB之安裝面之複數個焊盤LD2在透視俯視下重疊。配置於該第1中央區域CA1之焊盤之構造成為圖16~圖18各者之左側所例示之構造。 再者，於第1中央區域CA1與周邊區域PA之間配置有空閒區域FA1，該空閒區域FA1及其間隔Fd1與上述實施形態1之空閒區域FA及該間隔Fd相同，故而省略說明。又，焊盤LD1、LD2中相互配置於最近位置之焊盤(第1基準焊盤、第2基準焊盤)LD1、LD2之間隔Dsd(參照圖14)亦與上述實施形態1相同，故而省略說明。又，第1中央區域CA1之外周位置之規定與上述實施形態1之中央區域CA之外周位置之規定相同，故而省略說明。 第2中央區域CA2係以被第1中央區域CA1包圍之狀態配置於較第1中央區域CA1靠內側。該第2中央區域CA2係以較晶片CHP之平面面積稍大且在透視俯視下內包晶片CHP之狀態配置。配線基板WCB之晶片搭載面內之複數根引線LA在透視俯視下不與第2中央區域CA2重疊。即，配置於配線基板WCB之晶片搭載面之複數根引線LA與配置於配線基板WCB之安裝面之第2中央區域CA2內之複數個焊盤(第3焊盤)LD4在透視俯視下不重疊。因此，配置於第2中央區域CA2之焊盤LD4可為NSMD構造且焊盤上通孔構造、NSMD構造且與引出用之配線部WB連接之焊盤構造，或該等兩種構造。此處，如圖34所示，配置於第2中央區域CA2之焊盤LD4例如為NSMD構造且焊盤上通孔構造。 即，於阻焊層SR2，形成有直徑大於焊盤LD4且內包焊盤LD4之開口部(第3開口部)KB3(KB)。因於焊盤LD4未連接引出用之配線部WB，故焊盤LD4之上表面及整個側面自開口部KB3露出。又，該焊盤LD4經由形成於通孔(第3貫通孔)TH3(TH)內之通孔配線(第3通孔配線)WT3(WT)，而與形成於基材SB之晶片搭載面之通孔焊盤TLA電性連接。再者，焊盤LD4之具體構造與圖16~圖18各自之右側所例示之構造相同。又，開口部KB3之直徑與開口部KB(KB1、KB2)相同。又，通孔TH3之直徑與通孔TH(H1、TH2)相同。 於此種本實施形態2中，除上述實施形態1中所獲得之效果以外亦能獲得以下效果。即，藉由將配置於晶片CHP之正下方之焊盤上通孔構造之焊盤LD4及通孔配線WT3用作信號配線，能縮短信號配線之配線長度，故而能提高半導體裝置1之動作速度。又，亦可將配置於晶片CHP之正下方之焊盤上通孔構造之焊盤LD4及通孔配線WT3用作電源配線(高電位側之電源配線及基準電位側之電源(接地(GND)，例如，0 V)配線)。藉此，能縮短電源配線之配線長度，故而能對晶片CHP之積體電路供給穩定之電源電位。因此，能提高半導體裝置1之動作可靠性。進而，藉由使配置於晶片CHP之正下方之通孔配線WT3之構造為圖18所示之金屬填充型構造，能提高於半導體裝置1之動作時晶片CHP上所產生之熱之放散性，故而能提高半導體裝置1之動作可靠性。 又，於該第2中央區域CA2與第1中央區域CA1之間亦配置有空閒區域FA2。該空閒區域FA2之間隔(第4間隔)Fd2與上述實施形態1之空閒區域FA之間隔Fd相同，故而省略說明。第1中央區域CA1之焊盤LD2、及第2中央區域CA2之焊盤LD4中相互配置於最近位置之焊盤(第3基準焊盤、第4基準焊盤)LD2、LD4之間隔(第2間隔)與上述實施形態1中所說明之焊盤LD1、LD2之間隔Dsd(參照圖14)相同，故而省略說明。 此處，參照圖35對第1中央區域CA之內周位置(範圍設定)進行說明。再者，於圖35中，為使圖式容易看懂，對阻焊層SR1標附有影線。 與上述同樣地，可認為能將焊盤上通孔構造之焊盤配置於較引線LA2(LA)靠內側(配線基板WCB之中央側：圖35之左側)。但，實際上，因較引線LA2靠內側之配線部WA亦係以密集之狀態配置，故若於該配線部WA之密集區域以透視俯視下重疊之狀態配置焊盤上通孔構造之焊盤，則與引線LA之配置區域同樣地，難以實施配線基板WCB之配線之牽引。 因此，於本實施形態2中，將第1中央區域CA1之內周側擴展至較引線LA2靠內側之配線部WA之配置區域之一部分為止。即，將第1中央區域CA1之內周位置設定為自晶片CHP之中心位置X0至引線LA2之最內側端之位置X5為止之長度Rc4減去長度Rc5所達之位置X6。該長度Rc5例如大於等於焊盤LD(LD1~LD4)之直徑。該長度Rc5之條件可為與上述實施形態1之間隔Fd中所說明者相同之長度之條件。藉由如此設定，能使較引線LA2靠內側之配線部WA之密集區域亦成為NSMD構造且與引出用之配線部WB連接之焊盤LD2之配置區域。因此，能容易地實施配線基板WCB之配線之牽引。 另一方面，於第2中央區域CA2配置焊盤上通孔構造之焊盤LD4，故而根據與上述相同之理由，若第2中央區域CA2進入配線基板WCB之晶片搭載面之配線部WA之密集區域，則難以實施配線基板WCB之配線之牽引。 因此，於本實施形態2中，規定要將第2中央區域CA2之外周配置於第1中央區域CA1之內周之自位置X6隔開上述間隔Fd2之位置X7。即，將第2中央區域CA2設定於自晶片CHP之中心位置X0至第1中央區域CA1之內周之位置X6為止之長度Rc6減去間隔Fd2所達之位置X7。藉由如此設定，焊盤上通孔構造之焊盤LD4不會被配置於引線LA2之內側之配線部WA之密集區域，故而能容易地實施配線基板WCB之配線之牽引。再者，上述例中，於設定第1中央區域CA1及第2中央區域CA2之邊界(外周及內周)位置時，係以晶片CHP之中心為基準，但並不限定於此。例如，亦可將配線基板WCB之中心之位置、配線基板WCB之外周之位置、或者既已決定之周邊區域PA、第1中央區域CA1或第2中央區域CA2之邊界位置作為基準。 以上，對本發明人所完成之發明基於其實施形態具體進行了說明，但本發明並不限定於上述實施形態，當然可於不脫離其主旨之範圍內進行各種變更。
1‧‧‧半導體裝置
A1‧‧‧區域
A2‧‧‧區域
BE‧‧‧焊料球(焊料凸塊、外部端子、突起電極)
BK‧‧‧下模具
BW‧‧‧導線
C1‧‧‧吸嘴
C2‧‧‧毛細管
CA‧‧‧中央區域
CA1‧‧‧第1中央區域
CA2‧‧‧第2中央區域
CHP‧‧‧晶片
DB‧‧‧黏晶材
Dd‧‧‧間距
Dd1‧‧‧間距
Dd2‧‧‧間距
DFM‧‧‧切晶框架
Dp‧‧‧間距
Dp1‧‧‧間距
Dp2‧‧‧間距
DS‧‧‧切晶刀
Dsd‧‧‧間隔(第1間隔)
DT‧‧‧切晶帶
FA‧‧‧空閒區域
FA1‧‧‧空閒區域
FA2‧‧‧空閒區域
Fd‧‧‧間隔
Fd1‧‧‧間隔
Fd2‧‧‧間隔
Fi‧‧‧絕緣膜
G‧‧‧研磨機
IF‧‧‧絕緣層
KA‧‧‧開口部
KB‧‧‧開口部
KB1‧‧‧開口部
KB2‧‧‧開口部
KB3‧‧‧開口部
KC‧‧‧開口部
LA‧‧‧引線(接合指件、接合引線)
LA1‧‧‧引線
LA2‧‧‧引線
LD‧‧‧焊盤(凸塊焊盤、焊墊、端子)
Ld‧‧‧最小間隔
LD1‧‧‧焊盤(凸塊焊盤、焊墊、端子)
LD2‧‧‧焊盤(凸塊焊盤、焊墊、端子)
LD3‧‧‧焊盤(凸塊焊盤、焊墊、端子)
LD4‧‧‧焊盤(凸塊焊盤、焊墊、端子)
Lp‧‧‧最小間距
Lw‧‧‧寬度
M‧‧‧樹脂
MCB‧‧‧母板
MD‧‧‧樹脂密封體
MD0‧‧‧樹脂密封體
MLD‧‧‧焊盤
MSK‧‧‧金屬遮罩
MTH‧‧‧通孔
MWT‧‧‧通孔配線
P1‧‧‧箭頭
PA‧‧‧周邊區域
PD‧‧‧焊墊(電極、電極墊、端子)
PT‧‧‧保護帶
Rc1‧‧‧長度
Rc2‧‧‧長度
Rc3‧‧‧長度
Rc4‧‧‧長度
Rc5‧‧‧長度
Rc6‧‧‧長度
S1‧‧‧刮漿板
SB‧‧‧基材
SP‧‧‧焊料膏
SR1‧‧‧阻焊層
SR2‧‧‧阻焊層
SR3‧‧‧阻焊層
TH‧‧‧通孔
TH1‧‧‧通孔
TH2‧‧‧通孔
TH3‧‧‧通孔
TLA‧‧‧通孔焊盤
TLB‧‧‧通孔焊盤
UK‧‧‧上模具
WA‧‧‧配線部
WB‧‧‧配線部
WCB‧‧‧配線基板
WD‧‧‧配線部
WF‧‧‧半導體晶圓
WI‧‧‧內層配線
WT‧‧‧通孔配線
WT1‧‧‧通孔配線
WT2‧‧‧通孔配線
WT3‧‧‧通孔配線
X0‧‧‧位置
X1‧‧‧位置
X2‧‧‧位置
X3‧‧‧位置
X4‧‧‧位置
X5‧‧‧位置
X6‧‧‧位置
X7‧‧‧位置
圖1係實施形態1之半導體裝置之安裝面之俯視圖。 圖2係圖1之I-I線之剖視圖。 圖3係圖2之以虛線包圍之區域A1之放大剖視圖。 圖4係構成圖1之半導體裝置之配線基板之晶片搭載面的主要部分放大俯視圖。 圖5係配置於圖4之晶片搭載面之複數根引線之放大俯視圖。 圖6係圖1之半導體裝置之安裝面之將焊料球除去後所示的俯視圖。 圖7係圖6之以虛線包圍之區域A2之放大俯視圖。 圖8中，左圖係SMD構造之焊盤之俯視圖，右圖係圖8之左圖之II-II線之局部剖視圖。 圖9中，左圖係NSMD構造之焊盤之俯視圖，右圖係圖9之左圖之III-III線之局部剖視圖。 圖10中，左圖係NSMD構造且焊盤上通孔構造(焊盤上導通孔構造)之焊盤之俯視圖，右圖係圖10之左圖之IV-IV線之局部剖視圖。 圖11係將配線基板之晶片搭載面之引線與配線基板之安裝面之焊盤重疊所示的局部俯視圖。 圖12係對圖6之半導體裝置之安裝面表示周邊區域及中央區域之俯視圖。 圖13係圖12之V-V線之剖視圖。 圖14係圖12之半導體裝置之配線基板之安裝面的主要部分放大俯視圖。 圖15係圖12之半導體裝置之配線基板之晶片搭載面的主要部分放大俯視圖。 圖16中，左圖係配置於圖1之半導體裝置之安裝面之中央區域的焊盤之主要部分俯視圖，右圖係配置於圖1之半導體裝置之安裝面之周邊區域的焊盤之主要部分俯視圖。 圖17中，左圖係圖16之左圖之VI-VI線之剖視圖，右圖係圖16之右圖之VII-VII線之剖視圖。 圖18中，左圖係通孔配線之變化例且相當於圖16之左圖之VI-VI線之部位的剖視圖，右圖係通孔配線之變化例且相當於圖16之右圖之VII-VII線之部位的剖視圖。 圖19係表示圖1之半導體裝置之製造步驟之步驟圖。 圖20係圖1之半導體裝置之製造步驟之背面研磨步驟中的晶圓之剖視圖。 圖21係圖20之步驟後之切晶步驟中的晶圓之剖視圖。 圖22係圖21之步驟後之黏晶步驟中的晶片及配線基板之剖視圖。 圖23係圖22之步驟後之導線接合步驟中的晶片及配線基板之剖視圖。 圖24係圖23之步驟後之封裝塑模步驟中的半導體裝置之剖視圖。 圖25係圖24之步驟後之焊料印刷步驟中的半導體裝置之剖視圖。 圖26係圖25之步驟後之半導體裝置之剖視圖。 圖27係圖26之步驟後之回焊步驟後的半導體裝置之剖視圖。 圖28係圖27之步驟後之封裝切割步驟中的半導體裝置之剖視圖。 圖29係圖1之半導體裝置及搭載有半導體裝置之母板之主要部分剖視圖。 圖30係以單片塑模方式製造出之半導體裝置及搭載有半導體裝置之母板之一例之主要部分剖視圖。 圖31係圖1之半導體裝置及搭載有半導體裝置之母板之主要部分剖視圖。 圖32係對圖6之半導體裝置之安裝面表示周邊區域、第1中央區域及第2中央區域之俯視圖。 圖33係圖32之VIII-VIII線之剖視圖。 圖34係圖33之半導體裝置之主要部分放大剖視圖。 圖35係圖32之半導體裝置之配線基板之晶片搭載面的主要部分放大俯視圖。

Claims (18)

  1. 一種半導體裝置，其具備： 配線基板，其具備：基材，其具有第1面、及與上述第1面為相反側之第2面；複數根引線，其等配置於上述基材之上述第1面；第1絕緣膜，其以使上述複數根引線露出之狀態，設置於上述基材之上述第1面；複數個焊盤，其等配置於上述基材之上述第2面；第2絕緣膜，其以使上述複數個焊盤露出之狀態，設置於上述基材之上述第2面；複數個貫通孔，其等分別貫通上述基材之上述第1面與上述第2面之間；及複數個通孔配線，其等形成於上述複數個貫通孔各者之內部，將上述複數根引線與上述複數個焊盤分別電性連接； 半導體晶片，其具有第3面、形成於上述第3面之複數個電極、及與上述第3面為相反側之第4面，且以將上述第4面朝向上述基材之上述第1面之狀態，搭載於上述配線基板之上述第1面上； 複數根導線，其等將上述半導體晶片之上述複數個電極與上述配線基板之上述複數根引線分別電性連接； 樹脂密封體，其將上述半導體晶片及上述複數根導線密封；以及 外部端子，其設置於上述複數個焊盤之各者；且 上述複數個焊盤具有： 複數個第1焊盤，其等於透視俯視下不與上述複數根引線重疊，且沿著上述基材之緣而配置； 複數個第2焊盤，其等於俯視下位於較上述複數個第1焊盤靠內側，且於透視俯視下與上述複數根引線重疊，且沿著上述基材之上述緣而配置； 於上述複數個第2焊盤之各者，連接有形成於上述基材之上述第2面之配線部， 上述複數個第2焊盤具有位於最靠近上述複數個第1焊盤中之第1基準焊盤之第2基準焊盤， 上述第1基準焊盤與上述第2基準焊盤之第1間隔大於上述複數個第1焊盤中沿著上述基材之上述緣相鄰之2個焊盤彼此之間隔； 上述複數個通孔配線具有： 第1通孔配線，其與上述第1焊盤電性連接； 第2通孔配線，其經由上述配線部而與上述第2焊盤電性連接；且 上述複數個貫通孔中其內部形成有上述第1通孔配線之第1貫通孔在俯視下與上述第1焊盤重疊， 上述複數個貫通孔中其內部形成有上述第2通孔配線之第2貫通孔在俯視下不與上述第2焊盤重疊， 於上述第2絕緣膜，形成有以俯視下內包上述複數個焊盤各者之狀態露出之複數個開口部， 上述複數個開口部具有： 第1開口部，其使上述第1焊盤露出；及 第2開口部，其使上述第2焊盤及上述配線部之一部分露出。
  2. 如請求項1之半導體裝置，其中 上述焊盤之直徑大於上述複數根引線之相鄰間隔。
  3. 如請求項1之半導體裝置，其中 上述第1焊盤及上述第2焊盤遍複數行排列。
  4. 如請求項1之半導體裝置，其中 上述樹脂密封體覆蓋上述基材之上述第1面之整個區域。
  5. 如請求項1之半導體裝置，其中 上述第1間隔大於上述焊盤之直徑。
  6. 如請求項1之半導體裝置，其中 上述第1間隔大於上述複數個第1焊盤中沿著上述基材之上述緣相鄰之2個焊盤彼此之相鄰間距。
  7. 如請求項1之半導體裝置，其中 上述複數個焊盤包含複數個第3焊盤，該等第3焊盤沿著上述基材之上述緣配置於被上述複數個第2焊盤之配置區域包圍之區域且於透視俯視下不與上述複數根引線重疊之位置； 上述複數個第3焊盤包含位於最靠近上述複數個第2焊盤中之第3基準焊盤之第4基準焊盤， 上述第3基準焊盤與上述第4基準焊盤之第2間隔大於上述複數個第1焊盤中沿著上述基材之上述緣相鄰之2個焊盤彼此之間隔。
  8. 如請求項7之半導體裝置，其中 上述複數個第3焊盤透視在俯視下與上述半導體晶片重疊。
  9. 如請求項7之半導體裝置，其中 上述複數個通孔配線： 具有與上述第3焊盤電性連接之第3通孔配線，且 上述複數個貫通孔中其內部形成有上述第3通孔配線之第3貫通孔係於俯視下與上述第3焊盤重疊， 上述第2絕緣膜之上述複數個開口部具有以俯視下內包上述第3焊盤之狀態露出之第3開口部。
  10. 一種半導體裝置，其具備： 配線基板，其具備：基材，其具有第1面、及與上述第1面為相反側之第2面；複數根引線，其等配置於上述基材之上述第1面；第1絕緣膜，其以使上述複數根引線露出之狀態，設置於上述基材之上述第1面；複數個焊盤，其等配置於上述基材之上述第2面；第2絕緣膜，其以使上述複數個焊盤露出之狀態，設置於上述基材之上述第2面；複數個貫通孔，其等分別貫通上述基材之上述第1面與上述第2面之間；及複數個通孔配線，其等形成於上述複數個貫通孔各者之內部，將上述複數根引線與上述複數個焊盤分別電性連接； 半導體晶片，其具有第3面、形成於上述第3面之複數個電極、及與上述第3面為相反側之第4面，且搭載於上述配線基板之上述第1面上； 複數根導線，其等將上述半導體晶片之上述複數個電極與上述配線基板之上述複數根引線分別電性連接； 樹脂密封體，其將上述半導體晶片及上述複數根導線密封；以及 外部端子，其設置於上述複數個焊盤之各者；且 上述複數根引線於透視俯視下不與上述基材之上述第2面內之外周側之第1區域重疊，於透視俯視下與較上述第1區域靠內側之第2區域重疊， 上述複數個焊盤具有： 複數個第1焊盤，其等沿著上述基材之緣配置於上述第1區域內；及 複數個第2焊盤，其等沿著上述基材之上述緣配置於上述第2區域內； 於上述複數個第2焊盤之各者，連接有形成於上述基材之上述第2面之配線部， 上述第1區域與上述第2區域最靠近之第3間隔大於上述複數個第1焊盤中沿著上述基材之上述緣相鄰之2個焊盤彼此之間隔； 上述複數個通孔配線具有： 第1通孔配線，其與上述第1焊盤電性連接； 第2通孔配線，其經由上述配線部而與上述第2焊盤電性連接；且 上述複數個貫通孔中其內部形成有上述第1通孔配線之第1貫通孔在俯視下與上述第1焊盤重疊， 上述複數個貫通孔中其內部形成有上述第2通孔配線之第2貫通孔在俯視下不與上述第2焊盤重疊， 於上述第2絕緣膜，形成有以俯視下內包上述複數個焊盤各者之狀態露出之複數個開口部， 上述複數個開口部具有： 第1開口部，其使上述第1焊盤露出；及 第2開口部，其使上述第2焊盤及上述配線部之一部分露出。
  11. 如請求項10之半導體裝置，其中 上述焊盤之直徑大於上述複數根引線之相鄰間隔。
  12. 如請求項10之半導體裝置，其中 上述第1焊盤及上述第2焊盤遍複數行排列。
  13. 如請求項10之半導體裝置，其中 上述樹脂密封體覆蓋上述基材之上述第1面之整個區域。
  14. 如請求項10之半導體裝置，其中 上述第3間隔大於上述焊盤之直徑。
  15. 如請求項10之半導體裝置，其中 上述第3間隔大於上述複數個第1焊盤中沿著上述基材之上述緣相鄰之2個焊盤彼此之間隔。
  16. 如請求項10之半導體裝置，其中 上述複數個焊盤包含複數個第3焊盤，該等第3焊盤沿著上述基材之上述緣配置於較上述第2區域靠內側且於透視俯視下不與上述複數根引線重疊之第3區域， 上述第2區域與上述第3區域之最近之第4間隔大於上述複數個第1焊盤中沿著上述基材之上述緣相鄰之2個焊盤彼此之間隔。
  17. 如請求項16之半導體裝置，其中 上述複數個第3焊盤於透視俯視下與上述半導體晶片重疊。
  18. 如請求項16之半導體裝置，其中 上述複數個通孔配線： 具有與上述第3焊盤電性連接之第3通孔配線，且 上述複數個貫通孔中其內部形成有上述第3通孔配線之第3貫通孔係於俯視下與上述第3焊盤重疊， 上述第2絕緣膜之上述複數個開口部具有以俯視下內包上述第3焊盤之狀態露出之第3開口部。
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CN108807289A (zh) 2018-11-13
US20180315691A1 (en) 2018-11-01
JP2018186197A (ja) 2018-11-22

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