TWI683357B - 半導體裝置之製造方法 - Google Patents

半導體裝置之製造方法 Download PDF

Info

Publication number
TWI683357B
TWI683357B TW107129787A TW107129787A TWI683357B TW I683357 B TWI683357 B TW I683357B TW 107129787 A TW107129787 A TW 107129787A TW 107129787 A TW107129787 A TW 107129787A TW I683357 B TWI683357 B TW I683357B
Authority
TW
Taiwan
Prior art keywords
resin film
manufacturing
semiconductor device
photosensitive resin
electrode
Prior art date
Application number
TW107129787A
Other languages
English (en)
Other versions
TW202004870A (zh
Inventor
前田和弘
Original Assignee
日商三菱電機股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日商三菱電機股份有限公司 filed Critical 日商三菱電機股份有限公司
Publication of TW202004870A publication Critical patent/TW202004870A/zh
Application granted granted Critical
Publication of TWI683357B publication Critical patent/TWI683357B/zh

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568Temporary substrate used as encapsulation process aid
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28114Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/7682Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895Local interconnects; Local pads, as exemplified by patent document EP0896365
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/315Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the encapsulation having a cavity
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561Batch processing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1005Formation and after-treatment of dielectrics
    • H01L2221/101Forming openings in dielectrics
    • H01L2221/1015Forming openings in dielectrics for dual damascene structures
    • H01L2221/1031Dual damascene by forming vias in the via-level dielectric prior to deposition of the trench-level dielectric

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Dicing (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

將覆蓋半導體元件(5)及半導體基板(1)的切割線(7)的樹脂膜(8)形成在半導體基板(1)的主面之上,無須去除切割線(7)之上的樹脂膜(8),而去除第1電極(2)周圍的樹脂膜(8),且去除第2電極(3、4)之上的樹脂膜(8)而形成第1接觸孔(9)。將樹脂薄膜(11)黏貼在樹脂膜(8)的上面而在第1電極(2)的周圍形成中空構造(12)。將樹脂薄膜(11)圖案化,同時形成與第1接觸孔(9)相連的第2接觸孔(13)與切割線(7)的上方的第1開口(14)。在形成第1開口(14)之後,沿著切割線(7)切割半導體基板(1)。

Description

半導體裝置之製造方法
本發明係關於半導體裝置之製造方法。
為實現半導體裝置的高積體化與小型化,使用一種反覆積層樹脂膜與金屬配線的多層配線構造。但是,因樹脂膜,寄生電容會增加,且半導體元件的電特性會劣化。尤其在具有Y型或T型閘極電極的半導體裝置中,係在閘極電極的帽簷之下被填充樹脂,寄生電容會增加,高頻特性的增益會劣化。相對於此,已提出一種方法係將覆蓋半導體元件的樹脂膜圖案化而將閘極電極周圍的樹脂膜去除,且將樹脂薄膜黏貼在樹脂膜的上面,藉此在閘極電極的周圍形成中空構造(參照例如專利文獻1)。藉由形成中空構造,與填充樹脂膜的情形相比,特性尤其提升。
〔先前技術文獻〕
〔專利文獻〕
專利文獻1:日本特開2016-39319號公報
以往在將樹脂膜圖案化時,亦去除切割線之上的樹脂膜。因此, 樹脂薄膜與樹脂膜的接觸面積減小,因此密接力減弱。此外,樹脂薄膜係被支持在支持薄膜,在將樹脂薄膜黏貼在樹脂膜之後,必須將支持薄膜從樹脂薄膜剝下。但是,樹脂薄膜與支持薄膜的密接力比樹脂薄膜與樹脂膜的密接力更強,因此當將支持薄膜從樹脂薄膜剝下時,會有發生樹脂薄膜浮起或剝落的情形。此外,亦有所黏貼的樹脂薄膜埋入至中空部的情形。結果,有製品良率降低的問題。
本發明係用以解決如上所述之課題而完成者,其目的在獲得可使製品良率提升的半導體裝置之製造方法。
本發明之半導體裝置之製造方法之特徵為:包括:在半導體基板的主面形成具有第1及第2電極的半導體元件的步驟;在前述半導體基板的前述主面之上,形成覆蓋前述半導體元件及前述半導體基板的切割線的樹脂膜,無須去除前述切割線之上的前述樹脂膜,而去除前述第1電極周圍的前述樹脂膜,且去除前述第2電極之上的前述樹脂膜而形成第1接觸孔的步驟;將一邊由前述第1及第2電極間離一邊覆蓋前述第1及第2電極的上方的感光性樹脂薄膜黏貼在前述樹脂膜的上面,而在前述第1電極的周圍形成中空構造的步驟;將前述感光性樹脂薄膜進行曝光及顯影,同時形成與前述第1接觸孔相連的第2接觸孔與前述切割線的上方的第1開口的步驟;形成透過前述第1及第2接觸孔而與前述第2電極相連接的配線的步驟;及在形成前述第1開口之後,沿著前述切割線切割前述半導體基板的步驟。
在本發明中,當將樹脂膜圖案化時,不去除切割線之上的樹脂膜。因此,樹脂薄膜與樹脂膜的接觸面積增加,因此密接力提升,可防止樹脂薄膜浮起及剝落。此外,樹脂薄膜被牢固地支持在樹脂膜,因此亦可防止埋入。結果,可使製品良率提升。
1‧‧‧半導體基板
2‧‧‧閘極電極(第1電極)
3‧‧‧源極電極(第2電極)
4‧‧‧汲極電極(第2電極)
5‧‧‧半導體元件
6‧‧‧絕緣膜
7‧‧‧切割線
8‧‧‧感光性樹脂膜(樹脂膜)
9‧‧‧第1接觸孔
10‧‧‧支持薄膜
11‧‧‧感光性樹脂薄膜(樹脂薄膜)
12‧‧‧中空構造
13‧‧‧第2接觸孔
14‧‧‧第1開口
15‧‧‧絕緣膜
16‧‧‧阻劑
17‧‧‧第2開口
18‧‧‧配線
19‧‧‧非感光性樹脂薄膜
〔圖1〕係顯示實施形態1之半導體裝置之製造方法的剖面圖。
〔圖2〕係顯示實施形態1之半導體裝置之製造方法的剖面圖。
〔圖3〕係顯示實施形態1之半導體裝置之製造方法的剖面圖。
〔圖4〕係顯示實施形態1之半導體裝置之製造方法的剖面圖。
〔圖5〕係顯示實施形態1之半導體裝置之製造方法的剖面圖。
〔圖6〕係顯示實施形態1之半導體裝置之製造方法的剖面圖。
〔圖7〕係顯示實施形態1之半導體裝置之製造方法的剖面圖。
〔圖8〕係顯示實施形態1之半導體裝置之製造方法的剖面圖。
〔圖9〕係顯示實施形態1之半導體裝置之製造方法的剖面圖。
〔圖10〕係顯示比較例之半導體裝置之製造方法的剖面圖。
〔圖11〕係顯示比較例之半導體裝置之製造方法的剖面圖。
〔圖12〕係顯示比較例之半導體裝置之製造方法的剖面圖。
〔圖13〕係顯示實施形態2之半導體裝置之製造方法的剖面圖。
〔圖14〕係顯示實施形態2之半導體裝置之製造方法的剖面圖。
〔圖15〕係顯示實施形態3之半導體裝置之製造方法的剖面圖。
〔圖16〕係顯示實施形態3之半導體裝置之製造方法的剖面圖。
〔圖17〕係顯示實施形態3之半導體裝置之製造方法的剖面圖。
〔圖18〕係顯示實施形態3之半導體裝置之製造方法的剖面圖。
參照圖示,說明實施形態之半導體裝置之製造方法。對於相同或 對應的構成要素係有標註相同符號,且省略反覆說明的情形。
實施形態1.
圖1至圖9係顯示實施形態1之半導體裝置之製造方法的剖面圖。首先,如圖1所示,在半導體基板1的主面形成具有閘極電極2、源極電極3及汲極電極4的半導體元件5。以耐濕性高的絕緣膜6覆蓋半導體元件5。將源極電極3、汲極電極4及切割線7上的絕緣膜6形成開口。接著,將覆蓋半導體元件5及半導體基板1的切割線7的感光性樹脂膜8,以旋轉塗佈機塗佈在半導體基板1的主面之上。將感光性樹脂膜8藉由曝光及顯影進行圖案化,無須去除切割線7之上的感光性樹脂膜8,而去除閘極電極2周圍的感光性樹脂膜8,去除源極電極3及汲極電極4之上的感光性樹脂膜8而形成第1接觸孔9。之後,進行熱硬化處理而將感光性樹脂膜8硬化。
接著,如圖2所示,使用層壓法或STP法,將被支持在支持薄膜10的感光性樹脂薄膜11黏貼在感光性樹脂膜8的上面。感光性樹脂薄膜11係一邊由閘極電極2、源極電極3及汲極電極4間離,一邊覆蓋閘極電極2、源極電極3及汲極電極4的上方。接著,如圖3所示,將支持薄膜10從感光性樹脂薄膜11剝下。藉此,如圖4所示,在閘極電極2的周圍形成中空構造12。
接著,如圖5所示,將感光性樹脂薄膜11藉由曝光及顯影進行圖案化,同時形成與第1接觸孔9相連的第2接觸孔13與切割線7的上方的第1開口14。之後,進行熱硬化處理而將感光性樹脂薄膜11硬化。
接著,如圖6所示,全面依序形成絕緣膜15及阻劑16,在切割線7的上方,將阻劑16形成開口。接著,進行使用阻劑16作為遮罩的乾式蝕刻。藉此,如圖7所示,將切割線7之上的絕緣膜15及感光性樹脂膜8去除而形成第2開口17。藉由預先去除切割線7的上方的感光性樹脂薄膜11,以乾式蝕刻去除的膜的膜厚會變薄,因此乾式蝕刻變得較為容易。之後,將作為遮罩所使用的絕緣膜15及阻劑16去除。
接著,如圖8所示,藉由鍍敷或蒸鍍法,形成透過第1及第2接觸孔9、13而與源極電極3及汲極電極4相連接的配線18。接著,使用切割刀19,沿著切割線7切割半導體基板1。結果,如圖9所示,按各個晶片予以間離。
接著,與比較例相比較,說明本實施形態的效果。圖10至圖12係顯示比較例之半導體裝置之製造方法的剖面圖。在比較例中,如圖10所示,將感光性樹脂膜8圖案化時,將切割線7之上的感光性樹脂膜8去除。接著,如圖11所示,將感光性樹脂薄膜11黏貼在感光性樹脂膜8的上面。接著,如圖12所示,將感光性樹脂薄膜11進行曝光及顯影。
在比較例中,藉由去除切割線7之上的感光性樹脂膜8,感光性樹脂薄膜11與感光性樹脂膜8的接觸面積減小,因此密接力減弱。因此,當將支持薄膜10從感光性樹脂薄膜11剝下時,有發生感光性樹脂薄膜11浮起或剝落的情形。此外,亦有所黏貼的感光性樹脂薄膜11埋入至中空部的情形。結果,有製品良率降低的問題。
相對於此,在本實施形態中,將感光性樹脂膜8圖案化時,不去除切割線7之上的感光性樹脂膜8。因此,感光性樹脂薄膜11與感光性樹脂膜8的接觸面積增加,因此密接力提升,可防止感光性樹脂薄膜11浮起及剝落。此外,感光性樹脂薄膜11牢固地被支持在感光性樹脂膜8,因此亦可防止埋入。結果,可使製品良率提升。
此外,若在將被支持在支持薄膜10的感光性樹脂薄膜11黏貼在感光性樹脂膜8的上面之後,將支持薄膜10從感光性樹脂薄膜11剝下時,容易發生感光性樹脂薄膜11浮起及剝落。在如上所示之情形下,如本實施形態所示,以使感光性樹脂薄膜11與感光性樹脂膜8的密接力提升為尤其有效。
此外,閘極電極2係包含帽簷的Y型或T型的閘極電極,在閘極電極2的帽簷之下亦形成有中空構造12。藉此,寄生電容減少,高頻特性的增益提 升。
此外,形成第1開口14之後,在切割半導體基板1之前,將切割線7之上的感光性樹脂膜8去除而形成第2開口17。藉此,切割變得較為容易。
此外,感光性樹脂薄膜11的第1開口14的端部比感光性樹脂膜8的第2開口17的端部更靠近半導體元件5側。藉此,可防止在切割時切割刀抵碰於感光性樹脂薄膜11的第1開口14的端部。因此,半導體裝置的良率提升。
實施形態2.
圖13及圖14係顯示實施形態2之半導體裝置之製造方法的剖面圖。至圖5的步驟為止,係與實施形態1相同。在本實施形態中,無須將切割線7之上的感光性樹脂膜8以乾式蝕刻進行加工,而如圖13所示,形成透過第1及第2接觸孔9、13而與源極電極3及汲極電極4相連接的配線18。接著,如圖14所示,將切割線7之上的感光性樹脂膜8連同半導體基板1一起切割。藉此,相較於實施形態1,可更加刪減製程數。其他構成及效果係與實施形態1相同。
實施形態3.
圖15至圖18係顯示實施形態3之半導體裝置之製造方法的剖面圖。本實施形態係將實施形態1及2的感光樹脂薄膜11置換成非感光性樹脂薄膜19者。至圖5的步驟為止係與實施形態1相同。接著,如圖15所示,使用層壓法或STP法,將被支持在支持薄膜10的非感光性樹脂薄膜19黏貼在感光性樹脂膜8的上面。非感光性樹脂薄膜19係一邊由閘極電極2、源極電極3及汲極電極4間離,一邊覆蓋閘極電極2、源極電極3及汲極電極4的上方。接著,若將支持薄膜10從非感光性樹脂薄膜19剝下,如圖16所示,在閘極電極2的周圍形成中空構造12。接著,如圖17所示,全面依序形成絕緣膜15及阻劑16,將阻劑16藉由光微影等進行圖案化。藉由進行使用該阻劑16作為遮罩的乾式蝕刻,如圖18所示,將第2接觸孔13及第1開口14形成開口。之後,進行實施形態1或實施形態2任一者的步驟,來製作元 件構造。其他構成及效果係與實施形態1相同。
1‧‧‧半導體基板
2‧‧‧閘極電極(第1電極)
3‧‧‧源極電極(第2電極)
4‧‧‧汲極電極(第2電極)
5‧‧‧半導體元件
6‧‧‧絕緣膜
7‧‧‧切割線
8‧‧‧感光性樹脂膜(樹脂膜)
9‧‧‧第1接觸孔
10‧‧‧支持薄膜
11‧‧‧感光性樹脂薄膜(樹脂薄膜)

Claims (6)

  1. 一種半導體裝置之製造方法,其特徵為包括:在半導體基板的主面形成具有第1及第2電極的半導體元件的步驟;在前述半導體基板的前述主面之上,形成覆蓋前述半導體元件及前述半導體基板的切割線的樹脂膜,無須去除前述切割線之上的前述樹脂膜,而去除前述第1電極周圍的前述樹脂膜,且去除前述第2電極之上的前述樹脂膜而形成第1接觸孔的步驟;將一邊由前述第1及第2電極間離一邊覆蓋前述第1及第2電極的上方的樹脂薄膜黏貼在前述樹脂膜的上面,而在前述第1電極的周圍形成中空構造的步驟;將前述樹脂薄膜圖案化,同時形成與前述第1接觸孔相連的第2接觸孔與前述切割線的上方的第1開口的步驟;形成透過前述第1及第2接觸孔而與前述第2電極相連接的配線的步驟;及在形成前述第1開口之後,沿著前述切割線切割前述半導體基板的步驟。
  2. 如申請專利範圍第1項之半導體裝置之製造方法,其中,在將被支持在支持薄膜的前述樹脂薄膜黏貼在前述樹脂膜的上面之後,將前述支持薄膜從前述樹脂薄膜剝下。
  3. 如申請專利範圍第1或2項之半導體裝置之製造方法,其中,前述第1電極係包含帽簷的Y型或T型閘極電極,在前述閘極電極的前述帽簷之下亦形成有前述中空構造。
  4. 如申請專利範圍第1或2項之半導體裝置之製造方法,其中,另外包括:形成前述第1開口之後,在切割前述半導體基板之前,去除前述切割線之上的前述樹脂膜而形成第2開口的步驟。
  5. 如申請專利範圍第4項之半導體裝置之製造方法,其中,前述第1開口的端部比前述第2開口的端部更接近前述半導體元件側。
  6. 如申請專利範圍第1或2項之半導體裝置之製造方法,其中,將前述切割線之上的前述樹脂膜連同前述半導體基板一起切割。
TW107129787A 2018-05-28 2018-08-27 半導體裝置之製造方法 TWI683357B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
WOPCT/JP2018/020353 2018-05-28
PCT/JP2018/020353 WO2019229802A1 (ja) 2018-05-28 2018-05-28 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
TW202004870A TW202004870A (zh) 2020-01-16
TWI683357B true TWI683357B (zh) 2020-01-21

Family

ID=68697057

Family Applications (1)

Application Number Title Priority Date Filing Date
TW107129787A TWI683357B (zh) 2018-05-28 2018-08-27 半導體裝置之製造方法

Country Status (7)

Country Link
US (1) US11244863B2 (zh)
JP (1) JP6927430B2 (zh)
KR (1) KR102497370B1 (zh)
CN (1) CN112189251B (zh)
DE (1) DE112018007677B4 (zh)
TW (1) TWI683357B (zh)
WO (1) WO2019229802A1 (zh)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05335343A (ja) * 1992-05-27 1993-12-17 Sony Corp 電界効果トランジスタ
JP5335343B2 (ja) 2008-09-18 2013-11-06 株式会社アルバック 付着物の分析方法
CN105374743A (zh) * 2014-08-08 2016-03-02 三菱电机株式会社 半导体装置的制造方法

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004147220A (ja) 2002-10-25 2004-05-20 Toyo Commun Equip Co Ltd Sawチップの構造、その製造方法、表面実装型sawデバイス、及びその製造方法
JP2005150452A (ja) * 2003-11-17 2005-06-09 Fujikura Ltd 半導体パッケージの製造方法
JP3953027B2 (ja) * 2003-12-12 2007-08-01 ソニー株式会社 半導体装置およびその製造方法
JP4413062B2 (ja) 2004-04-13 2010-02-10 シャープ株式会社 パターニングされた膜を有する基板の製造方法
JP2006093367A (ja) * 2004-09-24 2006-04-06 Sanyo Electric Co Ltd 半導体装置の製造方法
JP4607531B2 (ja) 2004-09-29 2011-01-05 カシオマイクロニクス株式会社 半導体装置の製造方法
JP2006278610A (ja) * 2005-03-29 2006-10-12 Sanyo Electric Co Ltd 半導体装置及びその製造方法
US7807506B2 (en) 2006-02-03 2010-10-05 Infineon Technologies Ag Microelectromechanical semiconductor component with cavity structure and method for producing the same
KR20090063983A (ko) * 2007-12-14 2009-06-18 주식회사 코오롱 칩온필름용 적층필름 및 칩온필름의 제조방법
JP4939452B2 (ja) 2008-02-07 2012-05-23 ラピスセミコンダクタ株式会社 半導体装置の製造方法
JP4484934B2 (ja) 2008-02-26 2010-06-16 富士通メディアデバイス株式会社 電子部品及びその製造方法
JP2011014652A (ja) 2009-06-30 2011-01-20 Panasonic Electric Works Co Ltd 機能性デバイスの製造方法および、それにより製造された機能性デバイスを用いた半導体装置の製造方法
JP2013065582A (ja) 2009-12-28 2013-04-11 Fujikura Ltd 半導体ウエハ及び半導体装置並びに半導体装置の製造方法
WO2011145750A1 (ja) 2010-05-20 2011-11-24 日立化成工業株式会社 感光性樹脂組成物、感光性フィルム、リブパターンの形成方法、中空構造とその形成方法及び電子部品
JP5521862B2 (ja) * 2010-07-29 2014-06-18 三菱電機株式会社 半導体装置の製造方法
JP5821429B2 (ja) * 2011-09-01 2015-11-24 三菱電機株式会社 半導体装置及びその製造方法
US9613930B2 (en) * 2013-10-25 2017-04-04 Infineon Technologies Ag Semiconductor device and method for manufacturing a semiconductor device
JP2015106698A (ja) * 2013-12-02 2015-06-08 味の素株式会社 半導体装置の製造方法
TWI657510B (zh) * 2014-10-02 2019-04-21 日商住友電木股份有限公司 半導體裝置之製造方法及半導體裝置
US9748334B1 (en) * 2016-02-18 2017-08-29 International Business Machines Corporation Fabrication of nanomaterial T-gate transistors with charge transfer doping layer

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05335343A (ja) * 1992-05-27 1993-12-17 Sony Corp 電界効果トランジスタ
JP5335343B2 (ja) 2008-09-18 2013-11-06 株式会社アルバック 付着物の分析方法
CN105374743A (zh) * 2014-08-08 2016-03-02 三菱电机株式会社 半导体装置的制造方法

Also Published As

Publication number Publication date
KR20200143481A (ko) 2020-12-23
DE112018007677T5 (de) 2021-03-04
WO2019229802A1 (ja) 2019-12-05
JP6927430B2 (ja) 2021-08-25
DE112018007677B4 (de) 2023-10-12
KR102497370B1 (ko) 2023-02-07
CN112189251A (zh) 2021-01-05
JPWO2019229802A1 (ja) 2021-02-12
CN112189251B (zh) 2023-12-26
US20210066128A1 (en) 2021-03-04
TW202004870A (zh) 2020-01-16
US11244863B2 (en) 2022-02-08

Similar Documents

Publication Publication Date Title
US8748320B2 (en) Connection to first metal layer in thin film transistor process
KR20030020930A (ko) 전자 부품 및 제조 방법
JPH0821559B2 (ja) 半導体集積回路装置の製造方法
JP7134617B2 (ja) 半導体装置及び半導体装置の製造方法
TWI683357B (zh) 半導體裝置之製造方法
TWI631782B (zh) 半導體雷射及其製造方法
JP2004282034A (ja) 半導体装置及びその製造方法
JP2012253182A (ja) 半導体装置及びその製造方法
JP2001176975A (ja) 半導体装置及びその製造方法
JP4277692B2 (ja) 半導体装置の製造方法
JPH11186393A (ja) 半導体素子及びその製造方法
JP2020009823A (ja) 半導体装置及び半導体装置の製造方法
JPS6336548A (ja) 半導体装置及びその製造方法
JPH0661233A (ja) 半導体装置の製造方法
JP6937724B2 (ja) 半導体装置およびその製造方法
JPH07245301A (ja) 半導体装置の製造方法
US10128162B2 (en) Method of manufacturing semiconductor device
JPH06310597A (ja) 半導体装置
JPH10189583A (ja) 半導体装置
JP2005302816A (ja) 半導体装置及びその製造方法
JP2004303784A (ja) 半導体装置の製造方法
JP4984645B2 (ja) 半導体装置の製造方法
JP3718261B2 (ja) 半導体集積回路装置の製造方法
JP2004273769A (ja) 半導体のパッシベーション構造およびその製造方法
JPS63260053A (ja) 半導体装置の製造方法