TWI647330B - 低氧化電漿輔助製程 - Google Patents
低氧化電漿輔助製程 Download PDFInfo
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- TWI647330B TWI647330B TW104111910A TW104111910A TWI647330B TW I647330 B TWI647330 B TW I647330B TW 104111910 A TW104111910 A TW 104111910A TW 104111910 A TW104111910 A TW 104111910A TW I647330 B TWI647330 B TW I647330B
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- 230000008569 process Effects 0.000 title claims abstract description 35
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- RSKFXZJLEFGMQK-UHFFFAOYSA-N 1-n,1-n,1-n',1-n'-tetramethyldecane-1,1-diamine Chemical compound CCCCCCCCCC(N(C)C)N(C)C RSKFXZJLEFGMQK-UHFFFAOYSA-N 0.000 description 1
- BHIMRMREBDUIIB-UHFFFAOYSA-N C(C)N(C)C(CCCCCCCCC)N(CC)C Chemical compound C(C)N(C)C(CCCCCCCCC)N(CC)C BHIMRMREBDUIIB-UHFFFAOYSA-N 0.000 description 1
- IAQUNTUPBIIBGK-UHFFFAOYSA-N C(C)N(CCCCCCCCCC)C.NN Chemical compound C(C)N(CCCCCCCCCC)C.NN IAQUNTUPBIIBGK-UHFFFAOYSA-N 0.000 description 1
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- UOACKFBJUYNSLK-XRKIENNPSA-N Estradiol Cypionate Chemical compound O([C@H]1CC[C@H]2[C@H]3[C@@H](C4=CC=C(O)C=C4CC3)CC[C@@]21C)C(=O)CCC1CCCC1 UOACKFBJUYNSLK-XRKIENNPSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
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- 125000000118 dimethyl group Chemical group [H]C([H])([H])* 0.000 description 1
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- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
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- 150000002430 hydrocarbons Chemical class 0.000 description 1
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- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- XAVHSDMSRKWEFR-UHFFFAOYSA-N n-ethyl-n-methyldecan-1-amine Chemical compound CCCCCCCCCCN(C)CC XAVHSDMSRKWEFR-UHFFFAOYSA-N 0.000 description 1
- 239000007800 oxidant agent Substances 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 125000002924 primary amino group Chemical group [H]N([H])* 0.000 description 1
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- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 229910052724 xenon Inorganic materials 0.000 description 1
Classifications
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- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/455—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
- C23C16/45523—Pulsed gas flow or change of composition over time
- C23C16/45525—Atomic layer deposition [ALD]
- C23C16/45527—Atomic layer deposition [ALD] characterized by the ALD cycle, e.g. different flows or temperatures during half-reactions, unusual pulsing sequence, use of precursor mixtures or auxiliary reactants or activations
- C23C16/45536—Use of plasma, radiation or electromagnetic fields
- C23C16/45538—Plasma being used continuously during the ALD cycle
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- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
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- C23C16/40—Oxides
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- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
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- C23C16/401—Oxides containing silicon
- C23C16/402—Silicon dioxide
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- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
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- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
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- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
本發明係有關一種藉電漿輔助循環製程形成氧化膜之方法,包括:(i)供應一前驅物至一反應空間,其中該空間放置一基板;(ii)於第一時間段施敷一第一射頻功率至該反應空間而不供應一前驅物;以及(iii)於第二時間段施敷一第二射頻功率至該反應空間而不供應該前驅物,其中第一射頻功率係低於第二射頻功率,及/或第一時間段係短於第二時間段。
Description
本發明一般而言係有關一種藉電漿輔助製程如電漿增強式原子層沉積法(plasma-enhanced atomic layer deposition;簡稱PEALD)形成金屬或矽之氧化膜之方法。
於PEALD製程中,取決於應用類型,有問題尚待解決,如底層之氧化作用。常規上,此問題以降低射頻功率處理。然而,當射頻功率降低時,無法取得薄膜所需特性如厚度、均勻度、及濕蝕刻率(wet etch rate)等。
舉例而言,SiO製程需要低射頻功率,其中無需底層3之氧化,係因如圖1A所述,當施敷高射頻功率時,底層3由於氧電漿、離子衝擊、及薄膜沉積期間濺射等影響而氧化。亦即,當SiO薄膜1藉PEALD沉積於底層3上時,其中含有W、TiN、或其他材料,或其為SiN薄膜,構成底層3之材料係於其上部2處由電漿氧化,該電漿包括用於沉積SiO薄膜1之氧化性氣體,從而無法取得所需之裝置特性。
此外,於超精細製程中,例如FinFET製程(內建於SOI基
板上之非平面、雙匣電晶體),如圖1B所示,具高6nm之Si突起圖案4係進行PEALD,如(a)所示。當於高氧化條件7下進行PEALD時,突起圖案4之表面5係經氧化及侵蝕,而SiO薄膜6係藉PEALD沉積,從而減少突起圖案4之尺寸,特別是在垂直方向(例如,突起圖案4之高度減至4nm),如(b)所示。其結果為,圖案尺寸改變,可能無法取得所設計之電子性質。相反地,當於低氧化條件8下進行PEALD時,突起圖案4之表面未明顯氧化,而SiO薄膜6係藉PEALD沉積,從而防止突起圖案4之尺寸減少,特別是在垂直方向(突起圖案4之高度可維持在6nm),如(c)所示。
此外,光阻之薄膜沉積製程需要低射頻功率,係因如圖1C所示,當於薄膜沉積製程期間施敷高射頻功率時,光阻尺寸由於氧電漿、離子衝擊、及濺射等影響而回蝕(set back)及減少。亦即,當氧化物9藉PEALD沉積於圖案化光阻10時,其中該光阻係以雙重圖案化製程形成於基板11上,底部光阻10之一部分12係藉電漿氧化及侵蝕,該電漿包括用於沉積SiO薄膜9之氧化性氣體,從而無法取得所需尺寸之光阻10。
相關技術所涉及之問題及解答之任何討論係已涵蓋於本發明之中,其目的僅在於提供本發明之前後關係,而不應視為認可所討論之任一部分或全部於發明完成時即已習知。
於一第一具體實施例,其可解決至少一上述問題,氧化膜由多層組成,其係由體材膜(bulk film)與保護膜之結合物構成,其中體材膜係一經沉積以滿足針對目標應用之均勻度、薄膜圖案、及薄膜品質之薄膜,
而不強加限制射頻功率及/或氧化條件,以及保護膜係於體材膜沉積前以低射頻功率沉積之薄膜。於一第二具體實施例,其可解決至少一上述問題,係藉以低射頻功率重複至少一低氧化循環及以高射頻功率重複至少一非氧化循環而沉積氧化膜,從而維持良好薄膜品質,且抑制底層氧化。
於該第一具體實施例,於開始沉積一氧化膜時,以低射頻功率形成一保護膜以作為初始膜,之後連續沉積薄膜,直到薄膜厚度達到目標值,該薄膜經設計以滿足目標應用所需之薄膜均勻度、薄膜圖案、及薄膜品質。於一些具體實施例,初始膜係藉低射頻功率,如300-mm晶圓低於100W,所產生之電漿沉積,而標靶膜係藉高射頻功率,如300-mm晶圓100W至800W,所產生之電漿沉積。最終薄膜係由保護膜與標靶膜之結合物構成,其中保護膜之最小厚度為約2nm。於一些具體實施例,製程溫度範圍為約50℃至約400℃,其係電熱線型鋁基座之可控範圍。於一些具體實施例,電極間距範圍為約7mm至約15mm。根據該第一具體實施例,可達到改進薄膜品質及抑制基底膜(underlying film)氧化。此外,可最小化生產力下降之情況,即使是進行低氧化製程。
於該第二具體實施例,藉重複低功率低氧化循環與高功率非氧化循環構成之PEALD循環而沉積薄膜,從而取得所需之薄膜品質及抑制基底膜氧化。於一些具體實施例,第一電漿處理步驟係使用一包括氧之氣體系統且第二電漿處理步驟係使用一不包括氧之氣體系統,其係於特定條件下進行。於一些具體實施例,第一步驟之氧化劑流速為各反應室約500sccm至2,000sccm,而第二步驟不供應氧化性氣體。於一些具體實施例,製程溫度範圍為約50℃至約400℃,其係電熱線型鋁基座之可控範圍。於
一些具體實施例,製程壓力範圍為約200Pa至約500Pa,以便推動電漿點火(ignition),即使是在低射頻功率下亦然,以達到良好沖淨效率(purge efficiency)。第一步驟之射頻功率係低至如300-mm晶圓約30W至約100W,以便抑制基底膜氧化,且第二步驟之射頻功率範圍為約300-mm晶圓100W至約800W,其係高於第一步驟之範圍,係因第二步驟不包括氧化。於一些具體實施例,電極間距範圍為約7mm至約15mm。於一些具體實施例,各循環之射頻功率施敷時間依標靶膜品質而變,且其於第一步驟之範圍為約0.1秒至約1.5秒,而其至少0.1秒。根據該第二具體實施例,可達到維持高薄膜品質及抑制基底膜氧化。此外,不同於後處理(即表面處理),藉交替重複第一與第二步驟,不僅表面還有深處部分,於厚度方向上可均勻維持高薄膜品質。此外,藉改變第一與第二步驟之循環數比例及/或第一步驟與第二步驟之射頻功率施敷時間比例,而非改變第一與第二步驟之射頻功率,可控制薄膜品質。
本文係描述本發明之特定主體及優勢,目的在於摘錄本發明之態樣及相關技術達成之優勢。當然,應理解到,並非所有該些主體或優勢可根據本發明之任何特定具體實施例而實現。因此,例如,本領域之技術人員應體認到,本發明可藉達成或優化本文所教導之一優勢或一組優勢之方式而體現或實現,而不必達成其他本文所教導或建議之主體或優勢。
本發明之進一步態樣、特徵、及優勢將因下列詳述而顯見。
1‧‧‧SiO薄膜
2‧‧‧上部
3‧‧‧底層
4‧‧‧Si突起圖案
5‧‧‧表面
6‧‧‧SiO薄膜
7‧‧‧高氧化條件
8‧‧‧低氧化條件
9‧‧‧氧化物
9‧‧‧SiO薄膜
10‧‧‧光阻
11‧‧‧基板
12‧‧‧部分
41‧‧‧基板
42‧‧‧導電平板電極
42‧‧‧下平台
43‧‧‧反應室
44‧‧‧導電平板電極
44‧‧‧上電極
45‧‧‧高射頻功率
46‧‧‧排氣管
51‧‧‧內部
52‧‧‧電接地
63‧‧‧氣體流量控制器
64‧‧‧密封氣體流量控制器
71‧‧‧脈衝流量控制閥
72‧‧‧脈衝流量控制閥
73‧‧‧脈衝流量控制閥
74‧‧‧瓶
90‧‧‧低射頻功率
本專利或申請文件含有至少一彩色圖式。本專利或專利申請
公開案之彩圖副本將由智慧財產局根據請求及給付所需費用後提供。
本發明之該些及其他特徵現將參照較佳具體實施例之圖式陳述,其旨在於說明而非侷限本發明。附圖係經明顯簡化以用於說明,且不一定按比例繪製。
圖1A係部分加工之積體電路的示意剖面圖,其顯示SiO製程。
圖1B係由(a)、(b)、及(c)組成,其顯示超精細製程,如FinFET製程(內建於SOI基板上之非平面、雙匣電晶體)。
圖1C係部分加工之積體電路的示意剖面圖,其顯示沉積一薄膜於光阻之製程。
圖2A係顯示實施例之結果,其中電漿增強式原子層沉積法(PEALD)之「邊緣變厚」配方循環數及POR配方循環數係經改變。
圖2B係顯示薄膜厚度圖案之彩色版影像,其係由圖2A所示薄膜之2D彩色圖譜分析測量。
圖3係本發明具體實施例之保護性氧化膜之臨界尺寸(critical dimensions;CD)與厚度間關係之顯示圖。
圖4係說明本發明具體實施例之X循環、Y循環、及Z循環構成之順序。
圖5係實施例取得之薄膜濕蝕刻率顯示圖。
圖6係本發明具體實施例使用之沉積氧化膜之PEALD裝置示意圖。
於本發明中,「氣體」可包括經蒸發之固體及/或液體,且可由單一氣體或氣體混合物構成。同樣地,「一」或「一者」等詞係指一物種或屬,其包括多個物種。於本發明中,經由噴灑頭導入反應室之製程氣體可包含、基本上組成自、或組成自含金屬或矽前驅物及反應氣體。反應氣體包括一氣體,當射頻功率施敷至反應氣體時,該氣體氧化前驅物。前驅物及反應氣體可個別導入反應空間。前驅物可結合載體氣體如稀有氣體導入。一製程氣體以外之氣體,亦即不通過噴灑頭所導入之氣體,可用於如密封反應空間,其包括密封氣體如稀有氣體。於一些具體實施例,「薄膜」係指一層連續地以垂直於厚度之方向延伸,且實質上無須針孔覆蓋整個標靶或關注面。於一些具體實施例,「層」係指於一表面上形成特定厚度之結構或薄膜之同義詞或非薄膜結構。薄膜或層可由具特定特性之分立單膜或層、或多膜或層構成,且相鄰薄膜或層間之邊界可或可不明確,並可根據物理、化學、及/或任何其他特性、成型製程或順序、及/或相鄰薄膜或層之功能或目的而建立。於一些具體實施例,「由~構成」乙詞係指「包含」、「基本上組成自」、或「組成自」。此外,於本發明中,一變數之任二數字可構成該變數之可行範圍,而該可行範圍可根據常規作業決定,且任何指定範圍可涵蓋或排除終點。此外,於一些具體實施例,變數之任何指定值(不論其是否以「約」指定)可指精確值或近似值且包括等同物,並可指平均值、中位數、代表值、多數值等。
於本發明中,若未指定條件及/或結構,本領域之技術人員可鑑於本發明,易於提供此類條件及/或結構,以進行常規實驗。
於所有揭示之具體實施例中,具體實施例所使用之任何元件可以其等同之任何元件替換,包括本文中針對預期目的之該些明確、必然、或本質上之揭示。此外,本發明可同樣應用於其他裝置及方法。
於本發明中,於一些具體實施例,任何定義之含意不一定排除普通及習慣含意。
於一些具體實施例,一種藉電漿輔助循環製程形成氧化膜之方法,包含:(i)供應一前驅物至一反應空間,其中該空間放置一基板;(ii)於第一時間段施敷一第一射頻功率至該反應空間而不供應該前驅物;以及(iii)於第二時間段施敷一第二射頻功率至該反應空間而不供應該前驅物,其中第一射頻功率係低於第二射頻功率,及/或第一時間段係短於第二時間段。於一些具體實施例,氧化膜係於厚度方向上具實質上均勻組合物之薄膜,且根據組合物均勻度及/或連續性歸類為單膜。此外,「氧化膜」可指特徵為M-O鍵(M係金屬或矽)之薄膜,其主要或主體上由M-O鍵構成,並歸類為Mi-O薄膜,及/或其主要骨架實質上由Mi-O鍵構成。當使用具烴,如有機胺基矽烷,之前驅物時,氧化膜可含衍生自前驅物之碳。於一些具體實施例,氧化膜可含碳、氫、及/或氮等次要元素。
於一些具體實施例,氧化膜係由一第一氧化層及一第二氧化層構成,其中步驟(i)及(ii)而非步驟(iii)構成一第一循環,且藉重複第一循環,第一氧化層係於基板上形成,且其中步驟(i)及(iii)而非步驟(ii)構成一第二循環,且藉重複第二循環,第二氧化層係於第一氧化膜之頂部形成,用於第一及第二循環之前驅物係相同。於一些具體實施例,第一氧化層及第二氧化層係連續形成,其中氧化膜係於厚度方向上由實質上均勻之組合物
構成。於本發明中,第一氧化層亦可指「一保護層」或「一初始層」,且第二氧化層可指「一標靶氧化層」。
於一些具體實施例,步驟(ii)係經控制,以使第一氧化層具一薄膜圖案,其顯示第一氧化層之厚度,其中第一氧化層之中央係厚於沿第一氧化層之邊緣,且步驟(iii)係經控制,以使第二氧化層具一薄膜圖案,其顯示第二氧化層之厚度,其中沿第二氧化層之邊緣係厚於第二氧化層之中央。於沉積第一氧化層時,由於步驟(ii)使用低於步驟(iii)之射頻功率及/或短於步驟(iii)之射頻功率施敷,可有效抑制基底膜氧化,且當沉積第二氧化層時,第一氧化層可保護基底膜免於氧化。因此,第一氧化層之作用為保護層。此外,於沉積第一氧化層時,由於步驟(ii)使用低於步驟(iii)之射頻功率及/或短於步驟(iii)之射頻功率施敷,第一氧化層之薄膜圖案傾向顯示中央變厚且邊緣變薄,即凸起之橫截面,而第二氧化層之薄膜圖案傾向顯示邊緣變厚且中央變薄,即凹陷之橫截面。於一些具體實施例,第二氧化層厚於第一氧化層,且氧化膜具薄膜圖案,其顯示氧化膜之厚度,其中氧化膜之中央及沿其之邊緣係厚於中央與邊緣間之區域。藉篩選第一及第二氧化層之厚度,可操控標靶氧化膜之薄膜圖案。於本發明中,薄膜或層之厚度係指薄膜或層之平均厚度,其係藉隨機選取薄膜或層之多個點以測量薄膜或層之厚度而定。
於一些具體實施例,重複第一循環直到第一氧化層之厚度為約2nm或以上(如3nm、5nm、7nm、10nm、15nm、20nm、30nm、或任何前述數字間之值)。於一些具體實施例,第一氧化層之厚度為約20nm或以下。當第一氧化層具上述厚度時,其有效作為保護層(保護基底膜免
於氧化)。
於一些具體實施例,於整個步驟(i)、步驟(ii)、及步驟(iii)中,氧化性氣體係連續供應至反應室。當連續進行步驟時,第一與第二氧化層間不形成介面,以維持良好連續性。於一些具體實施例,於第一氧化層形成後及於第二氧化層形成前,第一氧化層可曝露於環境空氣。於該情況,可檢測第一與第二氧化層間之介面。然而,該檢測層係無形且無實質內容,故由第一及第二氧化層構成之氧化膜可視為單膜。此外,生產力係經改進。於本發明之一些具體實施例,「連續」係指不破壞真空、不中斷時間、不改變處理條件,之後立即進行下一步驟,或二結構間無分立之物理或化學邊界。
於一些具體實施例,第一射頻功率不大於約0.14W/cm2(基板之每單位面積瓦特數)(如0.05W/cm2、0.07W/cm2、0.10W/cm2、或任何前述數字間之值)且第二射頻功率不小於約0.14W/cm2且不大於約1.13W/cm2(如0.20W/cm2、0.50W/cm2、1.00W/cm2、或任何前述數字間之值)。於一些具體實施例,除上述或此外,用於施敷射頻功率之第一時間段為約0.1秒至約1.5秒(如0.2秒、0.5秒、1.0秒、或任何前述數字間之值),且用於施敷射頻功率之第二時間段係長於第一時間段。於一些具體實施例,第一射頻功率及第二射頻功率係相同,且用於施敷射頻功率之第一時間段係短於用於施敷射頻功率之第二時間段。於一些具體實施例,第一射頻功率係低於第二射頻功率,且用於施敷射頻功率之第一時間段係與用於施敷射頻功率之第二時間段相同。較佳地,射頻功率及施敷時間兩者係經調整以有效抑制底層氧化,以取得所需之最終氧化膜。
作為SiO薄膜之前驅物,例如,可使用有機胺基矽烷,包括雙(二乙基胺基)矽烷(BDEAS或SAM24)、肆(二甲基胺基)矽烷(4DMAS)、參(二甲基胺基)矽烷(3DMAS)、雙(二甲基胺基)矽烷(2DMAS)、肆(乙基甲基胺基)矽烷(4EMAS)、參(乙基甲基胺基)矽烷(3EMAS)、雙(三級丁基胺基)矽烷(BTBAS)、及雙(乙基甲基胺基)矽烷(BEMAS),其係單獨或任意結合二或多者使用。於一些具體實施例,前驅物基本上由前述化合物之任一者組成。「基本上由~組成」乙詞係用於法律及法規許可之最大範圍。
於一些具體實施例,電漿係以具或不具稀有氣體之O2、CxOy、及/或NxOy產生。CxOy、CO、C2O、CO2、C3O2、CO3、及C5O2可單獨或任意結合二或多者使用。NxOy、NO、N2O、NO2、N2O3、N2O4,、及N2O5可單獨或任意結合二或多者使用。
作為載體氣體、密封氣體、沖洗氣體、或製程調整氣體(輔助氣體),可使用稀有氣體如Ar、He、Ne、Kr、及Xe,其係單獨或任意結合二或多者使用。
於一些具體實施例,步驟(i)至(iii)係於溫度約50℃至約400℃下進行,且第一及第二射頻功率係於電極間充電,電極相距約7mm至15mm,其間放置基板。於一些具體實施例,電漿輔助循環製程為電漿增強式原子層沉積法(PEALD)。
於一些具體實施例,第一氧化層可於下列條件下沉積,儘管該條件可根據氧化膜類型而變:
於一些具體實施例,第二氧化層可於下列條件下沉積,儘管該條件可根據氧化膜類型而變:
於一些具體實施例,第一氧化層及第二氧化層可藉僅改變射頻功率施敷而連續形成。於其他具體實施例,第一氧化層及第二氧化層可藉不僅改變射頻功率施敷還有氣體供應條件而連續形成,其具過渡期,其中可逐步及連續改變氣流。
於其他具體實施例,氧化膜係由多個子氧化層構成,其中步驟(i)、(ii)、及(iii)構成一循環,且藉重複該循環,於基板上形成多個子氧化
層,其中於步驟(ii),係供應氧化性氣體,且於步驟(iii),不供應氧化性氣體。於上述具體實施例中,以多個子氧化層替換保護層,可有效抑制底層氧化,其中各子層係於低氧化條件下沉積,其中射頻功率低及/或射頻功率施敷時間短,接著為高射頻功率及/或更長射頻功率時間條件下之非氧電漿處理循環。多個子氧化層之沉積條件及電漿處理條件可實質上類似於或等同於先前描述之保護層及標靶層,除了下面具體描述之條件以外。
於一些具體實施例,形成標靶氧化膜之循環(亦稱作「Z循環」)係由至少一第一子循環(亦稱作「X循環」)及至少一第二子循環(亦稱作「Y循環」)構成,各第一子循環係由步驟(i)及(ii)而非步驟(iii)構成,各第二子循環係由步驟(iii)而非步驟(i)及(ii)構成。於一些具體實施例,各第一子循環沉積一子層,其構成氧化膜,且各第二子循環不沉積子層。於上述中,第二子循環為非氧電漿表面處理,不沉積任何薄膜或層。當於第二子循環時,無前驅物供應至反應空間,且該循環用作表面電漿處理,其可有效緻密化子層並改進薄膜性質。由於第二子循環之緻密化結果,子層厚度減少。
於一些具體實施例,該循環(Z循環)係由至少一第一子循環(X循環)及至少一第二子循環(Y循環)構成,各第一子循環係由步驟(i)及(ii)而非步驟(iii)構成,各第二子循環係由步驟(i)及(iii)而非步驟(ii)構成。於上述具體實施例中,由於第二子循環使用前驅物,由第一子循環形成之子層緻密化可能進展不足,且薄膜性質可能未改進。然而,薄膜生長率高,且生產力改進。因此,取決於所需之薄膜性質及生產力,前驅物可用於第二子循環。
根據所需之薄膜性質及應用,選擇Z循環數、X循環數、及Y循環數。於一些具體實施例,各Z循環取得之層厚度為約0.05nm至約2.0nm,其取決於X循環數。於一些具體實施例,針對氧化膜之預期應用及目的,可改變各Z循環之X循環數及Y循環數,形成二或多層,以便改良厚度方向之薄膜性質。於一些具體實施例,氧化膜之薄膜圖案顯示邊緣變厚且中央變薄(即凹陷之橫截面)。
於一些具體實施例,於第一子循環,氧化性氣體係以流速約500sccm至約2,000sccm(如750sccm、1,000sccm、1,500sccm、及任何前述數字間之值)連續供應至反應空間,且於第二子循環,無氧化性氣體供應至反應空間。
於一些具體實施例,第一射頻功率不大於約0.14W/cm2(基板之每單位面積瓦特數)(如0.05W/cm2、0.07W/cm2、0.10W/cm2、或任何前述數字間之值)且第二射頻功率不小於約0.14W/cm2且不大於約1.13W/cm2(如0.20W/cm2、0.50W/cm2、1.00W/cm2、或任何前述數字間之值)。於一些具體實施例,除上述或此外,用於施敷射頻功率之第一時間段為約0.1秒至約1.5秒(如0.2秒、0.5秒、1.0秒、或任何前述數字間之值),且用於施敷射頻功率之第二時間段係長於第一時間段。於一些具體實施例,第一射頻功率與第二射頻功率係相同,且用於施敷射頻功率之第一時間段係短於用於施敷射頻功率之第二時間段。於一些具體實施例,第一射頻功率係低於第二射頻功率,且用於施敷射頻功率之第一時間段與用於施敷射頻功率之第二時間段係相同。較佳地,射頻功率及施敷時間兩者係經調整,以有效抑制底層氧化,以取得所需之最終氧化膜。
於一些具體實施例,子層係連續形成,其中氧化膜係於厚度方向上由實質上均勻之組合物構成。由於重複第一及第二子循環,構成氧化膜之組合物的均勻度及連續性可於厚度方向上維持。
於一些具體實施例,第一子循環(X循環)可於下列條件進行,儘管該條件可根據氧化膜類型而變:
於一些具體實施例,第二子循環(Y循環)可於下列條件進行,儘管該條件可根據氧化膜類型而變:
於上述中,符號「*」表示由第二子循環轉換至第一子循環之過渡期,該功能係沖洗機制所需。
於一些具體實施例,第一子循環及第二子循環可連續進行,係藉僅改變射頻功率施敷及稀釋氣體流量。於其他具體實施例,第一子循環及第二子循環可連續進行,係藉不僅改變射頻功率施敷及稀釋氣體流量,還有其他氣體流量。
圖4係說明本發明具體實施例之X循環、Y循環、及Z循環構成之順序。於此具體實施例,於Y循環,不供應前驅物,且不供應氧化性氣體,但供應更高之射頻功率,且時間比X循環的長。由於X循環與Y循環間之製程條件不同,其間存在過渡期,其一般而言為0.1秒或0.2秒。
於一些具體實施例,於X循環,可以脈衝方式供應O2,其不與前驅物脈衝重疊。於一些具體實施例,藉施敷射頻功率至反應空間,可於反應空間產生電漿(原位電漿)。於一些具體實施例,可以遠端電漿單元激發反應氣體並供應電漿至反應空間。
圖6係本發明一些具體實施例使用之PEALD裝置示意圖,較佳為連接可控編程以進行本文所述之順序。於此圖中,藉提供一對平行之導電平板電極44、42,並於反應室43之內部51彼此相對,施敷高射頻功率(13.56MHz或27MHz)45及低射頻功率5MHz或更低(400kHz~500kHz,必要時)90至一側,電接地52另一側,於電極間激發電漿。於下平台42(下電極)提供溫度調節器,且置於其上之基板41溫度維持在恆定溫度。上電極44係作為淋浴板(shower plate),且反應氣體及稀有氣體經由氣體流量控制器63、脈衝流量控制閥71-73、及淋浴板導入反應室43。於此具體實施例,前驅物以液態保存於一瓶74,其配備加熱器。稀有氣體可連續流入反應室43,其係(a)經由閥71,當閥72與73關閉時,或(b)經由閥72、瓶74、及閥73,當閥71關閉時。於(b),稀有氣體攜帶前驅物,並與前驅物一起流入反應室43。於(a),稀有氣體單獨流入反應室43。藉上述閥門操作機制,於脈衝供給前驅物時,可連續供給稀有氣體。此外,於反應室43,提供一排氣管46,反應室43內部51之氣體可經其排出。此外,反應室係提供一密封氣體流量控制器64,以導入密封氣體至反應室43的內部51(本圖省略一分隔板,其於反應室內部分隔出反應區及轉移區)。針對循環式PECVD,可使用相同裝置。
本領域之技術人員應理解到,所述裝置包括一或多個控制器
(未顯示),其係經編程或以其他方式配置,使得進行本文另外描述之沉積及反應器清洗製程。控制器係與反應器之各電源、加熱系統、泵、機器、及氣體流量控制器或閥門相通信,如本領域之技術人員所理解。
將300-mm Si基板,其具光阻圖案形成於其上,載入圖6所示之裝置,並於下表5所示之條件下藉PEALD沉積一氧化膜。結果顯示於圖2A。於此應用中,標靶膜係產生薄膜圖案所需,且沿基板邊緣顯示相對高之厚度。於表中,「僅POR(厚)」乙詞(「POR」係指「參考膜之製程-中央變厚」)係指PEALD製程僅使用低射頻功率氧電漿,直到薄膜厚度達到約20nm。「僅POR(薄)」乙詞係指PEALD製程僅使用低射頻功率氧電漿,直到薄膜厚度達到約10nm。「僅邊緣變厚」乙詞係指PEALD製程僅使用高射頻功率氧電漿,直到薄膜厚度達到約20nm。「雙層1」乙詞係指PEALD製程使用低射頻功率氧電漿,直到薄膜厚度達到約10nm,之後使用高射頻功率氧電漿,直到薄膜厚度達到約20nm。「雙層2」乙詞係指PEALD製程使用低射頻功率氧電漿,直到薄膜厚度達到約3nm,之後使用高射頻功率氧電漿,直到薄膜厚度達到約20nm。「高射頻功率」係指以3,000W射頻功率施敷1.0秒,而「低射頻功率」係指以50W射頻功率施敷0.3秒。「邊緣變厚配方」乙詞係指施敷高射頻功率,而「POR配方」乙詞係指施敷低射頻功率。「WiW均勻度[1σ%]」(「WiW」係指「晶圓之內」)乙詞係指於1%(STDEV/Ave x 100)之平面薄膜均勻度,而「WiW均勻度[全範圍%]」乙詞係指全部範圍之平面薄膜均勻度,其係以((最大值-最小值)/
平均值x 100)評估。「厚度分佈」顯示薄膜厚度圖案之灰階影像,其係由薄膜之2D彩色圖譜分析測量。由於灰階影像未提供是否暗區代表厚區或薄區之資訊,圖2B顯示薄膜厚度圖案之彩色版影像,其係由圖2A所示薄膜之2D彩色圖譜分析測量。於影像中,紅色區域代表具相對較高厚度之區域,而藍色區域代表具相對較低厚度之區域。「示意圖案」顯示當觀察橫截面時,薄膜之示意性圖案。
如圖2A及圖2B所見,高射頻功率施敷使得薄膜圖案顯示邊緣變厚(大致上凹陷圖案),如「僅邊緣變厚」所示,而低射頻功率施敷使得薄膜圖案顯示中央變厚(大致上凸起圖案),如「僅POR(厚)」及「僅POR(薄)」所示。當結合高射頻功率施敷及低射頻功率施敷時,如「雙層1」及「雙層2」所示,薄膜圖案顯示中央變厚且邊緣變厚(例如,覆蓋一凹陷
薄膜於凸起薄膜頂部),其滿足邊緣變厚之需求。
下表6顯示各實施例中底部光阻氧化之結果。「PR寬度」乙詞係指薄膜沉積前之光阻寬度,「Depo厚度」乙詞係指沉積於光阻之薄膜厚度,且「CD」乙詞係指臨界尺寸(亦即,覆蓋薄膜之光阻寬度,即於橫截面沿水平線擷取,光阻一側壁上形成之氧化膜厚度、光阻寬度、及於光阻另一側壁上形成之氧化膜厚度之總和)。雖然高射頻功率施敷使得薄膜圖案顯示邊緣變厚,如表5之「僅邊緣變厚」所示,但相較於表6之「僅POR(厚)」及「雙層1」之CD 68nm,其CD減至61nm。這表示,當使用高射頻功率施敷時,光阻經氧化侵蝕,其係由氧電漿造成,且由於連續之離子衝擊,光阻寬度減少。相反地,當開始沉積時,使用低射頻功率施敷以形成一保護性氧化膜,該保護膜保護光阻免於氧化及離子衝擊,且沉積之氧化膜不會減少光阻寬度。當保護膜厚度變薄時(「雙層2」),CD輕微減少(CD係67nm),但該減少不明顯。「雙層1」及「雙層2」兩者顯示CD與「僅POR(厚)」的相當。
圖3係CD(臨界尺寸)與保護性氧化膜厚度間之關係顯示圖,包括表6顯示之結果。如圖3所示,當保護性氧化膜厚度為2nm、3nm、或7nm以上時,可有效抑制底層氧化。然而,當保護性氧化膜厚度為10nm以上時,底層之氧化抑制達到平線區(plateau)。因此,一旦保護性氧化膜厚度能有效抑制底層氧化,則可根據標靶氧化膜所需之薄膜圖案選擇保護性氧化膜的厚度。
可藉操縱射頻功率及射頻施敷時間控制薄膜圖案。當於相對較長時間使用較高射頻功率時,所得薄膜圖案顯示邊緣變厚(凹陷圖案),而當於相對較短時間使用較低射頻功率時,所得薄膜圖案顯示中央變厚(凸起圖案)。然而,當以高射頻功率用於凹陷圖案時,底層例如光阻係經氧化及侵蝕,其降低CD性質。另一方面,當使用低射頻功率時,即使可抑制底層氧化,仍難以取得凹陷圖案。藉使用低射頻功率施敷及高射頻功率施敷之順序,可沉積一凹陷圖案薄膜,而不會造成底層氧化,亦即不會降低CD性質。
於下表7所示之條件下,藉PEALD於基板上沉積氧化膜,其係使用圖6所示之裝置。「低功率SiO」係指以圖4所示之X循環及低射
頻功率沉積一SiO薄膜。「高功率SiO」係指以圖4所示之X循環及高射頻功率替代低射頻功率(改良之X循環)沉積一SiO薄膜。「低功率HQ SiO」係指以圖4所示之Z循環,其包括X循環及Y循環,沉積一SiO薄膜。以所得薄膜進行濕蝕刻測試。
結果顯示於圖5。「濕蝕刻率」係指使用DHF(1:100)之濕蝕刻率。如圖5所示,當使用低射頻功率循環時(X循環),所得SiO薄膜(「低功率SiO」)不具良好濕蝕刻抗性。當使用高射頻功率循環時(改良之X循環),所得SiO薄膜(「高功率SiO」)具良好濕蝕刻抗性。令人意外地,當結合低射頻功率循環及高射頻功率非氧化循環(Z循環)使用時,所得SiO薄膜(「低功率HQ SiO」)呈現極佳濕蝕刻抗性。此外,由於重複Z循環,
其由X循環及Y循環構成,所得之SiO薄膜,預期該整個薄膜具實質上均勻之組合物,特別是在厚度方向上。亦即,Y循環並非沉積後表面處理,而為循環之一部分。
本領域之技術人員應理解到,可進行許多及各種改良而不違背本發明之精神。因此,應清楚理解到,本發明之形式僅在於說明,而未旨在侷限本發明之範疇。
Claims (17)
- 一種藉電漿輔助循環製程形成氧化膜之方法,包含:(i)供應一前驅物至一反應空間,其中該空間放置一基板;(ii)於第一時間段施敷一第一射頻功率至該反應空間而不供應該前驅物;以及(iii)於第二時間段施敷一第二射頻功率至該反應空間而不供應該前驅物,其中該第一射頻功率係低於該第二射頻功率,及/或該第一時間段係短於該第二時間段;其中該氧化膜係由一第一氧化層及一第二氧化層構成,其中步驟(i)及(ii)而非步驟(iii)構成一第一循環,且藉重複該第一循環,該第一氧化層係於該基板上形成,且其中步驟(i)及(iii)而非步驟(ii)構成一第二循環,且藉重複該第二循環,該第二氧化層係於該第一氧化膜之頂部形成,用於該第一及第二循環之該前驅物係相同;及其中步驟(ii)係經控制,以使該第一氧化層具一薄膜圖案,其顯示該第一氧化層之厚度,其中該第一氧化層之中央係厚於沿該第一氧化層之邊緣,且步驟(iii)係經控制,以使該第二氧化層具一薄膜圖案,其顯示該第二氧化層之厚度,其中沿該第二氧化層之邊緣係厚於該第二氧化層之中央。
- 如申請專利範圍第1項之方法,其中該第一循環係經重複,直到該第一氧化層具厚度約2nm或以上。
- 如申請專利範圍第2項之方法,其中該第一氧化層之厚度為約20nm或以下。
- 一種藉電漿輔助循環製程形成氧化膜之方法,包含:(i)供應一前驅物至一反應空間,其中該空間放置一基板;(ii)於第一時間段施敷一第一射頻功率至該反應空間而不供應該前驅物;以及(iii)於第二時間段施敷一第二射頻功率至該反應空間而不供應該前驅物,其中該第一射頻功率係低於該第二射頻功率,及/或該第一時間段係短於該第二時間段;其中該氧化膜係由一第一氧化層及一第二氧化層構成,其中步驟(i)及(ii)而非步驟(iii)構成一第一循環,且藉重複該第一循環,該第一氧化層係於該基板上形成,且其中步驟(i)及(iii)而非步驟(ii)構成一第二循環,且藉重複該第二循環,該第二氧化層係於該第一氧化膜之頂部形成,用於該第一及第二循環之該前驅物係相同;及其中該第二氧化層係厚於該第一氧化層,且該氧化膜具一薄膜圖案,其顯示該氧化膜之厚度,其中該氧化膜之中央及沿其之邊緣係厚於中央與邊緣間之區域。
- 如申請專利範圍第1或4項之方法,其中於整個步驟(i)、步驟(ii)、及步驟(iii)中連續供應一氧化性氣體至該反應室。
- 如申請專利範圍第1或4項之方法,其中該第一射頻功率係不大於約0.14W/cm2(基板之每單位面積瓦特數),且該第二射頻功率係不小於約0.14W/cm2且不大於約1.13W/cm2。
- 如申請專利範圍第1或4項之方法,其中該第一氧化層及該第二氧化層係連續形成,其中該氧化膜係於厚度方向上由實質上均勻之組合物構成。
- 一種藉電漿輔助循環製程形成氧化膜之方法,包含:(i)供應一前驅物至一反應空間,其中該空間放置一基板;(ii)於第一時間段施敷一第一射頻功率至該反應空間而不供應該前驅物;以及(iii)於第二時間段施敷一第二射頻功率至該反應空間而不供應該前驅物,其中該第一射頻功率係低於該第二射頻功率,及/或該第一時間段係短於該第二時間段;其中該氧化膜係由多個子氧化層構成,其中步驟(i)、(ii)、及(iii)構成一循環,且藉重複該循環,該多個子氧化層係於該基板上形成,其中於步驟(ii),係供應氧化性氣體,且於步驟(iii),不供應氧化性氣體;及其中該循環係由至少一第一子循環及至少一第二子循環構成,各第一子循環係由步驟(i)及(ii)而非步驟(iii)構成,各第二子循環係由步驟(iii) 而非步驟(i)及(ii)構成。
- 如申請專利範圍第8項之方法,其中各第一子循環沉積一子層,其構成該氧化膜,且各第二子循環不沉積子層。
- 如申請專利範圍第8項之方法,其中該循環係由至少一第一子循環及至少一第二子循環構成,各第一子循環係由步驟(i)及(ii)而非步驟(iii)構成,各第二子循環係由步驟(i)及(iii)而非步驟(ii)構成。
- 如申請專利範圍第8項之方法,其中於第一子循環,該氧化性氣體係以流速約500sccm至約2,000sccm連續供應至該反應空間,且於第二子循環,無氧化性氣體供應至該反應空間。
- 如申請專利範圍第8項之方法,其中該第一射頻功率係不大於約0.14W/cm2(基板之每單位面積瓦特數),且該第二射頻功率係不小於約0.14W/cm2且不大於約1.13W/cm2。
- 如申請專利範圍第8項之方法,其中該用於施敷射頻功率之第一時間段為約0.1秒至約1.5秒,且該用於施敷射頻功率之第二時間段係長於該第一時間段。
- 如申請專利範圍第8項之方法,其中該第一射頻功率及該第二射頻功 率係相同,且該用於施敷射頻功率之第一時間段係短於該用於施敷射頻功率之第二時間段。
- 如申請專利範圍第8項之方法,其中該子層係連續形成,其中該氧化膜係於厚度方向上由實質上均勻之組合物構成。
- 如申請專利範圍第8項之方法,其中步驟(i)至(iii)係於溫度約50℃至約400℃下進行,且該第一及第二射頻功率係於電極間充電,該電極相距約7mm至15mm,其間放置該基板。
- 如申請專利範圍第8項之方法,其中該電漿輔助循環製程為電漿增強式原子層沉積法。
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US20150315704A1 (en) | 2015-11-05 |
KR102370787B1 (ko) | 2022-03-07 |
US9464352B2 (en) | 2016-10-11 |
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