TWI646662B - Non-volatile semiconductor memory device - Google Patents
Non-volatile semiconductor memory device Download PDFInfo
- Publication number
- TWI646662B TWI646662B TW104119865A TW104119865A TWI646662B TW I646662 B TWI646662 B TW I646662B TW 104119865 A TW104119865 A TW 104119865A TW 104119865 A TW104119865 A TW 104119865A TW I646662 B TWI646662 B TW I646662B
- Authority
- TW
- Taiwan
- Prior art keywords
- movable charge
- movable
- active region
- layer
- charge collecting
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
- H10D62/351—Substrate regions of field-effect devices
- H10D62/357—Substrate regions of field-effect devices of FETs
- H10D62/364—Substrate regions of field-effect devices of FETs of IGFETs
- H10D62/378—Contact regions to the substrate regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
- H10W20/42—Vias, e.g. via plugs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
- H10W20/43—Layouts of interconnections
Landscapes
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
- Physics & Mathematics (AREA)
- Geometry (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2014-127706 | 2014-06-20 | ||
| JP2014127706A JP6286292B2 (ja) | 2014-06-20 | 2014-06-20 | 不揮発性半導体記憶装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201611196A TW201611196A (zh) | 2016-03-16 |
| TWI646662B true TWI646662B (zh) | 2019-01-01 |
Family
ID=54935562
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW104119865A TWI646662B (zh) | 2014-06-20 | 2015-06-18 | Non-volatile semiconductor memory device |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US10680001B2 (https=) |
| JP (1) | JP6286292B2 (https=) |
| TW (1) | TWI646662B (https=) |
| WO (1) | WO2015194582A1 (https=) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9847133B2 (en) * | 2016-01-19 | 2017-12-19 | Ememory Technology Inc. | Memory array capable of performing byte erase operation |
| CN109565201B (zh) * | 2016-08-09 | 2021-06-18 | 日本电产株式会社 | 马达 |
| KR20180120870A (ko) | 2017-04-27 | 2018-11-07 | 삼성전자주식회사 | 반도체 소자 |
| JP7462389B2 (ja) * | 2019-07-18 | 2024-04-05 | ローム株式会社 | 不揮発性半導体記憶装置 |
| KR102864662B1 (ko) | 2020-12-30 | 2025-09-25 | 에스케이하이닉스 주식회사 | 비휘발성 메모리 장치 |
Citations (3)
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| US6107659A (en) * | 1997-09-05 | 2000-08-22 | Mitsubishi Denki Kabushiki Kaisha | Nonvolatile semiconductor memory device operable at high speed with low power supply voltage while preventing overerasing/overwriting |
| JP2005142571A (ja) * | 2003-11-05 | 2005-06-02 | Magnachip Semiconductor Ltd | 不揮発性メモリ素子及びその製造方法 |
| JP2014086435A (ja) * | 2012-10-19 | 2014-05-12 | Floadia Co Ltd | 不揮発性半導体記憶装置 |
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| JP6078327B2 (ja) * | 2012-12-19 | 2017-02-08 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
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-
2014
- 2014-06-20 JP JP2014127706A patent/JP6286292B2/ja active Active
-
2015
- 2015-06-17 WO PCT/JP2015/067412 patent/WO2015194582A1/ja not_active Ceased
- 2015-06-17 US US15/319,875 patent/US10680001B2/en active Active
- 2015-06-18 TW TW104119865A patent/TWI646662B/zh active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6107659A (en) * | 1997-09-05 | 2000-08-22 | Mitsubishi Denki Kabushiki Kaisha | Nonvolatile semiconductor memory device operable at high speed with low power supply voltage while preventing overerasing/overwriting |
| JP2005142571A (ja) * | 2003-11-05 | 2005-06-02 | Magnachip Semiconductor Ltd | 不揮発性メモリ素子及びその製造方法 |
| JP2014086435A (ja) * | 2012-10-19 | 2014-05-12 | Floadia Co Ltd | 不揮発性半導体記憶装置 |
Also Published As
| Publication number | Publication date |
|---|---|
| US10680001B2 (en) | 2020-06-09 |
| JP2016009692A (ja) | 2016-01-18 |
| JP6286292B2 (ja) | 2018-02-28 |
| WO2015194582A1 (ja) | 2015-12-23 |
| US20170133391A1 (en) | 2017-05-11 |
| TW201611196A (zh) | 2016-03-16 |
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