TWI567987B - 用於ｎ型及ｐ型金氧半導體源極汲極接觸之三五族層 - Google Patents

用於ｎ型及ｐ型金氧半導體源極汲極接觸之三五族層 Download PDF

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TWI567987B
TWI567987B TW101147882A TW101147882A TWI567987B TW I567987 B TWI567987 B TW I567987B TW 101147882 A TW101147882 A TW 101147882A TW 101147882 A TW101147882 A TW 101147882A TW I567987 B TWI567987 B TW I567987B
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type source
material layer
doped
semiconductor material
tri
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TW101147882A
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TW201342612A (zh
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葛蘭 葛雷斯
安拿 莫希
塔何 甘尼
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英特爾股份有限公司
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    • H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
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    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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Description

用於N型及P型金氧半導體源極汲極接觸之三五族層
技術被揭示，用於形成已相對傳統裝置減少寄生接觸電阻的電晶體裝置。
包含被形成在半導體基板上之電晶體、二極體、電阻器、電容器、及其他被動與主動電子裝置的電路裝置之增加的性能，典型係於那些裝置之設計、製造、及操作期間所考慮之主要因素。譬如，在諸如那些被使用於互補金屬氧化物半導體(CMOS)的金屬氧化物半導體(MOS)電晶體半導體裝置之設計及製造或形成期間，其通常想要的是使與接觸有關之寄生電阻減至最小，該電阻以別的方式已知為外部電阻Rext。減少的Rext能夠由相同之電晶體設計有較高的電流。
【發明內容及實施方式】
技術被揭示，用於形成已相對傳統裝置減少寄生接觸電阻的電晶體裝置。該等技術能被提供例如在該半導體加工流程中之地點，在此傳統之接觸處理將直接地採用矽源極汲極區域上之矽化物，及使用標準之觸點堆疊、諸如矽(Si)或矽鍺(SiGe)或鍺(Ge)源極/汲極區域上之一系列金屬。於一些示範實施例中，該等技術能被使用於提供CMOS裝置之MOS電晶體的觸點，在此中介之三五族 半導體材料層被提供於該p型及n型源極/汲極區域與其個別觸點金屬之間，以顯著地減少接觸電阻。該中介之三五族半導體材料層可具有一小的能帶隙(例如低於0.5電子伏特)及/或以別的方式被摻雜，以提供該想要之傳導性。該等技術能被使用在極多電晶體架構(例如平面式、鰭式、及奈米線電晶體)上，包含應變及無應變通道結構。
一般之概觀
如先前所說明，該等電晶體中之增加的驅動電流能藉由減少裝置電阻所達成。接觸電阻係裝置之全部電阻的一分量。典型之電晶體觸點堆疊包含譬如矽或SiGe源極/汲極層、矽化物/鍺化物層、氮化鈦黏附層、及鎢觸點/插塞。諸如鎳、鉑、鈦、鈷等金屬之矽化物及鍺化物能於鎢插塞沈積之前被形成在該源極汲極區域上。於此等組構中，該接觸電阻係相當高及藉由對該金屬中之釘扎位準的矽或SiGe價帶對齊所有效地限制。形成觸點之典型的工業方式大致上採用具有於0.5-1.5電子伏特、或較高的範圍中之能帶隙的合金。雖然一些此等方式可為適當用於n型電晶體結構，它們不適當用於p型電晶體結構。
如此，及按照本發明之此實施例，中介之三五族半導體材料層係在源極/汲極形成之後、但在金屬觸點沈積之前沈積。注意相同的中介三五族半導體材料層可被沈積在p型及n型源極/汲極區域兩者之上。於一些實施例中，該 三五族材料層被選擇，以譬如具有一狹窄之能帶隙、諸如具有低於05電子伏特的能帶隙之銻化銦(InSb)或其他相關化合物，包含鋁(Al)、鎵(Ga)、銦(In)、磷(P)、砷(As)、及/或銻(Sb)之各種組合。此小能帶隙三五族材料層可譬如被使用於對MOS電晶體源極汲極區域、諸如p型及n型Si、SiGe合金、及Ge源極汲極區域提供良好之接觸特性。於其他實施例中。具有任意能帶隙的三五族材料可被沈積及摻雜，藉此可比較於小能帶隙三五族材料而增加其至一位準之傳導性、或至在其他方面用於該給定之應用可接受的傳導性位準。
注意於一些實施例中，既然此小能帶隙材料中之載子的熱產生係在室溫足以能夠有高傳導性，該三五族半導體材料能被保持無摻雜的，及特別相對於具有低於約0.5電子伏特的能帶隙之三五族材料。於摻雜被使用之其他實施例中，諸如那些使用具有任意能帶隙的三五族材料者，該摻雜可被以許多方式執行，包含原位及非原位摻雜技術。一些此等實施例採用具有充分高摻雜位準之三五族材料的使用，並具有四族摻雜劑、諸如碳、矽、鍺、或錫。在很高的摻雜位準(例如大於1E18原子/立方公分替代濃度)，這些兩性摻雜劑促成於價帶及傳導帶兩者中之載子，藉此增加用於兩載子型式之載子濃度。於一些此案例中，該摻雜係在原位進行。於其他實施例中，本質的三五族材料層被沈積，隨後有一非原位摻雜製程、諸如離子植入或擴散摻雜，以便提供該想要之傳導性(例如具有譬如 100至500S/cm之值的傳導性)。於一些示範案例中，該三五族材料層能被摻雜，使得該p型區域具有第一摻雜方式，且n型區域具有第二摻雜方式。例如，n型源極/汲極區域能被摻雜以譬如矽、鍺、或碲，且p型源極/汲極區域可被摻雜以鋅或鎘。如將在此揭示內容之觀點中被了解，此等涉及多數摻雜方式之實施例大致上將需要額外之佈圖步驟。
進一步注意該三五族材料層能被採用，以改善任何數目電晶體結構及組構中之接觸電阻，包含平面式、升高的源極/汲極、非平面式(例如奈米線電晶體及鰭式電晶體、諸如雙閘極及三閘極電晶體結構)、以及應變與無應變通道結構。此外，該等電晶體結構可包含源極及汲極尖部區域，其被設計成例如減少該電晶體之整個電阻，而改善短通道效應(SCE)，如有時候做成者。任何數目之結構特色可會同如在此中所敘述之三五族半導體材料層被使用。
該電晶體結構可包含p型源極/汲極區域、n型源極/汲極區域、或n型及p型源極/汲極區域。於一些示範實施例中，該電晶體結構於MOS結構中包含矽、SiGe合金、或名義上純鍺薄膜(例如，諸如那些具有少於10%矽者)之摻雜劑植入源極/汲極區域或外延(或多晶)的替換源極/汲極區域。於任何此等措施中，三五族半導體材料之層或蓋子可按照本發明之實施例被直接地形成在該源極/汲極區域之上。該三五族材料層可同樣被直接地形成 在該電晶體結構、諸如多閘極及/或接地分接頭區域或其他此等區域的其他零件之上，如果如此想要，在此低接觸電阻係想要的。
於分析(例如掃描電子顯微鏡及/或復合映射)時，按照本發明成份之實施例所建構的結構將有效地顯示三五族半導體材料的一額外層，包括例如鋁、鎵、銦、磷、砷、及/或銻之組合(隨同任何摻雜劑，如果可適用，其將傳導性增加至一可接受之位準)，並將呈現低於使用傳統矽化物及鍺化物觸點製程所製成之裝置的接觸電阻之接觸電阻。如將被了解，對於高效能觸點具有一需要的任何數目之半導體裝置或電路系統可自在此中所提供之低電阻觸點技術獲益。
如此，相對於較低的接觸電阻，按照本發明之實施例所建構的電晶體結構在傳統結構之上提供一改良。以此揭示內容之觀點，極多製程變動將變得明顯。例如，該三五族半導體材料可於絕緣體層係沈積在該源極/汲極層上方之前被沈積在該源極汲極區域上。另一選擇係，於絕緣體層係沈積在該源極/汲極層區域上方且接觸溝渠已被蝕刻至該源極/汲極層之後，該三五族半導體材料可被沈積在該源極汲極區域上。
方法論及架構
圖1A係按照本發明之實施例用於形成具有低接觸電阻之電晶體結構的方法。圖2A至2F說明當該方法被進行 且按照一些實施例時所形成之範例結構。
該範例方法包含在半導體基板上形成102一或多個閘極堆疊，而MOS裝置可被形成於該基板上。該MOS裝置可包括NMOS或PMOS電晶體，或NMOS及PMOS電晶體兩者(例如用於CMOS裝置)。圖2A顯示一範例結果結構，於此案例中，其包含形成在相同基板300上及藉由淺溝渠隔離(STI)所分開之NMOS及PMOS電晶體兩者。p型及n型區域間之其他合適形式的隔離同樣能被使用。如能被看見，每一閘極堆疊係形成在電晶體的通道區域之上，且包含閘極介電層302、閘極電極304、選擇性的硬罩幕層306，且間隔層310被形成毗連該閘極堆疊。
該閘極介電層302可為譬如任何合適之氧化物、諸如二氧化矽或高k值閘極介電材料。高k值閘極介電材料之範例包含例如鉿氧化物、鉿矽氧化物、鑭氧化物、鑭鋁氧化物、鋯氧化物、鋯矽氧化物、鉭氧化物、鈦氧化物、鋇鍶鈦氧化物、鋇鈦氧化物、鍶鈦氧化物、釔氧化物、鋁氧化物、鉛鈧鉭氧化物、及鉛鋅鈮酸鹽。於一些實施例中，當高k值材料被使用時，退火製程可在該閘極介電層302上被進行，以改善其品質。於一些特定示範實施例中，該高k值閘極介電層302可具有於5埃至約100埃厚(例如10埃)的範圍中之厚度。於其他實施例中，該閘極介電層302可具有氧化物材料之一單層的厚度。大致上，該閘極介電層302之厚度應為足以由該源極及汲極觸點電絕緣該閘極電極304。於一些實施例中，諸如退火處理之額外的 處理可在該高k值的閘極介電層302上被施行，以改善該高k值材料之品質。
該閘極電極304材料可為譬如多晶矽、氮化矽、碳化矽、或金屬層(例如鎢、氮化鈦、鉭、氮化鉭)，雖然其他合適之閘極電極材料能同樣被使用。於一些示範實施例中，可為犧牲材料之閘極電極304材料具有於10埃至500埃厚(例如100埃)的範圍中之厚度，該犧牲材料稍後被移去，用於一替換性金屬閘極(RMG)製程。
該選擇性閘極的硬罩幕層306能在處理期間被使用於提供某些利益或應用，諸如保護該閘極電極304不遭受隨後之蝕刻及/或離子植入製程。該硬罩幕層306可使用典型之硬罩幕材料被形成，諸如二氧化矽、氮化矽、及/或其他傳統的絕緣體材料。
該閘極堆疊能如傳統地做成或使用任何合適之定製技術(例如傳統佈圖製程，以蝕刻掉該閘極電極及該閘極介電層之各部份而形成該閘極堆疊，如在圖2A中所示)被形成。該閘極介電層302及閘極電極304材料之每一者可被形成，譬如使用傳統沈積製程、諸如化學蒸氣沈積(CVD)、原子層沈積(ALD)、旋轉式塗佈沈積(SOD)、或物理蒸氣沈積(PVD)。交互之沈積技術同樣可被使用，例如，該閘極介電層302及閘極電極304材料可被熱生長。如以此揭示內容之觀點將被了解，任何數目之其他合適材料、幾何形狀、及形成製程能被使用於提供本發明之實施例，以便提供如在此中所敘述之低接觸電 阻電晶體裝置或結構。
該等間隔層310可被形成，譬如，使用傳統材料，諸如氧化矽、氮化矽、或其他合適之間隔層材料。該間隔層310之寬度大致上可基於待形成電晶體用之設計需求而被選擇。然而，按照一些實施例，該間隔層310之寬度係不遭受藉由該源極及汲極上尖部之形成所強加的設計限制，並在該源極/汲極尖部區域中給予充分高硼摻雜鍺含量。
任何數目之合適的基板能被使用於提供基板300，包含塊狀基板、絕緣底半導體基板(XOI，在此X係半導體材料、諸如矽、鍺、或富含鍺之矽)；及多層狀結構，包含於隨後閘極佈圖製程之前將鰭片或奈米線形成在其上之那些基板。於一些特定的示範案例中，該基板300係鍺或矽或SiGe塊狀基板、或鍺或矽或SiGe在氧化物上之基板。雖然可形成該基板300的一些材料之範例在此被敘述，可用作一基礎的任何材料落在所主張之發明的精神及範圍內，而低接觸電阻半導體裝置可被製成在該基礎上。
進一步參考圖1A，在該一或多個閘極堆疊被形成之後，該方法繼續界定104該電晶體結構之源極/汲極區域。該源極/汲極區域能被以任何數目之合適製程及組構所提供。譬如，該源極/汲極區域可被植入、蝕刻及上充填、升高、矽或鍺或SiGe合金、p型及/或n型，且具有一平面式或鰭片或線形擴散區域。例如，於一些此等示範案例中，該源極及汲極區域能使用植入/擴散製程或蝕刻/沈積製程之任一者被形成。於該前一製程中，諸如硼、 鋁、銻、磷、或砷之摻雜劑可被離子植入該基板300，以形成該源極及汲極區域。該離子植入製程之後典型有一退火製程，其活化該等摻雜劑，且亦可造成該等摻雜劑進一步擴散進入該基板300。於該後一製程中，該基板300可首先被蝕刻，以在該等源極及汲極區域之位置形成凹部。一外延的沈積製程可接著被進行，以用矽合金、諸如矽鍺或碳化矽充填該等凹部，藉此形成該源極及汲極區域。於一些措施中，該外延沈積的矽合金可原位或非原位地以摻雜劑、諸如硼、砷、或磷被摻雜。
於圖2A-2F所示之示範實施例中，基板300已被蝕刻，以提供孔腔以及個別之尖部區域，其底切該閘極介電層302。該等孔腔及尖部區域已被充填，以提供該源極/汲極區域及該選擇性之尖部區域。按照一些特定之示範實施例，在此該基板300係矽塊狀或絕緣層上矽(SOI)基板，該源極及汲極孔腔隨著其個別之尖部區域被以原位摻雜的矽或SiGe或鍺充填，藉此形成該源極及汲極區域(隨著其個別的上尖部)。相對於材料(例如摻雜的或無摻雜的矽、鍺、SiGe)、摻雜劑(例如硼、砷、或磷)、及幾何形狀(例如源極/汲極層之厚度範圍可例如由50至500奈米，以便提供一齊平或升高的源極/汲極區域)，任何數目之源極/汲極層組構能在此被使用。
如將在此揭示內容之觀點中被了解，任何數目之其他電晶體部件可被以本發明之實施例實施。例如，該通道可為應變或無應變的，且該源極/汲極區域可或不能包含尖 部區域，其形成該對應的源極/汲極區域及該通道區域間之區域中。在這種意義上，不論電晶體結構是否具有應變或無應變通道、或源極汲極尖部區域或沒有源極汲極尖部區域，係特別與本發明之各種實施例無關者，且此等實施例係不意欲受限於任何特別之此等結構特色。反之，任何數目之電晶體結構及型式、及特別是那些結構具有n型及p型源極/汲極電晶體區域者，能由採用小能帶隙及/或以別的方式在該源極/汲極區域之上充分地摻雜的三五族材料層獲益，如在此中所敘述者。大致上，如果該能帶隙係足夠小，則在室溫無需摻雜劑(雖然摻雜劑能被使用，如果如此想要)。於一特定之示範案例中，InSb具有無摻雜的p及n型源極/汲極區域之作用。用於較大的能帶隙三五族材料(>0.5電子伏特)，摻雜能被使用，以提供該想要之傳導性。
進一步參考圖1A，在該源極/汲極區域被界定之後，此示範實施例之方法繼續沈積106一絕緣體層322。圖2B顯示絕緣體層322，如係與該閘極堆疊之硬罩幕層306齊平，但其不須為此。該絕緣體能夠被以許多方式建構。於一些實施例中，絕緣體層322被以SiO2或其他低k值絕緣體材料實施。於更一般的意義中，絕緣體層322材料之介電常數能如想要地被選擇。於一些實施例中，絕緣體層322可包含襯裡(例如氮化矽)，隨後有一或更多的SiO2層，或氮化物、氧化物、氮氧化物、碳化物、碳氧化物、或其他合適絕緣體材料之任何組合。可被稱為層間介電層 (ILD)之絕緣體層322可如一般所做成地被平坦化(例如經由後沈積平坦化製程、諸如化學機械平坦化、或CMP)。能被使用於形成絕緣體層322之其他範例絕緣體材料包含例如碳摻雜的氧化物(CDO)、諸如八氟環丁烷或聚四氟乙烯、氟矽酸玻璃(FSG)之有機聚合物、及諸如倍半矽氧烷、矽氧烷、或有機矽酸鹽玻璃的有機矽酸鹽。於一些範例組構中，該絕緣體層322可包含細孔或其他空隙，以進一步減少其介電常數。
如將在此揭示內容之觀點中被了解，及按照本發明的一些實施例，在此替換性金屬閘極(RMG)製程被使用，該方法可另包含使用蝕刻製程移去該閘極堆疊(包含該高k值閘極介電層302、該犧牲的閘極電極304、及該硬罩幕層306)，如傳統上所做成者。於一些此等案例中，僅只該犧牲的閘極電極304及硬罩幕層306被移去。如果該閘極介電層302被移去，該方法可將新的閘極介電層沈積進入該溝渠開口而繼續。任何合適之閘極介電材料、諸如那些先前所述者可在此被使用，諸如鉿氧化物。相同之沈積製程亦可被使用。該閘極介電層之替換可被使用於譬如在應用該乾式及濕式蝕刻製程期間對付任何對於該原來之閘極介電層可能已發生的損壞，及/或以高k值或在其他方面想要之閘極介電材料替換低k值或犧牲介電材料。於此等RMG製程中，該方法可另包含將該閘極電極層沈積進入該溝渠及在該閘極介電層之上。傳統沈積製程可被用來形成該替換性閘極電極、諸如CVD、ALD、及PVD。該閘 極電極層可包含譬如p型功函數金屬、諸如釕、鈀、鉑、鈷、鎳、及例如氧化釕的傳導性金屬氧化物。於一些範例組構中，二或更多金屬閘極電極層可被沈積。例如，功函數金屬可被沈積於該閘極溝渠中，隨後有充填諸如鋁或銀之金屬的合適之金屬閘極電極。圖2B'顯示源自此一選擇性RMG製程之範例閘極結構，其包含在替換性閘極介電層324之上的替換性閘極電極層326。又於其他實施例中，此RMG處理能夠稍後發生在該方法中(例如在步驟114之後)，以致該等替換性閘極材料將不遭受與步驟108至114有關的處理。
進一步參考圖1A，在絕緣體層322(與任何想要的預先觸點形成RMG製程)被提供之後，該方法繼續蝕刻108，以形成該源極/汲極接觸溝渠。任何合適之乾式及/或濕式蝕刻製程能被使用。圖2C按照一示範實施例顯示在蝕刻被完成之後的源極/汲極接觸溝渠。
該方法繼續在該電晶體結構之源極/汲極區域上沈積110三五族半導體材料層。圖2D按照一示範實施例顯示在n型及p型源極/汲極區域之上的三五族材料層317。此沈積可被非選擇性地執行，在此任何超過之三五族沈積隨後被由絕緣體層322之頂部(及閘極堆疊，如果需要)移去。於其他實施例中，該沈積可被選擇性執行，在此該三五族材料沈積係僅只在該源極/汲極區域(或其子集)上。例如，於一些示範實施例中，該沈積110係選擇性的，其中該製程包含p型區域或n型區域之遮罩，隨後有 選擇性沈積，以於該等區域的其中一者或另一者中唯一地達成沈積(例如在此p型區域承接具有第一摻雜方式的三五族材料化合物，且n型區域承接具有第二摻雜方式的三五族材料化合物)。另一選擇係，該沈積110可被產生，而在所有源極/汲極區域上具有單一成份之無摻雜的三五族材料，隨之有隨後的遮罩及摻雜，以對在下方之源極/汲極材料的摻雜型式進一步最佳化接觸電阻。另一選擇係，該沈積110可被產生，而在所有源極/汲極區域上具有單一成份之無摻雜的三五族材料，在此該無摻雜的三五族材料具有少於0.5電子伏特之能帶隙(例如InxGa1-xAs之能帶隙=0.427電子伏特，在此x=.9)。於一些此等小能帶隙案例中，該能帶隙係少於0.4電子伏特(例如InAs之能帶隙=0.36電子伏特)。於又其他此等案例中，該能帶隙係少於0.3電子伏特。於又其他此等案例中，該能帶隙係少於0.2電子伏特(例如InSb之能帶隙=0.17電子伏特)。於又其他此等案例中，該能帶隙係在一範圍內、諸如於0.1電子伏特及0.4電子伏特之間、或於0.1電子伏特及0.25電子伏特之間、或在0.25電子伏特及0.5電子伏特之間、或在0.15電子伏特及0.35電子伏特之間。然而，注意，該三五族材料不須被限制於具有少於0.5電子伏特之能帶隙。這是因為該三五族材料可被沈積，例如，以原位摻雜、擴散摻雜、或植入物摻雜，使得其被修改至該下方源極/汲極材料之摻雜型式。
於一些示範實施例中，該三五族材料層317係外延地 沈積。該三五族材料層317之厚度可為於譬如50埃至250埃之範圍中。按照一些特定之示範實施例，雖然其他實施例可具有其他層厚度，如將於此揭示內容之觀點中變得明顯。於一些實施例中，CVD製程或另一合適之沈積技術可被使用於該沈積108、或以別的方式形成該三五族材料層317。譬如，該沈積108可為在CVD、或快速熱CVD(RT-CVD)、或低壓CVD(LP-CVD)、或超高真空CVD(UHV-CVD)、或氣體源極分子束外延(GS-MBE)工具中進行，並使用三五族材料之化合物、諸如鋁、鎵、銦、磷、砷、銻、及/或其先質之組合。於一特定之此示範實施例中，該三五族材料層317係以無摻雜的銻化銦(InSb)所實施。於另一實施例中，該三五族材料層317係以摻雜有鍺之GaAs所實施，以提供1E19原子/立方公分或較高之替代鍺濃度，其導致約5E-3歐姆-公分之電阻率(或約200Mho/cm之對應的傳導率)。於任何此等實施例中，例如可有一載子氣體，諸如氫、氮、或惰性氣體(例如先質係在1-20%濃度下稀釋，而平衡為載子氣體)。於一些示範案例中，可有諸如砷化氫或TBA之砷先質、諸如TMG之鎵先質，及/或諸如TMI之銦先質。譬如，亦可有蝕刻劑氣體，諸如以鹵素為基礎之氣體、諸如氯化氫(HCl)、氯(Cl)、或溴化氫(HBr)。該三五族材料層317遍及一寬廣範圍的條件之基本沈積係可能的，並使用在譬如300℃至700℃(例如400-500℃)的範圍中之沈積溫度及例如於1托爾至760托爾的範圍中之反 應器壓力。載子及蝕刻劑之每一者能具有在10及300SCCM的範圍中之流動(典型，不超過100SCCM之流動係需要的，但一些實施例中，可自較高的流率獲益)。於一特定之示範實施例中，該沈積110係在100及1000SCCM間之範圍中的流率下進行。用於鍺之原位摻雜，例如，被稀釋的鍺烷或二鍺烷可被使用(例如該鍺烷可被稀釋於H2中，該H2在10%濃度及在10及100SCCM間之範圍的流率)。
如將在此揭示內容之觀點被了解，該三五族材料層317被沈積之選擇性能如想要地變化。於一些案例中，例如，該三五族材料層317僅只被沈積在該源極/汲極區域或該源極/汲極區域的一部份上(而非橫跨該整個結構)。任何數目之遮罩/佈圖技術可被進一步使用來界定子集合區域，以選擇性地沈積三五族材料層317。再者，其他實施例可自掩蓋譬如被暴露之多晶閘極區域或被暴露之接地分接頭區域的三五族材料層317獲益。如將會在此揭示內容之觀點中被進一步了解者，按照一些示範實施例，該三五族材料層317能被使用於在該源極及汲極區域(與其它區域，在此低接觸電阻係可想要的、諸如地分接頭區域)中顯著地實現較低的接觸電阻。
該方法接著繼續沈積112接觸電阻減少金屬及退火，且接著沈積114該源極/汲極接觸插塞。注意於此等實施例中，沒有矽化物或鍺化物。反之，任何反應係於該三五族材料層317及該金屬接觸電阻減少層325之間。圖2E 顯示該金屬接觸電阻減少層325，其於一些實施例中包含銀、鎳、鋁、鈦、金、金鍺、鎳鉑或鎳鋁、及/或其他此等電阻減少金屬或合金。如果如此想要的，其他實施例可另包含額外之層，諸如三五族材料層317及金屬接觸電阻減少層325間之黏附層。圖2F顯示該金屬接觸插塞329，其於一些實施例中包含鋁或鎢，雖然任何適當傳導性之接觸金屬或合金能被使用、諸如銀、鎳鉑或鎳鋁或鎳及鋁、或鈦之其他合金，並使用傳統的沈積製程。於一些示範案例中，具有以三五族材料層317在該源極/汲極區域及該金屬接觸電阻減少層325間之介面建構的源極/汲極之電晶體，能呈現少於100歐姆-微米之電阻率值，且於一些案例中少於90歐姆-微米，及於一些案例中少於80歐姆-微米，及於一些案例中少於75歐姆-微米，或較低。
圖1B係按照本發明之另一實施例用於形成具有低接觸電阻的電晶體結構之方法。圖3A至3C說明被形成之另一選擇範例組構。大致上，此方法係類似於參考圖1A及2A-F所敘述之方法，除了該三五族材料層317在該源極/汲極區域上之沈積係於沈積絕緣體層322之前進行以外。這是在圖1B中藉由移動該鍺材料之沈積110至在該源極/汲極界定104之後及於該絕緣體沈積106之前所有效地指示。在絕緣體沈積106之後的此結果之結構被在顯示圖3A中。注意於此示範實施例中，該三五族材料層317如何完全地覆蓋所示源極/汲極區域之每一者，而非僅只藉由該接觸溝渠所暴露之部份(如在圖2D中所最佳顯 示)。圖3B顯示在該接觸溝渠於108被蝕刻之後的結果之結構，且圖3C顯示在該金屬接觸電阻減少層325及金屬接觸插塞329被分別沈積在112及114之後的結果之結構。如將被了解，相對於參考圖1A所討論之範例方法的類似部份，該先前有關之討論係同樣地可適用於此。
非平面式組構
非平面式架構能被實施，例如，使用FinFETs或奈米線組構。FinFET係被製成環繞一薄條的半導體材料(大致上被稱為該鰭片)之電晶體。該電晶體包含該標準之場效電晶體(FET)節點，包含閘極、閘極介電層、源極區域、及汲極區域。該裝置之傳導性通道駐在該閘極介電層下方之鰭片的外部側面上/內。明確地是，電流沿著該鰭片之兩側壁(垂直於該基板表面的側面)以及沿著該鰭片之頂部(平行於該基板表面的側面)運行。因為此等組構之傳導通道本質上駐在沿著該鰭片之三處不同外部、平面式區域，此一FinFET設計有時候被稱為三閘極FinFET。其他型式之FinFET組構係亦可用的，諸如所謂之雙閘極FinFETs，其中該傳導通道主要僅只駐在沿著該二鰭片之側壁(且不沿著該鰭片之頂部)。奈米線電晶體(有時候被稱為環繞式閘極FET)被很類似地建構，但代替鰭片，奈米線(例如矽或SiGe或鍺奈米線)被使用，且該閘極材料大致上在所有側面上圍繞該通道區域。取決於該特別之設計，奈米線電晶體具有例如四個有效閘極。
圖4A-4E之每一者顯示按照本發明之一實施例所建構的示範非平面式架構之立體圖。明確地是，圖4A-B之每一者顯示FinFET電晶體結構之立體圖，且圖4C-E顯示範例奈米線通道電晶體結構。該等圖面之每一者現在將依序被討論。
如能被看見，圖4A所示之範例非平面式組構被以三閘極裝置實施，其之每一者包含具有半導體本體或鰭片660的基板600，該鰭片由該基板600延伸經過隔離區域620。閘極電極640被形成在該鰭片660的三表面之上，以形成三個閘極。硬罩幕690被形成在該閘極電極640之頂部上。閘極間隔層670、680被形成在該閘極電極640之相反側壁上。p型源極區域包括被形成在凹入的源極介面650及在一鰭片660側壁上的外延區域631a，且汲極區域包括被形成在凹入的源極介面650及在該相反之鰭片660側壁(未示出)上的外延區域631a。此外，n型源極區域包括被形成在凹入的源極介面650及在一鰭片660側壁上的外延區域631b，且汲極區域包括被形成在凹入的源極介面650及在該相反之鰭片660側壁(未示出)的外延區域631b。三五族材料蓋層641係沈積在該源極/汲極區域631a(亦即，外延區域631a)及631b(亦即，外延區域631b)之上。注意該三五族材料蓋層641可被提供於該凹入(尖部)區域中，但於其他實施例中係剛好設在該源極/汲極區域之上(且不在該等凹入區域中)。於一實施例中，該等隔離區域620係使用傳統技術所形成之淺溝渠 隔離(STI)區域，諸如蝕刻該基板600以形成溝渠，且接著將氧化物材料沈積至該等溝渠上，以形成該等STI區域。該等隔離區域620可被由任何合適之介電/絕緣材料、諸如SiO2所製成。該先前相對於該基板300之討論係同樣地可適用於此(例如基板600可為矽基板、或諸如SOI基板之XOI基板、或多層式基板)。如將在此揭示內容之觀點中被了解，傳統製程及形成技術能被使用於製造該FinFET電晶體結構。然而，及按照本發明之一示範實施例，該等源極/汲極區域631a及631b與三五族材料蓋層641之結構能被實施，例如，使用以三五族材料層(用於641)帽蓋之原位摻雜的矽或SiGe(用於631a及631b)。如將被進一步了解，注意對於該三閘極組構之另一選擇係雙閘極架構，其包含在該鰭片660的頂部上之介電/絕緣層。進一步注意圖4A所示該源極/汲極區域631(a及b)之範例形狀係不意欲將所主張之發明限制於任何特別之源極/汲極型式或形成製程，且其他源極/汲極形狀(p與n兩者)以此揭示內容之觀點將變得明顯例如圓形、正方形或長方形之p及n源極/汲極區域可被實施)。
如將應被了解，圖4A所示之源極/汲極區域631(a及b)係使用替換性處理(例如蝕刻、外延沈積等)所形成。然而，於其他實施例中，源極/汲極區域631可為由該基板600材料本身所形成之鰭片660的一部份，如在圖4B所最佳顯示者。僅只一源極/汲極區域631被顯示，但 極多此等區域可被以類似方式實施(包含n型及p型源極/汲極區域兩者)。三五族材料蓋層641係以類似方式沈積在該等源極/汲極區域631之上，如先前參考圖4A所討論。相對於圖4A所提供之另一有關討論係亦同樣地可適用於此，如將應被了解。
另一選擇係該奈米線通道架構可包含譬如基板600材料之臺座，奈米線660(例如矽或SiGe)係在該基板上生長或以別的方式提供，如在圖4C中所最佳顯示。類似於圖4B所示之鰭片結構，該奈米線660包含源極/汲極區域631(僅只一源極/汲極區域被顯示，但多數此等區域可被實施，包含p型及n型，如先前所說明)。就像以一鰭片結構，該源極/汲極區域631可為由基板600材料(該等奈米線由其所製成)或一或多個替換性材料(例如矽或SiGe)所形成。該三五族材料蓋層641能被提供例如圍繞奈米線660之所有該等源極/汲極區域631、或該奈米線660的僅只一部份(例如全部，除了該臺座上之部份以外)。圖4D說明具有多數奈米線660之奈米線組構(在此示範案例中有二奈米線)。如能被看見，一奈米線660被提供於基板600之凹部中，且另一奈米線有效地漂移在該三五族材料蓋層641中。該等對應的源極/汲極區域631被以直立之交叉影線所顯示，並可為p型及/或n型源極/汲極區域。圖4E亦說明一具有多數奈米線660之奈米線組構，但於此示範案例中，非活性材料632於該奈米線形成製程期間不由該等個別奈米線之間被移去，其可使用各 種傳統技術被執行，如將在此揭示內容之觀點中被了解。如此，一奈米線660被提供於該基板600之凹部中，且另一奈米線660有效地安坐在該材料632之頂部上。注意該等奈米線660係主動經過該通道，但該632材料不是。該三五族材料蓋層641層被提供圍繞該等奈米線660之所有其他被暴露表面。該等對應的源極/汲極區域631被以直立之交叉影線所顯示，並可為p型及/或n型源極/汲極區域。
示範系統
圖5說明以按照本發明之示範實施例所建構的一或多個電晶體結構所實施之計算系統1000。如能被看見，該計算系統1000容置一主機板1002。該主機板1002可包含許多零組件，包含但不限於處理器1004及至少一通訊晶片1006，其每一者可被物理地及電耦接至該主機板1002、或以別的方式整合在其中。如將應了解，該主機板1002可為譬如任何印刷電路板，不論是否為主板或安裝在主板上之子板或系統1000之唯一電路板等。視其應用而定，計算系統1000可包含一或多個其他零組件，其可或不能被物理地及電耦接至該主機板1002。這些其他零組件可包含、但不被限制於揮發性記憶體(例如DRAM)、非揮發性記憶體(例如ROM)、圖形處理器、數位信號處理器、密碼處理器、晶片組、天線、顯示器、觸控螢幕顯示器、觸控螢幕控制器、電池、音頻壓縮編碼、視頻壓縮編碼、 功率放大器、全球定位系統(GPS)裝置、羅盤、加速計、迴轉儀、喇叭、照相機、及大量儲存裝置(諸如硬碟機、光碟(CD)、數位多用途磁碟(DVD)等)。計算系統1000中所包含之任何零組件可包含如在此中所敘述的一或多個電晶體結構(例如在n型及p型源極/汲極區域兩者之上具有一小能帶隙或適當地摻雜的三五族材料層，以提供較低的接觸電阻/改良的傳導性)。這些電晶體結構能例如被使用於提供板上處理器快取或記憶體陣列。於一些實施例中，多數功能可被整合進入一或多個晶片(例如，注意該通訊晶片1006可為該處理器1004的一部份或以別的方式整合進入該處理器1004)。
該通訊晶片1006能夠無線通訊，用於資料之傳送至該計算系統1000及由該計算系統1000傳送資料。該“無線”一詞及其衍生詞可被用來敘述電路、裝置、系統、方法、技術、通訊通道等，其可經過該調制的電磁輻射之使用經過非固體媒介溝通資料。該名詞不會隱含該相關裝置未含有任何電線，雖然於一些實施例中它們可能沒有電線。該通訊晶片1006可實施許多無線標準或協定之任一者，包含、但不限於Wi-Fi(IEEE 802.11家族)、WiMAX(IEEE 802.16家族)、IEEE 802.20、長期演進技術(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、Bluetooth、其衍生者、以及被規定為3G、4G、5G、及超出者的任何其他無線協定。該計算系統1000可包含複數 通訊晶片1006。例如，第一通訊晶片1006可被專用於較短範圍無線通訊，諸如Wi-Fi及Bluetooth，且第二通訊晶片1006可被專用於較長範圍無線通訊、諸如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO、及其他者。
該計算系統1000之處理器1004包含被封裝在該處理器1004內之積體電路晶粒。於本發明之一些實施例中，該處理器之積體電路晶粒包含板子上記憶體電路系統，其被以如在此中所敘述之一或多個CMOS電晶體結構實施。該“處理器”一詞可意指任何裝置或裝置的一部份，其處理例如來自暫存器及/或記憶體之電子資料，以將該電子資料轉變成其他可被儲存於暫存器及/或記憶體中之電子資料。
該通訊晶片1006亦可包含被封裝在該通訊晶片1006內之積體電路晶粒。按照一些此等示範實施例，該通訊晶片之積體電路晶粒包含以如在此中所敘述之一或多個電晶體結構所實施的一或多個裝置，(例如晶片上處理器或記憶體)。如將在此揭示內容之觀點中被了解，注意該多標準無線能力可被直接地整合進入該處理器1004(例如在此任何晶片1006之功能性被整合進入處理器1004，而非具有分開之通訊晶片)。進一步注意該處理器1004可為一具有此無線能力之晶片組。簡言之，任何數目之處理器1004及/或通訊晶片1006能被使用。同樣地，任一晶片或晶片組能具有被整合在其中之多數功能。
於各種措施中，該計算系統1000可為膝上型電腦、上網型電腦、筆記型電腦、智慧型手機、平板電腦、個人數位助理器(PDA)、超級移動PC、行動電話、桌上型式電腦、伺服器、印表機、掃描器、監視器、機上盒、娛樂控制單元、數位照相機、手提式音樂播放器、或數位錄影機。於進一步措施中，該系統1000可為任何另一電子裝置，其處理資料或採用如在此中所敘述之低接觸電阻電晶體裝置(例如具有p及n型裝置的CMOS裝置)。
極多實施例將變得明顯，且在此中所敘述之特色可被組合在任何數目的組構中。本發明的一示範實施例提供半導體積體電路。該積體電路包含具有許多通道區域的基板，及在每一通道區域上方之閘極電極，其中閘極介電層被提供於每一閘極電極及對應通道區域之間。該積體電路另包含於該基板中及毗連對應通道區域的p型源極/汲極區域、及於該基板中及毗連對應通道區域之n型源極/汲極區域。該積體電路另包含在該p型源極/汲極區域的至少一部份及該n型源極汲極區域的一部份上之三五族半導體材料層。該積體電路另包含在該三五族半導體材料層上之金屬觸點。於一些案例中，該三五族半導體材料層係無摻雜的。於一些示範案例中，該三五族半導體材料層具有少於0.5電子伏特之能帶隙。於其他示範案例中，該三五族半導體材料層具有少於0.2電子伏特的能帶隙。於一些案例中，該三五族半導體材料層係摻雜的。於一些此等案例中，該三五族半導體材料層具有一與用於該p型及n型 源極/汲極區域兩者相同之摻雜方式。於其他此等案例中，該三五族半導體材料層具有用於該p型源極/汲極區域之第一摻雜方式及用於該n型源極/汲極區域的第二摻雜方式。該三五族半導體材料層能譬如被摻雜以一或多個兩性摻雜劑(C、Si、Ge、及/或Sn)。於一此案例中，該三五族半導體材料層係以一或多個兩性摻雜劑摻雜至大於1E18原子/立方公分替代濃度。該裝置能譬如以平面式電晶體架構、或非平面式電晶體架構被實施。於一此等案例中，該非平面式電晶體架構包含FinFET電晶體及/或奈米線電晶體之至少一者。於一些案例中，該p型及n型源極/汲極區域包括矽、鍺、或其合金。本發明之另一實施例提供一電子裝置，其包含具有如在此段落中不同地界定之一或多個積體電路的印刷電路板。於一此等案例中，該一或多個積體電路包括通訊晶片及/或處理器之至少一者。該裝置可為譬如計算裝置。
本發明之另一實施例提供一裝置，包括具有許多通道區域之含矽基板，及在每一通道區域上方之閘極電極，其中閘極介電層被提供於每一閘極電極及對應通道區域之間。該裝置另包含於該基板中及毗連對應通道區域的p型源極/汲極區域，該等p型源極/汲極區域包括矽、鍺、或其合金；及於該基板中且毗連對應通道區域的n型源極/汲極區域，該等n型源極/汲極區域包括矽、鍺、或其合金。該裝置另包含在該p型源極/汲極區域的至少一部份及該n型源極汲極區域的一部份上之三五族半導體材料 層，及一在該三五族半導體材料層上用於該p型及n型源極/汲極區域之每一者的金屬觸點。按照一特定之示範實施例，InSb在Si、SiGe合金及Ge源極/汲極區域上之三五族材料沈積係藉由模擬所預測，以對傳導給予很低的障礙。於此揭示內容之觀點中，其他合適之三五族材料層將變得明顯。於一些案例中，該三五族半導體材料層係無摻雜的。於一些案例中，該三五族半導體材料層具有少於0.5電子伏特之能帶隙。於一些案例中，該三五族半導體材料層係摻雜的。於一些此等案例中，該三五族半導體材料層具有一與用於該p型及n型源極/汲極區域相同之摻雜方式。於其他此等案例中，該三五族半導體材料層具有用於該p型源極/汲極區域之第一摻雜方式及用於該n型源極/汲極區域之第二摻雜方式。於一些案例中，該三五族半導體材料層係以諸如Ge的一或多個兩性摻雜劑摻雜(例如摻雜至大於1E18原子/立方公分替代濃度)。
本發明之另一實施例提供一用於形成半導體裝置之方法。該方法包含提供具有許多通道區域的基板，及提供在每一通道區域上方之閘極電極，其中閘極介電層被提供於每一閘極電極及對應通道區域之間。該方法另包含提供於該基板中及毗連對應通道區域的p型源極/汲極區域，且提供於該基板中及毗連對應通道區域之n型源極/汲極區域。該方法其另包含提供在該p型源極/汲極區域的至少一部份及該n型源極汲極區域的一部份上之三五族半導體材料層。該方法另包含提供一在該三五族半導體材料層上 之金屬觸點。
為著要說明及敘述之目的，本發明之實施例的前面敘述已被呈現。其係不意指為詳盡的或將本發明限制於所揭示之精確形式。以此揭示內容之觀點，很多修改及變動係可能的。其係意欲使本發明之範圍不被此詳細敘述所限制，反之被至此為止所附的申請專利範圍所限制。
300‧‧‧基板
302‧‧‧閘極介電層
304‧‧‧閘極電極
306‧‧‧硬罩幕層
310‧‧‧間隔層
317‧‧‧三五族材料層
322‧‧‧絕緣體層
324‧‧‧閘極介電層
325‧‧‧金屬接觸電阻減少層
326‧‧‧閘極電極層
329‧‧‧金屬接觸插塞
600‧‧‧基板
620‧‧‧隔離區域
631‧‧‧源極/汲極區域
631a‧‧‧外延區域
631b‧‧‧外延區域
632‧‧‧非活性材料
640‧‧‧閘極電極
641‧‧‧三五族材料蓋層
650‧‧‧源極介面
660‧‧‧鰭片
670‧‧‧閘極間隔層
680‧‧‧閘極間隔層
690‧‧‧硬罩幕
1000‧‧‧計算系統
1002‧‧‧主機板
1004‧‧‧處理器
1006‧‧‧通訊晶片
圖1A係用於按照本發明之實施例形成具有低接觸電阻的電晶體結構之方法。
圖1B係用於按照本發明之另一實施例形成具有低接觸電阻的電晶體結構之方法。
圖2A至2F說明當按照本發明之實施例執行圖1A之方法時所形成之結構。
圖3A至3C說明當按照本發明之另一實施例執行圖1B之方法時所形成之另一選擇結構。
圖4A-E之每一者顯示按照本發明的一實施例所建構之非平面式電晶體架構之立體圖。
圖5說明按照本發明之示範實施例提供一或多個電晶體結構的計算系統。
如將被了解，該等圖面不須按照一定比例描繪或意欲將所申請之發明限制於所示特定組構。例如，雖然一些圖面大致上指示直線、直角、及平滑表面，電晶體結構的實際措施可具有少於完美之直線、直角，且一些特色可具有 表面布局或以別的方式為非平滑的，而給予所使用之處理設備及技術的真實世界限制。總之，該等圖面僅只被提供於顯示範例結構。
300‧‧‧基板
302‧‧‧閘極介電層
304‧‧‧閘極電極
306‧‧‧硬式罩幕
317‧‧‧三五族材料層
322‧‧‧絕緣體層
325‧‧‧接觸電阻減少金屬
329‧‧‧金屬接觸插塞

Claims (25)

  1. 一種半導體積體電路，包括：基板，具有許多通道區域；閘極電極，在每一通道區域上方，其中閘極介電層被提供於每一閘極電極及對應通道區域之間；p型源極/汲極區域，其包含矽於該基板中及毗連對應通道區域；n型源極/汲極區域，其包含矽於該基板中及毗連對應通道區域；摻雜的三五族半導體材料層，在該p型源極/汲極區域之至少一部份與該n型源極/汲極區域的一部份上；及在該三五族半導體材料層上之金屬接觸。
  2. 如申請專利範圍第1項之半導體積體電路，其中該摻雜的三五族半導體材料層包括在其上的金屬接觸，用於該p型及n型源極/汲極區域之各者。
  3. 如申請專利範圍第1或2項之半導體積體電路，其中該摻雜的三五族半導體材料層具有少於0.5電子伏特之能帶隙。
  4. 如申請專利範圍第1項之半導體積體電路，其中該摻雜的三五族半導體材料層具有少於0.2電子伏特之能帶隙。
  5. 如申請專利範圍第1項之半導體積體電路，其中該三五族半導體材料層包含銻化銦、鋁、鎵、銦、磷、砷以及銻之至少其中一者。
  6. 如申請專利範圍第1項之半導體積體電路，其中該摻雜的三五族半導體材料層具有一摻雜方式，其用於該p型及n型源極/汲極區域兩者係相同的。
  7. 如申請專利範圍第1項之半導體積體電路，其中該摻雜的三五族半導體材料層具有用於該p型源極/汲極區域之第一摻雜方式及用於該n型源極/汲極區域的第二摻雜方式。
  8. 如申請專利範圍第1項之半導體積體電路，其中該摻雜的三五族半導體材料層係以一或多個兩性摻雜劑摻雜，該一或多個兩性摻雜劑包含碳、矽、鍺以及錫摻雜劑之至少其中一者。
  9. 如申請專利範圍第8項之半導體積體電路，其中該摻雜的三五族半導體材料層係以一或多個兩性摻雜劑摻雜至大於1E18原子/立方公分替代濃度。
  10. 如申請專利範圍第1項之半導體積體電路，其中該積體電路係以平面式電晶體架構施行。
  11. 如申請專利範圍第1項之半導體積體電路，其中該積體電路係以非平面式電晶體架構施行。
  12. 如申請專利範圍第11項之半導體積體電路，其中該非平面式電晶體架構包括FinFET(鰭式場效)電晶體及/或奈米線電晶體之至少一者。
  13. 如申請專利範圍第1項之半導體積體電路，其中該p型及n型源極/汲極區域更包括鍺。
  14. 一種電子裝置，包括： 印刷電路板，具有如申請專利範圍第1-13項的任一項所界定之一或多個積體電路。
  15. 如申請專利範圍第14項之電子裝置，其中該一或多個積體電路包括通訊晶片及/或處理器之至少一者。
  16. 如申請專利範圍第14或15項之電子裝置，其中該裝置為計算裝置。
  17. 一種裝置，包括：含矽基板，具有許多通道區域；閘極電極，在每一通道區域上方，其中閘極介電層被提供於每一閘極電極及對應通道區域之間；p型源極/汲極區域，其包含矽於該基板中及毗連對應通道區域，該p型源極/汲極區域包括矽、鍺、或其合金；n型源極/汲極區域，其包含矽於該基板中及毗連對應通道區域，該n型源極/汲極區域包括矽、鍺、或其合金；摻雜的三五族半導體材料層，在該p型源極/汲極區域之至少一部份與該n型源極/汲極區域的一部份上；及在該三五族半導體材料層上之金屬接觸，用於p型及n型源極/汲極區域之每一者。
  18. 如申請專利範圍第17項之裝置，其中該裝置係以平面電晶體架構建置。
  19. 如申請專利範圍第17項之裝置，其中該裝置係以非平面電晶體架構建置。
  20. 如申請專利範圍第17項之裝置，其中該摻雜的三五族半導體材料層具有一摻雜方式，其用於該p型及n型源極/汲極區域兩者係相同的。
  21. 如申請專利範圍第17項之裝置，其中該摻雜的三五族半導體材料層具有用於該p型源極/汲極區域之第一摻雜方式及用於該n型源極/汲極區域的第二摻雜方式。
  22. 如申請專利範圍第17至21項之裝置，其中該摻雜的三五族半導體材料層係以一或多個兩性摻雜劑摻雜，該一或多個兩性摻雜劑包含含碳、矽、鍺以及錫摻雜劑之至少其中一者。
  23. 如申請專利範圍第22項之裝置，其中該摻雜的三五族半導體材料層係以一或多個兩性摻雜劑摻雜至大於1E18原子/立方公分替代濃度。
  24. 如申請專利範圍第17項之裝置，其中該摻雜的三五族半導體材料層具有少於0.5電子伏特之能帶隙。
  25. 一種用於形成半導體積體電路之方法，包括：提供一具有許多通道區域之基板；在每一通道區域上方提供一閘極電極，其中一閘極介電層被提供於每一閘極電極與對應通道區域之間；於該基板中及毗連對應通道區域提供包含矽的p型源極/汲極區域；於該基板中及毗連對應通道區域提供包含矽的n型源極/汲極區域；在該p型源極/汲極區域之至少一部份與該n型源極/ 汲極區域的一部份上提供摻雜的三五族半導體材料層；及在該三五族半導體材料層上提供一金屬接觸。
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US20160329431A1 (en) 2016-11-10
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