TWI603451B - 用於降低接觸電阻之自我對準的接點金屬化 - Google Patents

用於降低接觸電阻之自我對準的接點金屬化 Download PDF

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TWI603451B
TWI603451B TW104144479A TW104144479A TWI603451B TW I603451 B TWI603451 B TW I603451B TW 104144479 A TW104144479 A TW 104144479A TW 104144479 A TW104144479 A TW 104144479A TW I603451 B TWI603451 B TW I603451B
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TW201628155A (zh
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葛蘭 葛雷斯
安拿 莫希
塔何 甘尼
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英特爾股份有限公司
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Description

用於降低接觸電阻之自我對準的接點金屬化
本發明係關於一種用於降低接觸電阻之自我對準的接點金屬化。
包括電晶體、二極體、電阻器、電容器、及形成於半導體基板上的其他被動及主動電子裝置之電路裝置的提昇性能典型地為該些裝置之設計、製造、及作業期間考慮的主要因素。例如，在金屬氧化物半導體(MOS)電晶體半導體裝置之設計及製造或形成期間，諸如用於互補金屬氧化物半導體(CMOS)中者，除了已知外部電阻Rext以外，其通常希望使與接點相關之寄生電阻最小。減少的Rext致能來自相等電晶體設計之更高電流。
102、104、106、108、110、112、114、116、118‧‧‧步驟
300、600‧‧‧基板
302、324‧‧‧閘極介電層
304、640‧‧‧閘極電極
306、690‧‧‧硬遮罩
310‧‧‧間隔器
317‧‧‧p型鍺層
319‧‧‧III-V材料層
322‧‧‧絕緣體層
325‧‧‧金屬接觸電阻降低金屬
326‧‧‧置換閘極電極層
329‧‧‧接點插銷金屬
620‧‧‧隔離區
631‧‧‧源極/汲極區
631a、631b‧‧‧外延區
632‧‧‧材料
641‧‧‧蓋體層
641a‧‧‧p型鍺蓋體層
641b‧‧‧n型III-V蓋體層
650‧‧‧內凹源極介面
660‧‧‧鰭片
660‧‧‧奈米線
670、680‧‧‧閘極間隔器
1000‧‧‧計算系統
1002‧‧‧主機板
1004‧‧‧處理器
1006‧‧‧通訊晶片
圖1A為依據本發明之實施例之形成具低接觸電阻之電晶體結構的方法。
圖1B為依據本發明之另一實施例之形成具低接觸電 阻之電晶體結構的方法。
圖2A至2I描繪依據本發明之實施例之結構，其係當實施圖1A之方法時形成。
圖3A至3C描繪依據本發明之另一實施例之替代結構，其係當實施圖1B之方法時形成。
圖4A-E各顯示依據本發明之一實施例組配之非平面電晶體架構的透視圖。
圖5描繪依據本發明之示範實施例之使用一或多個電晶體結構實施的計算系統。
【發明內容及實施方式】
所揭露之技術用於形成相對於習知裝置具有降低的寄生接觸電阻之電晶體裝置。在若干示範實施例中，組配MOS結構使得在接點凹槽形成之前或之後以p型鍺覆蓋p-MOS源極/汲極區，並於n-MOS區及覆蓋鍺之p-MCS區之上提供n型III-V半導體材料層。因此，覆蓋p型鍺之p-MOS源極/汲極區相對高於n-MOS矽源極/汲極區。接著可實施向後蝕刻程序以利用n型及p型區之間之源極/汲極高度差來自我對準接點類型，而暴露n-MOS區上之III-V材料及p-MOS區上之鍺。技術可進一步包括降低金屬沉積之接觸電阻，其後為鍺化物/III-V晶粒形成退火，接著為金屬接點插銷沉積，其後為拋光以移除多餘金屬而隔離每一接點凹槽與相鄰者。
總體概述
如先前所說明，電晶體中提昇的驅動電流可藉由降低裝置電阻予以達成。接觸電阻為裝置之整體電阻之一組件。典型電晶體接點堆疊包括例如矽或矽鍺(SiGe)源極/汲極層、矽化物/鍺化物層、鈦氮化物附著層、及鎢接點/插銷。諸如鎳、鉑、鈦、鈷等金屬之矽化物及鍺化物在鎢插銷沉積之前可形成於源極-汲極區上。在該等組態中，接觸電阻為相對高並有效地藉由矽或SiGe價帶校準侷限於接點金屬中銷連接級。典型地，使用產業標準矽化物，諸如鎳(或其他合適矽化物，諸如、鈦、鈷、鋁、或鉑)，此導致n型接點之約0.5eV或更高及p型接點之約0.3eV或更高之帶錯位及相應高電阻。
因而及依據本發明之示範實施例，提供p型源極/汲極及接點金屬之間之中間p型鍺層，及提供n型源極/汲極及接點金屬之間之中間n型III-V材料層。假設p型源極/汲極上之鍺充分厚，後續向後蝕刻程序接著在接點凹槽之底部導致暴露表面，接點凹槽包括n型源極/汲極上之III-V材料區域及p型源極/汲極上之鍺區域。標準接點形成程序流程可從此展開。
源極/汲極區及接點金屬之間之中間III-V材料及鍺層顯著地降低帶錯位值及接觸電阻。在若干示範狀況下，提供約3X或更佳的接觸電阻降低(相對於類似組配之習知接點堆疊，但無III-V材料及鍺之中間層)。STEM亮場模式中該等接點凹槽之透射電子顯微鏡(TEM)截面可 用以顯示例如大體上匹配凹槽形狀(例如，凹槽底部形狀)之III-V材料。III-V材料具有相對於矽或SiGe之對比。同樣地，TEM截面或二次離子質譜(SIMS)設定檔可用以顯示p型區上之鍺濃度，因為矽及SiGe之外延合金的設定檔可容易地與鍺濃度設定檔區分。成分分析及映射可用以顯示使用之材料特性。因而，根據分析，依據本發明之實施例組配之結構，組成將有效地顯示包含以下組合之n型III-V半導體材料的額外層，例如鋁(Al)、鎵(Ga)、銦(In)、磷(P)、砷(As)、及/或銻(Sb)，連同n型源極/汲極區上之任何n型摻雜劑(例如，矽、鍺、碲、或其他合適n型摻雜劑)及p型區上之p型鍺層(硼-摻雜、或其他合適p型摻雜劑)，並將展示接觸電阻，其低於使用習知接點程序製成之裝置的接觸電阻。如將理解的，具有高性能接點需求之任何數量半導體裝置或電路可獲益於文中所提供之低電阻接點技術。
可以各式方式達成加工程序期間P型及n型選擇性。在一實施例中，例如藉由具有於PMOS區沉積期間掩蔽之NMOS區，可避免NMOS源極/汲極位置上之沉積，且相對於PMOS選擇性反之亦然。在另一實施例中，可同步開啟NMOS及PMOS區，但藉由相應凹槽，沉積僅發生於各個NMOS及PMOS區中。如將進一步理解的，鑒於此揭露，選擇性可包括自然選擇性。例如，當p型摻雜鍺(例如，硼摻雜濃度超過1E20 cm-3)於p型SiGe或矽源極/汲極區上生長時，便不在諸如二氧化矽(SiO2)或氮 化矽(SiN)之絕緣體表面上生長；亦不在例如大量暴露之磷摻雜矽n型區上生長。類似地，n型摻雜III-V材料將為以下之任何組合，例如，Al、Ga、In、P、As、及/或Sb(例如，以>1E17 cm-3之濃度的矽、鍺、硫、碲等摻雜)，其將在n型SiGe或矽源極/汲極區及p型鍺源極/汲極區上生長，但將不在諸如SiO2或SiN之絕緣體表面上生長。當選擇性不可能或未採用或需要時，則可移除多餘沉積材料，例如使用平面化/拋光及/或蝕刻。
進一步請注意，可採用中間p型鍺及n型III-V材料層以改進任何數量電晶體結構及組態中的接觸電阻，包括平面、凸起源極/汲極、非平面(例如，奈米線電晶體及鰭片電晶體，諸如雙閘極及三閘極電晶體結構)，以及應變及未應變通道結構。此外，電晶體結構可包括源極及汲極尖端區，其經設計例如以減少電晶體之整體電阻，同時改進短通道效應(SCE)，如有時之作法。源極/汲極區本身亦可改變。在若干示範實施例中，電晶體結構包括矽之摻雜劑植入之源極/汲極區或外延(或多晶)置換源極/汲極區、SiGe合金、或MOS結構中之名義上純鍺膜(例如，具小於10%矽者)。在任何該等實施中，依據本發明之實施例，例如硼摻雜鍺(或其他合適p型鍺)之層或蓋體可直接形成於p型源極/汲極區之上，且例如矽摻雜III-V材料(或其他合適n型III-V材料)之層或蓋體可直接形成於n型源極/汲極區之上。接點金屬(或金屬系列)接著可沉積，並可實施後續反應(退火)以形成金 屬鍺化物/III-V晶粒源極及汲極接點。接著可沉積金屬插銷。如鑒於此揭露將理解的，中間p型鍺及/或n型III-V層可直接形成於電晶體結構之其他部分上，以及如果需要的話形成於諸如多閘極及/或接地分接區上。如文中所說明，任何數量結構特徵可結合p型鍺及n型III-V材料層使用。
請注意，在若干實施例中，可留下未摻雜之III-V半導體材料，特別是相對於具有約0.5eV以下帶隙的III-V材料，因為在室溫下該等小帶隙材料中載子之熱產生足以致能高導電性。在使用摻雜的其他實施例中，諸如使用具有任意帶隙之III-V材料者，可以若干方式實施摻雜，包括原地及易地摻雜技術(例如，類似於用於p型區上之鍺層的摻雜技術)。若干該等實施例採用具有具柱IV摻雜劑之充分高摻雜級的III-V材料，諸如碳、矽、鍺、或錫。在極高高摻雜級(例如，大於1E17原子/cm3置換濃度)，該些兩性摻雜劑有助於價帶及導帶中之載子，藉以提昇二載子類型之載子濃度。在若干該等狀況下，摻雜係原地實施。在其他實施例中，沉積固有III-V材料層，之後為易地摻雜程序，諸如離子植入或擴散摻雜，以便提供所欲導電性(例如，具例如100至500S/cm之值的導電性)。
方法論及架構
圖1A為依據本發明之實施例之形成具低接觸電阻之 電晶體結構的方法。圖2A至2I描繪實施該方法及依據若干實施例所形成之示範結構。
示範方法包括在102，於其上可形成MOS裝置之半導體基板上形成一或多個閘極堆疊。MOS裝置可包含NMOS或PMOS電晶體，或NMOS及PMOS電晶體(例如，用於CMOS裝置)。圖2A顯示示範結果結構，其在本狀況下包括形成於相同基板300上並藉由淺凹槽隔離(STI)分離的NMOS及PMOS電晶體。p型及n型區之間之隔離亦可使用其他合適形式。可以看出，每一閘極堆疊係形成於電晶體之通道區之上，並包括閘極介電層302、閘極電極304、可選硬遮罩306、及形成鄰近於閘極堆疊之間隔器310。
閘極電介質302可為例如任何合適氧化物，諸如二氧化矽(SiO2)或高-k閘極電介質材料。高-k閘極電介質材料之範例包括例如鉿氧化物、給矽氧化物、鑭氧化物、鑭鋁氧化物、鋯氧化物、鋯矽氧化物、鉭氧化物、鈦氧化物、鋇鍶鈦氧化物、鋇鈦氧化物、鍶鈦氧化物、釔氧化物、鋁氧化物、鉛鈧鉭氧化物、及鉛鋅鈮酸鹽。在若干實施例中，當使用高-k材料時，可在閘極介電層302上實施退火程序，以改進其品質。在若干特定示範實施例中，高-k閘極介電層302可具有介於5Å至約100Å厚(例如10Å)之厚度。在其他實施例中，閘極介電層302可具有一單層氧化物材料之厚度。通常，閘極電介質302之厚度應足以電隔離閘極電極304與源極及汲極接點。在若干實 施例中，可於高-k閘極介電層302上實施額外程序，諸如退火程序以改進高-k材料之品質。
儘管亦可使用其他合適閘極電極材料，閘極電極304材料可為例如多晶矽、氮化矽、碳化矽、或金屬層(例如鎢、氮化鈦、鉭、氮化鉭)。在若干示範實施例中，閘極電極304材料可為之後移除用於置換金屬閘極(RMG)程序之犧牲材料，其具有厚度介於10Å至500Å(例如100Å)。
可選閘極硬遮罩層306可用以提供某利益，或於處理期間使用，諸如保護閘極電極304免於後續蝕刻及/或離子植入程序。硬遮罩層306可使用典型硬遮罩材料形成，諸如二氧化矽、氮化矽、及/或其他習知絕緣體材料。
閘極堆疊可如習知般形成，或使用任何合適訂製技術(例如，如圖2A中所示習知圖案化程序，以蝕刻掉閘極電極及閘極介電層部分，而形成閘極堆疊)。閘極電介質302及閘極電極304材料之每一者可使用例如習知沉積程序形成，諸如化學汽化沉積(CVD)、原子層沉積(ALD)、旋塗沉積(SOD)、或物理汽化沉積(PVD)。亦可使用替代沉積技術，例如閘極電介質302及閘極電極304材料可為熱生長。如鑒於此揭露將理解的，任何數量其他合適材料、幾何、及形成程序可用以實施本發明之實施例，以便提供低接觸電阻電晶體裝置或如文中所說明之結構。
可使用例如習知材料形成間隔器310，諸如矽氧化 物、氮化矽、或其他合適間隔器材料。間隔器310之寬度通常可根據所形成電晶體之設計需求挑選。然而，依據若干實施例，間隔器310之寬度未遭受源極及汲極外延尖端之形成強加的設計限制，於源極/汲極尖端區中提供充分高硼摻雜鍺含量。
任何數量合適基板可用以實施基板300，包括塊體基板、絕緣體基板上半導體(XOI，其中X為半導體材料，諸如矽、鍺、或富鍺矽)、及多層結構，包括其上可於後續閘極圖案化程序之前形成鰭片或奈米線之該些基板。在若干特定示範狀況下，基板300為鍺或矽或SiGe塊體基板，或氧化物基板上鍺或矽或SiGe。儘管此處說明可形成基板300之材料的少數範例，可作為其上可建立低電阻電晶體裝置之基礎的其他合適材料落於所主張本發明之精神及範圍內。
進一步參照圖1A，在形成一或多個閘極堆疊之後，繼續方法且在104，定義電晶體結構之p型及n型源極/汲極區。可以任何數量合適程序及組態實施源極/汲極區。例如，源極/汲極區可植入、蝕刻及外延填充，可為凸起、矽或鍺或SiGe合金、p型及/或n型，並具有平面或鰭片或線形擴散區。例如，在若干該等示範狀況下，可使用植入/擴散程序或蝕刻/沉積程序形成源極及汲極區。在前者程序中，諸如硼、鋁、銻、磷、或砷之摻雜劑可為離子植入基板300以形成源極及汲極區。離子植入程序之後典型地為退火程序，其啟動摻雜劑並亦可致使離子 進一步擴散進入基板300。在後者程序中，首先可蝕刻基板300以於源極及汲極區的位置形成凹部。接著可實施外延沉積程序而以諸如矽鍺或碳化矽之矽合金填充凹部，藉以形成源極及汲極區。在若干實施中，外延沉積之矽合金可以諸如硼、砷、或磷之摻雜劑原地或易地摻雜，取決於希望該區為p型或n型功能。
在圖2A-2I中所示之示範實施例中，已蝕刻基板300以提供下切閘極電介質302之腔以及各個尖端區域。已填充腔及尖端區域提供源極/汲極區及可選尖端區，亦稱為源極-汲極延伸。依據若干特定示範實施例，其中基板300為矽塊體或絕緣體上矽(SOI)基板，以原地摻雜矽或SiGe或鍺填充源極及汲極腔連同其各個尖端區域，藉以形成源極及汲極區(連同其各個外延尖端)。相對於材料(例如，摻雜或未摻雜Si、Ge、SiGe)、摻雜劑(例如，硼、砷、或磷)、及幾何(例如，源極/汲極層之厚度可介於例如從50至500nm，以便提供平坦或凸起源極/汲極區)，此處可使用任何數量源極/汲極層組態。
如鑒於此揭露將理解的，可以本發明之實施例實施任何數量其他電晶體特徵。例如，通道可為應變或未應變，源極/汲極區可或不可包括形成於相應源極/汲極區及通道區之間區域中之尖端區。在這個意義上說，不論電晶體結構是否具有應變或未應變通道，或源極-汲極尖端區或無源極-汲極尖端區，並不特別相關於本發明之各式實施例，且不希望該等實施例侷限於任何特別該等結構特徵。 而是，如文中所說明，任何數量電晶體結構及類型，特別是該些結構具有n型及p型源極/汲極電晶體區，可獲益於採用n型源極/汲極區上之小帶隙及/或充分摻雜III-V材料層，及p型源極/汲極區上之充分摻雜鍺。通常，若III-V材料帶隙夠小，在室溫下便不需摻雜劑(儘管如果需要的話可使用摻雜劑)。在一特定示範狀況下，未摻雜銻化銦服務n型源極/汲極區及硼-摻雜鍺服務p型源極/汲極區。然而，對較大帶隙III-V材料(>0.5eV)而言，摻雜可用以提供n型III-V材料中所欲導電性。
進一步參照圖1A，在定義源極/汲極區之後，繼續本示範實施例之方法，且在106，沉積絕緣體層322。圖2B顯示絕緣體層322為平坦，且閘極堆疊之硬遮罩306不需為平坦。絕緣體可以若干方式組配。在若干實施例中，係以SiO2或其他低-k電介質(絕緣體)材料實施絕緣體層322。在更一般的意義上，可視需要選擇層322材料之介電常數。在若干實施例中，絕緣體層322可包括襯墊(例如，氮化矽)，其後為一或多層SiO2，或氮化物、氧化物、氮氧化物、碳化物、碳氧化物、或其他合適絕緣體材料之任何組合。可稱為層際電介質(ILD)之絕緣體層322可如常見作法平面化(例如，藉由後沉積平面化程序，諸如化學機械平面化或CMP)。可用以形成層322之其他示範絕緣體材料包括例如碳摻雜氧化物(CDO)；有機聚合物，諸如八氟環丁烷或聚四氟乙烯；氟矽玻璃(FSG)；及有機矽酸脂，諸如倍半矽氧烷、矽氧烷、或 有機矽酸鹽玻璃。在若干示範組態中，絕緣體層322可包括孔或其他空隙以進一步降低其介電常數。
如鑒於此揭露將理解的，及依據本發明之若干實施例，其中使用置換金屬閘極(RMG)程序，方法可進一步包括使用如習知作法之蝕刻程序移除閘極堆疊(包括高-k閘極介電層302、犧牲閘極電極304、及硬遮罩層306)。在若干該等狀況下，僅移除犧牲閘極304及硬遮罩層306。繼續方法，若移除閘極介電層302，可將新閘極介電層沉積進入凹槽開口。此處可使用諸如先前所說明之任何合適閘極電介質材料，諸如鉿氧化物。亦可使用相同沉積程序。可使用閘極介電層之置換，例如處理在應用乾式及濕式蝕刻程序期間最初閘極介電層可發生之任何損害，及/或以高-k或所欲閘極電介質材料置換低-k或犧牲電介質材料。在該等RMG程序中，方法可進一步包活將閘極電極層沉積進入凹槽及閘極介電層之上。習知沉積程序可用以形成置換閘極電極，諸如CVD、ALD、及PVD。閘極電極層可包括例如p型功函數金屬，諸如釕、鈀、鉑、鈷、鎳、及例如釕氧化物之傳導金屬氧化物。在若干示範組態中，可沉積二或更多金屬閘極電極層。例如，可於閘極凹槽中沉積功函數金屬，其後為合適金屬閘極電極填充金屬，諸如鋁或銀。圖2B'顯示源自該等可選RMG程序之示範閘極結構，其包括置換閘極介電層324上之置換閘極電極層326。仍在其他實施例中，之後在方法中可實施該RMG處理(例如，在步驟118之後)，使 得置換閘極材料將不經歷與步驟118及更早相關之處理。
進一步參照圖1A，在提供絕緣體層322(及任何所欲預接觸形成RMG程序)之後，繼續方法且在108，蝕刻以形成源極/汲極接點凹槽。可使用標準光刻，其後為任何合適乾式及/或濕式蝕刻程序。圖2C顯示依據一示範實施例之蝕刻完成後之源極/汲極接點凹槽。
如圖2D最佳顯示，繼續方法且在110，選擇地沉積p型鍺層317進入凹槽並在電晶體結構之p型源極/汲極區之上。請注意，有關此選擇鍺沉積之結果，p型源極/汲極區現在有效地相對高於較短n型源極/汲極區。在若干實施例中，p型鍺層317包含硼摻雜鍺，儘管亦可使用其他合適p型鍺。硼摻雜鍺程序之優勢為對於絕緣體322及SiGe源極/汲極區之n型矽是選擇的。在若干該等示範實施例中，可外延沉積於一或多層中之硼摻雜鍺層317具有超過90原子%的鍺濃度，儘管如鑒於此揭露將理解的可使用其他合適濃度級(例如，超過91原子%、或92原子%、...，或98原子%、或99原子%、或真正純鍺)。請注意，此鍺濃度可為固定或分級，以便從基級(接近基板300)提昇至高級(例如，超過90原子%)。在若干該等實施例中，硼濃度可超過1E20 cm-3，諸如高於2E20 cm-3或2E21 cm-3，亦可分級以便從接近基板300之基級提昇至高級(例如，超過1E20 cm-3或2E20 cm-3或3E20 cm-3、...，2E21 cm-3)。在相關p型源極/汲極區之鍺濃度為固定或相對低之實施例中，分級緩衝器可用以較佳界接源 極/汲極區與硼摻雜鍺層317。硼摻雜鍺層317之厚度可具有介於例如50至250Å之厚度。依據若干特定示範實施例，儘管如鑒於此揭露將顯而易見的，替代實施例可具有其他層厚度。
在若干實施例中，在110，CVD程序或其他合適沉積技術可用於沉積或形成硼摻雜鍺層317。在110，例如可以CVD、或快速熱CVD(RT-CVD)、或低壓CVD(LP-CVD)、或超高真空CVD(UHV-CVD)、或使用含鍺及硼先質之氣源分子束外延(GS-MBE)工具，諸如鍺烷(GeH4)或乙鍺烷(Ge2H6)及乙硼烷(B2H6)或二氟化硼(BF2)，實施沉積。在若干該等實施例中，可存在載氣，諸如氫、氮、或惰性氣體(例如，先質以1-20%濃度稀釋且餘額為載氣)。亦可存在蝕刻劑氣體，例如以鹵素為基之氣體，諸如氯化氫(HCl)、氯(Cl)、或溴化氫(HBr)。鍺以及硼摻雜鍺之基本沉積可能超越廣泛狀況，使用介於例如300℃至800℃(例如，400-500℃)之沉積溫度，及例如介於1Torr至760Torr之反應堆壓力。鍺係自然選擇，其中其沉積於矽或矽-鍺合金上，而不沉積於諸如二氧化矽及氮化矽之其他材料上。由於此自然選擇性並非完美無瑕，如先前所注意的，小流量蝕刻劑可用以提昇沉積之選擇性。載子及蝕刻劑之每一者可具有介於10及300SCCM之流量(典型地，需要不多於100SCCM流量，但若干實施例可要求更高流率)。在一特定示範實施例中，在206，使用以1%濃度氫稀釋並介於100 及1000SCCM流率之GeH4實施沉積。對硼之原地摻雜而言，可使用稀釋B2H6(例如，B2H6可以3%濃度H2稀釋並介於10及300SCCM流率)。在若干該等特定示範狀況下，HCl或Cl2之蝕刻劑以介於例如10及100SCCM流率添加，以提昇沉積之選擇性。
如鑒於此揭露將進一步理解的，p型鍺層317沉積之選擇性可視需要改變。在若干狀況下，例如p型鍺層317僅沉積於p型源極/汲極區或一部分該區上(而非跨越整個結構)。可使用或利用任何數量遮罩/圖案化及/或自然選擇性技術以選擇地沉積層317。再者，其他實施例可自覆蓋例如暴露多閘極區或暴露接地分接區之層317獲益。如鑒於此揭露將進一步理解的，依據若干示範實施例，高鍺濃度(例如，超過90原子%及直至純鍺)及高摻雜劑濃度(例如，硼超過2E20 cm-3)之組合可用以實現p型源極及汲極區(及希望低接觸電阻之其他區域，諸如接地分接區)中顯著低接觸電阻。此外，及如先前所說明，由於硼擴散藉由純鍺而被充分抑制，儘管任何高硼濃度緊鄰通道(若適用)，後續熱退火並未導致不利SCE降級。從接點表面的較高鍺濃度亦可致能降低障壁高度。在若干示範實施例中，超過95原子%及直至純鍺(100原子%)之鍺濃度可用於層317以達成該等利益。
一旦提供鍺層317，在112，方法繼續將III-V半導體材料層沉積在電晶體結構之n型源極/汲極區上，以及覆蓋鍺的電晶體結構之p型源極/汲極區上。圖2E顯示依 據一示範實施例之n型及覆蓋鍺之p型源極/汲極區上之III-V材料層319。如將理解的，在112，此沉積可非選擇性實施，如圖2F之最佳顯示，其中任何多餘III-V沉積隨後從絕緣體322(及閘極堆疊，若需要)之頂部移除。在其他實施例中，在112，沉積係選擇性實施，其中III-V材料沉積僅在n型源極/汲極區及覆蓋鍺之p型源極/汲極區上。在112，例如沉積可包含高度n型(例如，Si、Ge、S、Te等)摻雜(>1E17 cm-3)III-V層，其具有針對絕緣體322層(例如，SiO2或SiN)自然選擇之Al、Ga、In及P、As、Sb的任何組合。在該等選擇狀況下，層319將在n型SiGe或矽源極/汲極區及覆蓋鍺之p型源極/汲極區上生長，但將不在諸如SiO2或SiN之絕緣體表面上生長。
在若干實施例中，在112，可以摻雜III-V材料之單一組成實施所有源極/汲極區(包括覆蓋鍺之p型區)上的沉積。另一方面，在112，可以未摻雜III-V材料之單一組成實施所有源極/汲極區(包括覆蓋鍺之p型區)上的沉積，其中未摻雜III-V材料具有小於0.5eV之帶隙(例如，InxGa1-xAs之帶隙=0.427eV，其中x=.9)。在若干該等小帶隙狀況下，帶隙小於0.4eV(例如，InAs之帶隙=0.36eV)。在仍其他該等狀況下，帶隙小於0.3eV。在仍其他該等狀況下，帶隙小於0.2eV(例如，InSb之帶隙=0.17eV)。在仍其他該等狀況下，帶隙係介於諸如0.1eV及0.4eV、或0.1eV及0.25eV、或0.25eV 及0.5eV、或0.15eV及0.35eV之範圍內。然而，請注意，III-V材料不需侷限於具有小於0.5eV之帶隙。這是因為III-V材料可以例如原地摻雜、擴散摻雜、或植入摻雜沉積，使得其被調適為相關源極/汲極材料之摻雜型式。
在若干示範實施例中，III-V材料層319係外延沉積。依據若干特定示範實施例，III-V材料層319之厚度可介於例如50至250Å，如鑒於此揭露將顯而易見的，儘管其他實施例可具有其他層厚度。用以形成p型鍺層317之類似沉積技術可用以形成使用III-V材料化合物之n型III-V材料層319(例如，CVD、RT-CVD、LP-CVD、UHV-CVD、PVD、ALD、MBE或GS-MBE)，諸如Al、Ga、In、P、As、Sb、及/或其先質之組合。在一特定該等示範實施例中，III-V材料層319係以未摻雜銻化銦(InSb)實施。在另一實施例中，III-V材料層319係以GaAs摻雜Ge實施，以提供1E19原子/cm3或更高之置換Ge濃度，其導致約5E-3 Ohm-cm電阻係數(或約200Mho/cm之相應導電性)。在任何該等實施例中，可存在載氣，例如氫、氮、或惰性氣體(例如，以1-20%濃度稀釋先質，且餘額為載氣)。在若干示範狀況下，可存在砷先質諸如砷化三氫或TBA、鎵先質諸如TMG、及/或銦先質諸如TMI。可存在蝕刻劑氣體，例如以鹵素為基之氣體，諸如氯化氫(HCl)、氯(Cl)、或溴化氫(HBr)。III-V半導體材料層319之基本沉積可能超越廣 泛狀況，使用介於例如300℃至700℃(例如，300-500℃)之沉積溫度，及例如介於1Torr至760Torr之反應堆壓力。載子及蝕刻劑之每一者可具有介於10及300SCCM之流量(典型地，需要不多於100SCCM流量，但若干實施例可獲益於更高流率)。在一特定示範實施例中，在112，可以介於100及1000SCCM流率實施沉積。對原地摻雜鍺而言，例如可使用稀釋鍺烷或乙鍺烷(例如，鍺烷可以10%濃度H2稀釋並介於10及100SCCM流率)。
可使用任何數量遮罩/圖案化技術進一步定義區以選擇地沉積層319。再者，其他實施例可獲益自覆蓋例如多閘極區或接地分接區之層319。如鑒於此揭露將進一步理解的，依據若干示範實施例，III-V材料層319可用以實現n型源極及汲極區(及希望低接觸電阻之其他區域，諸如接地分接區)中之顯著低接觸電阻。
進一步參照圖1A，在114，方法繼續向後蝕刻III-V材料沉積層，以暴露p型源極/汲極區上之相關鍺層317，及n型源極/汲極區上之III-V材料層319的較小厚度。根據III-V沉積之選擇性及粗糙度，此向後蝕刻程序可包括最初平面化/拋光(例如，CMP)以移除多餘III-V材料，其後為蝕刻(可使用乾式及/或濕式蝕刻)。圖2G中顯示此向後蝕刻程序之示範結果結構(圖2F顯示在圖2G中所示蝕刻之前的可選平面化步驟)。由於III-V沉積通常粗糙，其可沉積至相對大厚度，接著使用例如乾 式蝕刻向後蝕刻以平面化，同時並使III-V層319變薄。假設p型源極/汲極區上之最初鍺層317充分厚，向後蝕刻程序導致接點凹槽之底部的暴露表面，該接點凹槽包括n型源極/汲極區上之III-V區域319，及p型源極/汲極區上之鍺區域317。因而，在114，向後蝕刻程序有效地利用高度差來自我對準接點類型。標準或訂製接點形成程序流程可此實施以產生低電阻p及n接點。
在116，方法接著繼續沉積接觸電阻降低金屬並在p型鍺層317及n型III-V材料層319上退火，接著在118，在每一者上沉積源極/汲極接點插銷。請注意在該等實施例中，在n型源極/汲極區之上並無矽化物或鍺化物。而是在III-V材料319及金屬接觸電阻降低層325之間之任何反應文中一般稱為III-V化物。圖2H顯示接觸電阻降低金屬325，在若干實施例中，其包括銀、鎳、鋁、鈦、金、金-鍺、鎳-鉑或鎳-鋁、及/或其他該等電阻降低金屬或合金。如果需要的話，其他實施例可進一步包括額外層，諸如層317及層325之間及/或層319及層325之間之附著層。圖2I顯示使用習知沉積程序之接點插銷金屬329，在若干實施例中，其包括鋁或鎢，儘管可使用任何適當傳導接點金屬或合金，諸如銀、鎳、鉑、鈦、或其合金。程序可進一步包括平面化/拋光以移除多餘金屬及隔離每一接點凹槽與相鄰者。在若干示範狀況下，在相應源極/汲極區及接觸電阻降低金屬325之間之介面具有組配鍺層317及III-V材料層319之源極/汲極的電晶 體可展示小於100Ohm-um之電阻係數值，在若干狀況下為小於90Ohm-um，及在若干狀況下為小於80Ohm-um，及在若干狀況下為小於75Ohm-um或更低。
圖1B為依據本發明之另一實施例之用於形成具低接觸電阻之電晶體結構的方法。圖3A至3C描繪形成替代示範結構。通常，此方法類似於參照圖1A及2A-I所說明之方法，除了係在絕緣體322沉積之前實施將鍺材料層317沉積於p型源極/汲極區之上。此在圖1B中有效地指出，將在110沉積鍺材料移動至在104定義源極/汲極之後，及在106沉積絕緣體之前。圖3A中顯示，在106絕緣體沉積後之結果結構。請注意，在此示範實施例中，鍺層317如何完全覆蓋所示p型源極/汲極區之每一者，而非僅藉由接點凹槽之暴露部分(如圖2D中最佳顯示)。圖3B顯示在108蝕刻接點凹槽後之結果結構，及圖3C顯示在112沉積及在114向後蝕刻n型III-V材料之後，及在116沉積接觸電阻降低金屬325及在118沉積金屬接點插銷329之後的結果結構。如將理解的，先前相對於參照圖1A所討論之示範方法的類似零件的相關討論此處同樣適用。
非平面組態
例如可使用鰭式場效電晶體(FinFET)或奈米線組態實施非平面架構。FinFET為環繞半導體材料之薄帶(一般稱為鰭片)建造之電晶體。電晶體包括標準場效電晶體 (FET)節點，其包括閘極、閘極電介質、源極區、及汲極區。裝置之傳導通道駐於閘極電介質下之鰭片外側/外側內。具體地，電流沿鰭片之側壁(垂直於基板表面之側面)運行，以及沿鰭片之頂部(平行於基板表面之側面)運行。因為該等組態之傳導通道實質上沿鰭片之三不同外部、平面區設置，該等FinFET設計有時稱為三閘極FinFET。其他類型FinFET組態亦可用，諸如所謂雙閘極FinFET，其中傳導通道主要僅沿鰭片之二側壁設置(未沿鰭片之頂部)。奈米線電晶體(有時稱為閘極環繞FET)係極類似地組配，但使用奈米線(例如，矽或SiGe或Ge奈米線)取代鰭片，且閘極材料一般圍繞通道區的所有側面。根據特別設計，奈米線電晶體具有例如四個有效閘極。
圖4A-4E各顯示依據本發明之一實施例組配之示範非平面架構的透視圖。具體地，圖4A-B各顯示FinFET電晶體結構之透視圖，及圖4C-E顯示示範奈米線通道電晶體結構。現在將依次討論每一圖。
可以看出，圖4A中所示示範非平面組態係以三閘極裝置實施，各包括基板600，其具有半導體本體或從基板600延伸穿過隔離區620之鰭片660。閘極電極640係形成於鰭片660之三表面上以形成三閘極。硬遮罩690係形成於閘極電極640之頂部。閘極間隔器670、680係形成於閘極電極640之相對側壁。p型源極區包含外延區631a，形成於內凹源極介面650及一鰭片660側壁上，且 汲極區包含外延區631a，形成於內凹源極介面650及相對鰭片660側壁(未顯示)上。此外，n型源極區包含外延區631b，形成於內凹源極介面650及一鰭片660側壁上，且汲極區包含外延區631b，形成於內凹源極介面650及相對鰭片660側壁(未顯示)上。p型鍺蓋體層641a係沉積於源極/汲極區631a之上，且n型III-V蓋體層641b係沉積於源極/汲極區631b之上。請注意，鍺及III-V材料蓋體層641a及641b分別可設置於相應凹部(尖端)區，但在其他實施例中，僅設置於源極/汲極區之上(未在凹部區中)。在一實施例中，隔離區620為使用習知技術形成之淺凹槽隔離(STI)區，諸如蝕刻基板600以形成凹槽，接著將氧化物材料沉積至凹槽上以形成STI區。隔離區620可以任何合適電介質/絕緣材料製成，諸如SiO2。先前相對於基板300討論者，此處同樣適用(例如，基板600可為矽基板，或XOI基板諸如SOI基板，或多層基板)。如鑒於此揭露將理解的，習知程序及形成技術可用以製造FinFET電晶體結構。然而，及依據本發明之一示範實施例，可使用例如原地p型矽或以p型鍺層(用於641a)覆蓋SiGe(用於631a)而實施p型源極/汲極區631a及相應蓋體層641a，並可使用例如原地n型矽或以n型III-V材料層(用於641b)覆蓋SiGe(用於631b)而實施n型源極/汲極區631b及相應蓋體層641b。如將進一步理解的，請注意，以雙閘極架構替代三閘極組態，雙閘極架構包括鰭片660之頂部上的電介 質/隔離層。進一步請注意，圖4A中所示之源極/汲極區631(a及b)的示範形狀不希望侷限所主張本發明於任何特定源極/汲極型式或形成程序，及鑒於此揭露，其他源極/汲極形狀(用於n及p)將顯而易見(例如，可實施圓形、方形或矩形p及n型源極/汲極區)。
如將理解的，圖4A中所示之源極/汲極區631(a及b)係使用置換程序(例如，蝕刻、外延沉積等)形成。然而，在其他實施例中，如圖4B中最佳顯示，源極/汲極區631可為從基板600材料本身形成之部分鰭片660。僅顯示一源極/汲極區631，但可以類似方式實施許多區(包括n型及p型S/D區)。蓋體層641係以先前參照圖4A所討論之類似方式沉積於源極/汲極區631之上(包括n型S/D區上之n型III-V材料及p型S/D區上之p型鍺)。如將理解的，相對於圖4A提供之其他相關討論，此處同樣適用。
另一替代為奈米線通道架構，如圖4C中最佳顯示，奈米線通道架構可包括例如基板600材料之基座，奈米線660(例如，矽或SiGe)於其上生長或設置。類似於圖4B中所示之鰭片結構，奈米線660包括源極/汲極區631(如先前所說明，僅顯示一區，但可實施多個該等區，包括p型及n型)。恰如鰭片結構，可從基板600材料或一或多個置換材料(例如，矽或SiGe)形成源極/汲極區631。材料641可設置例如環繞奈米線660的所有源極/汲極區631或僅奈米線660之一部分(例如，除了基座上 之部分以外)。如先前所說明，材料641可為例如n型S/D區上之n型III-V材料及p型S/D區上之p型鍺。圖4D描繪具有多奈米線660(本範例中為二)之奈米線組態。可以看出，一奈米線660設置於基板600之凹部，其他奈米線660則有效地在材料641層中漂浮。以垂直交叉影線顯示相應源極/汲極區631，其可為p型及/或n型源極/汲極區。圖4E亦描繪具有多奈米線660之奈米線組態，但在此範例中，在奈米線形成程序期間從個別奈米線之間移除非活動材料632，如鑒於此揭露將理解的，其可使用各式習知技術實施。因而，一奈米線660設置於基板600之凹部，其他奈米線660則有效地位在材料632之頂部上。請注意，奈米線660活動通過通道，但材料632則否。材料641係設置環繞奈米線660之所有其他暴露表面。如先前所說明，以垂直交叉影線顯示相應源極/汲極區631，其可為p型及/或n型源極/汲極區。
示範系統
圖5描繪使用依據本發明之示範實施例組配之一或多個電晶體結構實施計算系統1000。可以看出，計算系統1000容納主機板1002。主機板1002可包括若干組件，包括但不侷限於處理器1004及至少一通訊晶片1006，其每一者可實體或電耦接至主機板1002，或整合於其中。如將理解的，主機板1002可為例如任何印刷電路板，不論是主板或安裝於主板上之子板或僅系統1000板等。根據 其應用，計算系統1000可包括一或多個其他組件，可或不可實體或電耦接至主機板1002。該些其他組件可包括但不侷限於揮發性記憶體(例如DRAM)、非揮發性記憶體(例如ROM)、圖形處理器、數位信號處理器、加密處理器、晶片組、天線、顯示器、觸控螢幕顯示器、觸控螢幕控制器、電池、音頻編解碼器、視訊編解碼器、功率放大器、全球定位系統系統(GPS)裝置、羅盤、加速計、陀螺儀、揚聲器、相機、及大量儲存裝置(諸如硬碟機、光碟(CD)、數位影音光碟(DVD)等)。計算系統1000中所包括之任何組件可包括如文中所說明之一或多個電晶體結構(例如，具有n型源極/汲極區上之n型III-V材料層及p型源極/汲極區上之p型鍺以提供低接觸電阻/改進之導電性)。可使用該些電晶體結構例如以實施板上處理器高速緩衝記憶體或記憶體陣列。在若干實施例中，多功能可整合進入一或多個晶片(例如，請注意，通訊晶片1006可為處理器1004之一部分或整合於其中)。
通訊晶片1006致能無線通訊用於傳輸資料至及自計算系統1000。「無線」用詞及其衍生字可用以說明電路、裝置、系統、方法、技術、通訊通道等，可經由使用調變電磁輻射通過非固態媒體而傳達資料。此用詞並非暗示相關裝置未包含任何線路，儘管在若干實施例中可能未包含。通訊晶片1006可實施任何若干無線標準或協定，包括但不侷限於Wi-Fi(IEEE 802.11系列)、WiMAX (IEEE 802.16系列)、IEEE 802.20、長期演進(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、藍牙、其衍生、以及指定為3G、4G、5G及超越之任何其他無線協定。計算系統1000可包括複數通訊晶片1006。例如，第一通訊晶片1006可專用於短距離無線通訊，諸如Wi-Fi及藍牙，且第二通訊晶片1006可專用於長距離無線通訊，諸如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO、及其他。
計算系統1000之處理器1004包括封裝於處理器1004內的積體電路晶粒。在本發明之若干實施例中，處理器之積體電路晶粒包括板上記憶體電路，如文中各式說明，其係使用具有n型源極/汲極區上之n型III-V材料層及p型源極/汲極區上之p型鍺的一或多個CMOS電晶體結構而予實施。「處理器」用詞可指任何裝置或部分裝置，其處理例如來自暫存器及/或記憶體之電子資料，以將電子資料轉換為可儲存於暫存器及/或記憶體中的其他電子資料。
通訊晶片1006亦可包括封裝於通訊晶片1006內的積體電路晶粒。依據若干該等示範實施例，通訊晶片之積體電路晶粒包括使用如文中所說明之一或多個電晶體結構(例如，晶片上處理器或記憶體)實施的一或多個裝置。如鑒於此揭露將理解的，請注意，多標準無線能力可直接整合進入處理器1004(例如，任何晶片1006之功能性被 整合進入處理器1004，而非具有個別通訊晶片)。進一步請注意，處理器1004可為具有該等無線能力之晶片組。簡言之，可使用任何數量處理器1004及/或通訊晶片1006。同樣地，任何一晶片或晶片組可具有整合於其中之多功能。
在各式實施中，計算系統1000可為膝上型電腦、輕省筆電、筆記型電腦、智慧手機、平板電腦、個人數位助理(PDA)、超行動PC、行動電話、桌上型電腦、伺服器、印表機、掃描器、監視器、機上盒、娛樂控制單元、數位相機、可攜式音樂播放器、或數位視訊記錄器。在進一步實施中，系統1000可為任何其他電子裝置，其處理資料或採用如文中所說明之低接觸電阻電晶體裝置(例如，如文中各式說明，分別具有p型鍺及n型III-V材料層之中間層組配之p及n型裝置的CMOS裝置)。
許多實施例將顯而易見，且文中所說明之特徵可以任何數量組態組合。本發明之一示範實施例提供半導體積體電路。積體電路包括具有若干通道區的基板及每一通道區上之閘極電極，其中，閘極介電層係設置於每一閘極電極及相應通道區之間。積體電路進一步包括基板中及鄰近於相應通道區之p型源極/汲極區，及基板中及鄰近於相應通道區之n型源極/汲極區。積體電路進一步包括至少一部分p型源極/汲極區上之p型鍺層，及至少一部分n型源極/汲極區上之n型III-V半導體材料層。積體電路進一步包括p型鍺層及n型III-V半導體材料層之每一者上 之金屬接點。在若干狀況下，n型III-V半導體材料層為未摻雜。在若干狀況下，n型III-V半導體材料層具有小於0.5eV之帶隙。在若干狀況下，n型III-V半導體材料層具有小於0.2eV之帶隙。在其他狀況下，n型III-V半導體材料層為摻雜。在若干該等狀況下，n型III-V半導體材料層摻雜有一或多個兩性摻雜劑。在一該等狀況下，n型III-V半導體材料層摻雜有一或多個兩性摻雜劑以大於1E18原子/cm3置換濃度。在若干狀況下，p型鍺層摻雜有硼。在一該等狀況下，硼濃度超過1E20 cm-3。在若干狀況下，使用平面電晶體架構實施裝置。在其他狀況下，使用非平面電晶體架構實施裝置。在若干該等狀況下，非平面電晶體架構包含FinFET電晶體及/或奈米線電晶體之至少一者。在若干狀況下，p型及n型源極/汲極區包含矽、鍺、或其合金。本發明之另一實施例包括電子裝置，其包括具有如本段中所定義之一或多個積體電路的印刷電路板。在一該等狀況下，一或多個積體電路包含通訊晶片及/或處理器之至少一者。在另一該等狀況下，裝置為計算裝置。
本發明之另一實施例提供一種裝置，包含具有若干通道區的含矽基板及每一通道區上之閘極電極，其中，閘極介電層係設置於每一閘極電極及相應通道區之間。裝置進一步包括基板中及鄰近於相應通道區之p型源極/汲極區，及基板中及鄰近於相應通道區之n型源極/汲極區，p型及n型源極/汲極區包含矽、鍺、或其合金。裝置進一 步包括至少一部分p型源極/汲極區上之p型鍺層，及至少一部分n型源極/汲極區上之n型III-V半導體材料層。裝置進一步包括p型鍺層及n型III-V半導體材料層之每一者上之金屬接點。在若干狀況下，n型III-V半導體材料層為未摻雜。在其他狀況下，n型III-V半導體材料層為摻雜。在一該等狀況下，n型III-V半導體材料層摻雜有一或多個兩性摻雜劑。在另一該等狀況下，n型III-V半導體材料層摻雜有一或多個兩性摻雜劑以大於1E18原子/cm3置換濃度。在若干狀況下，n型III-V半導體材料層具有小於0.5eV之帶隙。在若干狀況下，p型鍺層摻雜有硼。在一該等狀況下，硼濃度超過1E20 cm-3。
本發明之另一實施例提供用於形成半導體裝置之方法。方法包括設置具有若干通道區之基板，以及設置每一通道區上之閘極電極，其中，閘極介電層係設置於每一閘極電極及相應通道區之間。方法進一步包括於基板中及鄰近於相應通道區設置p型源極/汲極區，及於基板中及鄰近於相應通道區設置n型源極/汲極區。方法進一步包括於至少一部分p型源極/汲極區上設置p型鍺層，及於至少一部分n型源極/汲極區上及其上具有p型鍺層之p型源極/汲極區上方設置n型III-V半導體材料層。方法進一步包括向後蝕刻n型III-V半導體材料層以暴露p型源極/汲極區上方之相關p型鍺，並使n型源極/汲極區上方之n型III-V半導體材料層變薄。方法進一步包括於p型鍺層及n型III-V半導體材料層之每一上設置金屬接 點。
本發明之實施例的上述說明已為描繪及說明之目的呈現。不希望排他或侷限本發明於所揭露之精確形式。鑒於此揭露，許多修改及變化是可能的。希望本發明之範圍不侷限於此詳細說明，而是侷限於附加之申請項。
如將理解的，圖不一定按比例尺繪製或希望所主張之本發明侷限於所示特定組態。例如，雖然若干圖通常指出直線、直角及平坦表面，電晶體結構之實際實施可具有小於完美直線、直角，及若干特徵可具有表面拓樸或為非平坦，所使用處理裝備及技術的特定真實世界限制。簡言之，圖僅提供用以顯示示範結構。
300‧‧‧基板
302‧‧‧閘極介電層
304‧‧‧閘極電極
306‧‧‧硬遮罩
317‧‧‧p型鍺層
322‧‧‧絕緣體層

Claims (20)

  1. 一種積體電路，包含：直接在p型源極/汲極區的至少一部分上之p型鍺；以及直接在n型源極汲極區的至少一部分上之n型III-V半導體材料。
  2. 如申請專利範圍第1項之積體電路，包含：具有若干通道區之基板；其中，該p型源極/汲極區係在該基板中及上的至少一者並鄰近於相應通道區；以及其中，該n型源極/汲極區係在該基板中及上的至少一者並鄰近於相應通道區。
  3. 如申請專利範圍第2項之積體電路，更包含：每一通道區上之閘極電極，其中，閘極介電係設置於每一閘極電極及相應通道區之間。
  4. 如申請專利範圍第2項之積體電路，更包含：該基板上之絕緣材料，該絕緣材料具有在該p型源極/汲極區及該n型源極/汲極區的每一者上形成之接點凹槽，其中該n型III-V半導體材料係完全在該n型源極/汲極區上所形成的該接點凹槽之內。
  5. 如申請專利範圍第4項之積體電路，其中該p型鍺係完全在該p型源極/汲極區上所形成的該接點凹槽之內。
  6. 如申請專利範圍第2項之積體電路，其中該基板係 塊體矽基板。
  7. 如申請專利範圍第6項之積體電路，其中該p型源極/汲極區係矽或鍺或矽鍺合金。
  8. 如申請專利範圍第6項之積體電路，其中該n型源極/汲極區係矽或鍺或矽鍺合金。
  9. 如申請專利範圍第1項之積體電路，其中該n型III-V半導體材料包含鋁、鎵、銦、磷、砷、及銻的至少一者。
  10. 如申請專利範圍第1項之積體電路，其中該p型源極/汲極區及該n型源極/汲極區具有平面擴散區。
  11. 如申請專利範圍第1項之積體電路，其中該p型源極/汲極區及該n型源極/汲極區具有鰭片形擴散區。
  12. 如申請專利範圍第1項之積體電路，其中該p型源極/汲極區及該n型源極/汲極區具有線形擴散區。
  13. 如申請專利範圍第1項之積體電路，其中該p型源極/汲極區及該n型源極/汲極區的每一者與通道區連接，且該p型源極/汲極區及該n型源極/汲極區的至少一者相對於它們的相應通道區而被抬高。
  14. 如申請專利範圍第1項之積體電路，更包含：在該p型鍺層及該n型III-V材料層上之接觸電阻降低金屬；以及在該接觸電阻降低金屬上之源極/汲極金屬接點插銷。
  15. 一種積體電路，包含： 具有若干鰭片從其延伸之基板，每一該基板具有通道區；在該基板中及上的至少一者並鄰近於相應通道區之p型源極/汲極區；在該基板中及上的至少一者並鄰近於相應通道區之n型源極/汲極區；直接在該p型源極/汲極區的至少一部分上之p型鍺；以及直接在該n型源極汲極區的至少一部分上之n型III-V半導體材料。
  16. 如申請專利範圍第15項之積體電路，更包含：該基板上之絕緣材料，該絕緣材料具有在該p型源極/汲極區及該n型源極/汲極區的每一者上形成之接點凹槽，其中該n型III-V半導體材料係完全在該n型源極/汲極區上所形成的該接點凹槽之內；每一通道區上之閘極電極，其中，閘極介電係設置於每一閘極電極及相應通道區之間；在該p型鍺層及該n型III-V材料層上之接觸電阻降低金屬；以及在該接觸電阻降低金屬上之源極/汲極金屬接點插銷。
  17. 如申請專利範圍第15項之積體電路，其中，該p型源極/汲極區及該n型源極/汲極區的至少一者具有一或多個佈線。
  18. 一種積體電路，包含：具有若干鰭片從其延伸之基板，每一該基板具有通道區，該通道區的至少一者配置有一或多個奈米佈線；在該基板中及上的至少一者並鄰近於相應通道區之p型源極/汲極區；在該基板中及上的至少一者並鄰近於相應通道區之n型源極/汲極區；直接在該p型源極/汲極區的至少一部分上之p型鍺；以及直接在該n型源極汲極區的至少一部分上之n型III-V半導體材料。
  19. 如申請專利範圍第18項之積體電路，更包含：該基板上之絕緣材料，該絕緣材料具有在該p型源極/汲極區及該n型源極/汲極區的每一者上形成之接點凹槽，其中該n型III-V半導體材料係完全在該n型源極/汲極區上所形成的該接點凹槽之內；每一通道區上之閘極電極，其中，閘極介電係設置於每一閘極電極及相應通道區之間；在該p型鍺層及該n型III-V材料層上之接觸電阻降低金屬；以及在該接觸電阻降低金屬上之源極/汲極金屬接點插銷。
  20. 如申請專利範圍第18項之積體電路，其中，該p型源極/汲極區及該n型源極/汲極區的至少一者具有一或多個佈線。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI819254B (zh) * 2020-08-31 2023-10-21 台灣積體電路製造股份有限公司 半導體元件及其製造方法及類比數位轉換器

Families Citing this family (89)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8896066B2 (en) * 2011-12-20 2014-11-25 Intel Corporation Tin doped III-V material contacts
WO2013095377A1 (en) 2011-12-20 2013-06-27 Intel Corporation Self-aligned contact metallization for reduced contact resistance
US9153583B2 (en) 2011-12-20 2015-10-06 Intel Corporation III-V layers for N-type and P-type MOS source-drain contacts
US20130299895A1 (en) 2012-05-09 2013-11-14 Taiwan Semiconductor Manufacturing Co., Ltd. Iii-v compound semiconductor device having dopant layer and method of making the same
US8866195B2 (en) 2012-07-06 2014-10-21 Taiwan Semiconductor Manufacturing Co., Ltd. III-V compound semiconductor device having metal contacts and method of making the same
US8847281B2 (en) 2012-07-27 2014-09-30 Intel Corporation High mobility strained channels for fin-based transistors
US9231106B2 (en) * 2013-03-08 2016-01-05 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET with an asymmetric source/drain structure and method of making same
US8884344B2 (en) * 2013-03-08 2014-11-11 International Business Machines Corporation Self-aligned contacts for replacement metal gate transistors
US9685509B2 (en) 2013-07-30 2017-06-20 Samsung Electronics Co., Ltd. Finfet devices including high mobility channel materials with materials of graded composition in recessed source/drain regions
KR102069609B1 (ko) 2013-08-12 2020-01-23 삼성전자주식회사 반도체 소자 및 그 제조 방법
EP3050109B1 (en) * 2013-09-27 2020-11-25 Intel Corporation Semiconductor device having group iii-v material active region and graded gate dielectric
KR102198938B1 (ko) * 2013-09-27 2021-01-05 인텔 코포레이션 인핸스먼트 모드 GaN 반도체 디바이스들을 위한 복합 하이-K 금속 게이트 스택
WO2015047354A1 (en) * 2013-09-27 2015-04-02 Intel Corporation Improved cladding layer epitaxy via template engineering for heterogeneous integration on silicon
US20160190319A1 (en) * 2013-09-27 2016-06-30 Intel Corporation Non-Planar Semiconductor Devices having Multi-Layered Compliant Substrates
US10109628B2 (en) 2013-12-18 2018-10-23 Intel Corporation Transistor device with gate control layer undercutting the gate dielectric
KR102135303B1 (ko) 2013-12-27 2020-07-17 인텔 코포레이션 확산된 팁 연장 트랜지스터
US9105663B1 (en) * 2014-01-30 2015-08-11 International Business Machines Corporation FinFET with silicon germanium stressor and method of forming
KR102220590B1 (ko) 2014-02-21 2021-03-03 삼성전자주식회사 컨택을 포함하는 집적 회로 장치 및 이의 제조 방법
WO2015142847A1 (en) * 2014-03-17 2015-09-24 Tufts University Integrated circuit with multi-threshold bulk finfets
US9171934B2 (en) * 2014-04-01 2015-10-27 Globalfoundries Inc. Methods of forming semiconductor devices using a layer of material having a plurality of trenches formed therein
US9142640B1 (en) * 2014-06-17 2015-09-22 Globalfoundries Inc. Containment structure for epitaxial growth in non-planar semiconductor structure
US9472628B2 (en) 2014-07-14 2016-10-18 International Business Machines Corporation Heterogeneous source drain region and extension region
KR102274587B1 (ko) 2014-07-16 2021-07-08 삼성전자주식회사 반도체 장치 및 그 제조 방법
US9385197B2 (en) * 2014-08-29 2016-07-05 Taiwan Semiconductor Manufacturing Co., Ltd Semiconductor structure with contact over source/drain structure and method for forming the same
US9793356B2 (en) 2014-09-12 2017-10-17 Samsung Electronics Co., Ltd. Semiconductor device and method for fabricating the same
US9773865B2 (en) 2014-09-22 2017-09-26 International Business Machines Corporation Self-forming spacers using oxidation
US9240454B1 (en) * 2014-10-22 2016-01-19 Stmicroelectronics, Inc. Integrated circuit including a liner silicide with low contact resistance
KR102245130B1 (ko) 2014-10-29 2021-04-29 삼성전자 주식회사 라이징 부 및 리세스 부를 갖는 컨택 패턴을 포함하는 반도체 소자
EP3021352B1 (en) * 2014-11-13 2020-10-07 IMEC vzw Method for reducing contact resistance in a transistor
EP3032575B1 (en) * 2014-12-08 2020-10-21 IMEC vzw Method for forming an electrical contact.
EP3238230A4 (en) * 2014-12-23 2018-08-22 INTEL Corporation Diffusion tolerant iii-v semiconductor heterostructures and devices including the same
US10497814B2 (en) 2014-12-23 2019-12-03 Intel Corporation III-V semiconductor alloys for use in the subfin of non-planar semiconductor devices and methods of forming the same
US9397162B1 (en) * 2014-12-29 2016-07-19 Globalfoundries Inc. FinFET conformal junction and abrupt junction with reduced damage method and device
US9543439B2 (en) * 2015-01-30 2017-01-10 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device structure and manufacturing method thereof
US9496264B2 (en) * 2015-02-13 2016-11-15 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of FinFET device
US9397214B1 (en) * 2015-02-16 2016-07-19 United Microelectronics Corp. Semiconductor device
KR102326316B1 (ko) * 2015-04-10 2021-11-16 삼성전자주식회사 반도체 소자의 제조 방법
KR102432268B1 (ko) 2015-04-14 2022-08-12 삼성전자주식회사 반도체 소자 및 그 제조 방법.
KR102316247B1 (ko) * 2015-04-14 2021-10-26 삼성전자주식회사 반도체 소자 및 이의 제조 방법
US9590102B2 (en) * 2015-04-15 2017-03-07 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
KR102400375B1 (ko) 2015-04-30 2022-05-20 삼성전자주식회사 반도체 장치 및 그 제조 방법
KR102398862B1 (ko) * 2015-05-13 2022-05-16 삼성전자주식회사 반도체 장치 및 그 제조 방법
US9871104B2 (en) 2015-06-30 2018-01-16 Taiwan Semiconductor Manufacturing Company, Ltd. Nanowire semiconductor device structure and method of manufacturing
US11201242B2 (en) * 2015-07-09 2021-12-14 International Business Machines Corporation Structure to enable titanium contact liner on pFET source/drain regions
US10103249B2 (en) 2015-09-10 2018-10-16 Taiwan Semiconductor Manufacturing Co., Ltd. FinFET device and method for fabricating the same
US10164097B2 (en) * 2015-09-11 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
WO2017044117A1 (en) 2015-09-11 2017-03-16 Intel Corporation Aluminum indium phosphide subfin germanium channel transistors
US9947755B2 (en) 2015-09-30 2018-04-17 International Business Machines Corporation III-V MOSFET with self-aligned diffusion barrier
US9553191B1 (en) * 2015-11-16 2017-01-24 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor and method for fabricating the same
US9899387B2 (en) * 2015-11-16 2018-02-20 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-gate device and method of fabrication thereof
WO2017091345A1 (en) * 2015-11-25 2017-06-01 Applied Materials, Inc. New materials for tensile stress and low contact resistance and method of forming
CN108292674B (zh) 2015-12-24 2022-05-13 英特尔公司 形成掺杂源极/漏极触点的方法及由其形成的结构
TWI692872B (zh) * 2016-01-05 2020-05-01 聯華電子股份有限公司 半導體元件及其形成方法
US10438948B2 (en) 2016-01-29 2019-10-08 Taiwan Semiconductor Manufacturing Co., Ltd. Method and device of preventing merging of resist-protection-oxide (RPO) between adjacent structures
CN108701692B (zh) * 2016-04-01 2024-04-02 英特尔公司 采用背侧半导体或金属的半导体二极管
CN109478566B (zh) 2016-06-17 2022-09-02 英特尔公司 一种场效应晶体管及其制作方法、cmos集成电路、移动计算机平台
US9824970B1 (en) 2016-06-27 2017-11-21 Globalfoundries Inc. Methods that use at least a dual damascene process and, optionally, a single damascene process to form interconnects with hybrid metallization and the resulting structures
KR102603279B1 (ko) 2016-07-01 2023-11-17 인텔 코포레이션 양쪽 사이드들 상의 금속화가 있는 반도체 디바이스들에 대한 후면 콘택트 저항 감소
US9799736B1 (en) * 2016-07-20 2017-10-24 International Business Machines Corporation High acceptor level doping in silicon germanium
US20180076324A1 (en) * 2016-09-14 2018-03-15 Applied Materials, Inc. Method of contact formation between metal and semiconductor
US10217707B2 (en) 2016-09-16 2019-02-26 International Business Machines Corporation Trench contact resistance reduction
US11757004B2 (en) * 2016-09-30 2023-09-12 Intel Corporation Transistors including source/drain employing double-charge dopants
US11978776B2 (en) * 2016-12-12 2024-05-07 Intel Corporation Non-planar semiconductor device having conforming ohmic contacts
TWI742137B (zh) * 2016-12-15 2021-10-11 台灣積體電路製造股份有限公司 半導體裝置的製造方法
US10269646B2 (en) * 2016-12-15 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US10249542B2 (en) 2017-01-12 2019-04-02 International Business Machines Corporation Self-aligned doping in source/drain regions for low contact resistance
US10062692B1 (en) * 2017-02-27 2018-08-28 Globalfoundries Inc. Field effect transistors with reduced parasitic resistances and method
US10319722B2 (en) 2017-03-22 2019-06-11 International Business Machines Corporation Contact formation in semiconductor devices
US10347581B2 (en) 2017-03-22 2019-07-09 International Business Machines Corporation Contact formation in semiconductor devices
TWI778048B (zh) * 2017-04-20 2022-09-21 美商微材料有限責任公司 形成半導體結構的方法
WO2019005106A1 (en) * 2017-06-30 2019-01-03 Intel Corporation PROHIBITED WIDE BAND CHANNEL TRANSISTOR AND SOURCE / BAND DRAIN PROHIBITED NARROW
CN109273528B (zh) * 2017-07-18 2021-08-06 中芯国际集成电路制造(上海)有限公司 半导体器件及其形成方法
US20190058044A1 (en) 2017-08-21 2019-02-21 International Business Machines Corporation Fin-type fet with low source or drain contact resistance
WO2019139615A1 (en) * 2018-01-12 2019-07-18 Intel Corporation Stacked thin film transistors with nanowires
US10373875B1 (en) 2018-03-22 2019-08-06 Globalfoundries Inc. Contacts formed with self-aligned cuts
CN110571188B (zh) * 2018-06-05 2021-10-01 中芯国际集成电路制造(上海)有限公司 接触插塞、半导体器件及其制造方法
US10608096B2 (en) 2018-06-11 2020-03-31 International Business Machines Corporation Formation of air gap spacers for reducing parasitic capacitance
US10886178B2 (en) 2018-08-22 2021-01-05 Globalfoundries Inc. Device with highly active acceptor doping and method of production thereof
CN112930591A (zh) 2018-09-18 2021-06-08 应用材料公司 原位集成型腔室
US10903315B2 (en) 2018-09-28 2021-01-26 International Business Machines Corporation Formation of dielectric layer as etch-stop for source and drain epitaxy disconnection
US10741639B2 (en) 2018-09-28 2020-08-11 International Business Machines Corporation Formation of dielectric layer as etch-stop for source and drain epitaxy disconnection
CN116705837A (zh) * 2018-10-26 2023-09-05 中国科学院微电子研究所 半导体器件与其制作方法
CN113261075A (zh) 2018-12-21 2021-08-13 应用材料公司 用于形成触点的处理系统和方法
US11195923B2 (en) 2018-12-21 2021-12-07 Applied Materials, Inc. Method of fabricating a semiconductor device having reduced contact resistance
WO2020163104A1 (en) 2019-02-08 2020-08-13 Applied Materials, Inc. Semiconductor device, method of making a semiconductor device, and processing system
CN110634866B (zh) * 2019-09-05 2021-09-14 中国科学院微电子研究所 一种cmos晶体管、cmos晶体管的制备方法及电子设备
US11211462B2 (en) 2020-03-05 2021-12-28 International Business Machines Corporation Using selectively formed cap layers to form self-aligned contacts to source/drain regions
US11469326B2 (en) * 2020-09-18 2022-10-11 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor devices and methods of fabrication thereof
US20230207655A1 (en) * 2021-12-24 2023-06-29 Intel Corporation Formation of metal contacts to silicon germanium layers with etch resistive cap layers

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201110352A (en) * 2009-09-01 2011-03-16 Taiwan Semiconductor Mfg Accumulation type FinFET, circuits and fabrication method thereof
US20110147713A1 (en) * 2009-12-23 2011-06-23 Ravi Pillarisetty Techniques for forming contacts to quantum well transistors

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7091075B2 (en) * 2004-07-09 2006-08-15 Atmel Corporation Fabrication of an EEPROM cell with SiGe source/drain regions
JP2006032542A (ja) * 2004-07-14 2006-02-02 Seiko Instruments Inc 半導体装置の製造方法
US20080121932A1 (en) * 2006-09-18 2008-05-29 Pushkar Ranade Active regions with compatible dielectric layers
US8878307B2 (en) * 2005-02-24 2014-11-04 Sony Corporation Shared contacts for MOSFET devices
US8811915B2 (en) * 2005-03-04 2014-08-19 Psion Inc. Digital wireless narrow band radio
JP2007214481A (ja) * 2006-02-13 2007-08-23 Toshiba Corp 半導体装置
CN200997401Y (zh) * 2006-05-12 2007-12-26 联华电子股份有限公司 金属氧化物半导体场效应晶体管
US7943469B2 (en) 2006-11-28 2011-05-17 Intel Corporation Multi-component strain-inducing semiconductor regions
US8217423B2 (en) * 2007-01-04 2012-07-10 International Business Machines Corporation Structure and method for mobility enhanced MOSFETs with unalloyed silicide
KR100864631B1 (ko) * 2007-02-23 2008-10-22 주식회사 하이닉스반도체 반도체 소자의 트랜지스터 및 그 제조 방법
KR101275025B1 (ko) * 2007-07-12 2013-06-14 삼성전자주식회사 반도체 소자용 배선 구조물 및 이의 형성방법
KR101408875B1 (ko) * 2008-04-18 2014-06-17 삼성전자주식회사 게르마늄 응축을 이용한 ｃｍｏｓ 트랜지스터 및 그제조방법
US8524562B2 (en) * 2008-09-16 2013-09-03 Imec Method for reducing Fermi-Level-Pinning in a non-silicon channel MOS device
US8115235B2 (en) * 2009-02-20 2012-02-14 Intel Corporation Modulation-doped halo in quantum well field-effect transistors, apparatus made therewith, and methods of using same
JP2010251344A (ja) 2009-04-10 2010-11-04 Hitachi Ltd 半導体装置およびその製造方法
CN101976667B (zh) * 2010-09-06 2012-07-18 清华大学 一种高性能cmos器件
WO2013095377A1 (en) 2011-12-20 2013-06-27 Intel Corporation Self-aligned contact metallization for reduced contact resistance

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201110352A (en) * 2009-09-01 2011-03-16 Taiwan Semiconductor Mfg Accumulation type FinFET, circuits and fabrication method thereof
US20110147713A1 (en) * 2009-12-23 2011-06-23 Ravi Pillarisetty Techniques for forming contacts to quantum well transistors

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI819254B (zh) * 2020-08-31 2023-10-21 台灣積體電路製造股份有限公司 半導體元件及其製造方法及類比數位轉換器

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